MCP6548 - Electronic component Microchip - Free user manual and instructions

USER MANUAL MCP6548 Microchip

Open-Drain Output Sub-Microamp Comparators

Features

• Low Quiescent Current: 600 nA/Comparator (typical)
  • Rail-to-Rail Input: V_SS - 0.3V to V_DD + 0.3V
• Open-Drain Output: V_OUT ≤ 10V
• Propagation Delay: 4 μs (typical, 100 mV Overdrive)
• Wide Supply Voltage Range: 1.6V to 5.5V
• Single Available in SOT-23-5, SC-70-5* Packages
  • Available in Single, Dual and Quad
  • Chip Select (CS) with MCP6548
• Low Switching Current
  • Internal Hysteresis: 3.3 mV (typical)
  • Temperature Ranges:
• Industrial: -40°C to +85°C
• Extended: -40°C to +125°C

Typical Applications

• Laptop Computers
• Mobile Phones
• Metering Systems
• Handheld Electronics
• RC Timers
  • Alarm and Monitoring Circuits
• Windowed Comparators
• Multivibrators

Related Devices

• CMOS/TTL-Compatible Output: MCP6541/2/3/4

Package Types

MCP6546
PDIP, SOIC, MSOP

MCP6546R MCP6547
SOT-23-5

Description

The Microchip MCP6546/6R/6U/7/8/9 family of comparators, is offered in single (MCP6546, MCP6546R, MCP6546U), single with Chip Select (CS) (MCP6548), dual (MCP6547) and quad (MCP6549) configurations. The outputs are open-drain and are capable of driving heavy DC or capacitive loads.

These comparators are optimized for low-power, single-supply application with greater than rail-to-rail input operation. The output limits supply current surges and dynamic power consumption while switching. The open-drain output of the MCP6546/6R/6U/7/8/9 family can be used as a level-shifter for up to 10V using a pull-up resistor. It can also be used as a wired-OR logic. The internal input hysteresis eliminates output switching due to internal noise voltage, reducing current draw. These comparators operate with a single-supply voltage as low as 1.6V and draw a quiescent current of less than 1 A/comparator.

The related Microchip MCP6541/2/3/4 family of comparators has a push-pull output that supports rail-to-rail output swing and interfaces with CMOS/TTL logic.

Note that SC-70-5 E-Temp parts are not available at this release of the data sheet.

The MCP6546U SOT-23-5 is E-Temp only.

MCP6546
SC-70-5, SOT23-5

MCP6546U
SC-70-5, SOT-23-5

MCP6548
PDIP, SOIC, MSOP

V_DD - V_SS 7.0V

Open-Drain Output. V_SS + 10.5V

Analog Input (V IN +, V IN -)††...... V SS - 1.0V to V DD + 1.0V

All Other Inputs and Outputs .... V SS - 0.3V to V DD + 0.3V

Difference Input Voltage .... |V_DD - V_SS|

Output Short-Circuit Current ......Continuous

Current at Input Pins ....±2 mA

Current at Output and Supply Pins ....±30 mA

Storage Temperature ( T_S )....-65°C to +150°C

Maximum Junction Temperature (TJ) ....+150°C

ESD Protection on all Pins:

(HBM;MM) 2 kV;200V (MCP6546U)

(HBM;MM) 4 kV; 200V (all other parts)

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

†† See Section 4.1.2 "Input Voltage and Current Limits".

DC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD = +1.6V to +5.5V , V_SS = GND , T_A = 25°C , V_IN + = V_DD/2 , V_IN - = V_SS , R_PU = 2.74 kΩ to V_PU = V_DD (Refer to Figure 1-3).
Parameters Sym Min	Typ Max Units		Conditions
Power Supply
Supply Voltage	V_DD	1.6	—	5.5	V	V_PU ≥ V_DD
Quiescent Current per Comparator	I_Q	0.3	0.6	1	μA	I_OUT = 0
Input
Input Voltage Range	V_CMR	V_SS-0.3	—	V_DD+0.3	V
Common-mode Rejection Ratio	CMRR	55	70	—	dB	V_DD = 5V , V_CM = -0.3V to 5.3V
Common-mode Rejection Ratio	CMRR	50	65	—	dB	V_DD = 5V , V_CM = 2.5V to 5.3V
Common-mode Rejection Ratio	CMRR	55	70	—	dB	V_DD = 5V , V_CM = -0.3V to 2.5V
Power Supply Rejection Ratio	PSRR	63	80	—	dB	V_CM = V_SS
Input Offset Voltage	V_OS	-7.0 ± 1.5	+7.0 mV		V	_CM = V_SS (Note 1)
Drift with Temperature	V_OS/ T_A	—	±3	— μV/°C		T_A = -40°C to +125°C , V_CM = V_SS
Input Hysteresis Voltage	V_HYST	1.5	3.3	6.5	mV	V_CM = V_SS (Note 1)
Linear Temp. Co.	TC_1	—	6.7	—	μV/°C	T_A = -40°C to +125°C , V_CM = V_SS (Note 2)
Quadratic Temp. Co. TC	2	—	-0.035	— μV/°C	^2	T_A = -40°C to +125°C , V_CM = V_SS (Note 2)
Input Bias Current	I_B	—	1	— pA	V	_CM = V_SS
At Temperature (I-Temp parts)	I_B	—	25	100	pA	T_A = +85°C , V_CM = V_SS (Note 3)
At Temperature (E-Temp parts)	I_B	—	1200	5000 pA	T	_A = +125°C , V_CM = V_SS (Note 3)
Input Offset Current	I_OS	—	±1	— pA	V	_CM = V_SS

Note 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the input-referred trip points.
2: V_HYST at differential temperatures is estimated using:
V_HYST(T_A)=V_HYST+(T_A-25^)TC_1+(T_A-25^)^2TC_2.
3: Input bias current at temperature is not tested for the SC-70-5 package.
4: Do not short the output above V_SS + 10V . Limit the output current to Absolute Maximum Rating of 30 mA. The minimum V_PU test limit was V_DD before Dec. 2004 (week code 52).

DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, V_DD = +1.6V to +5.5V , V_SS = GND , T_A = 25°C , V_IN+ = V_DD/2 , V_IN- = V_SS , R_PU = 2.74 k to V_PU = V_DD (Refer to Figure 1-3).
Parameters	Sym	Min	Typ	Max	Units	Conditions
Common-mode Input Impedance	Z_CM	—	10^13||4	— Ω||pF
Differential Input Impedance Z	DIFF	—	10^13||2	— Ω||pF
Open-Drain Output
Output Pull-Up Voltage V	PU	1.6 —	10 V (Note 4)
High-Level Output Current I	OH	-100 —	— nA V			_DD = 1.6V to 5.5V, V_PU = 10V (Note 4)
Low-Level Output Voltage	V_OL	V_SS	—	V_SS+0.2	V I	_OUT = 2 mA , V_PU = V_DD = 5V
Short-Circuit Current	I_SC	—	±1.5	—	mA	V_PU = V_DD = 1.6V (Note 4)
	I_SC	—	30 —	mA	V	_PU = V_DD = 5.5V (Note 4)
Output Pin Capacitance	C_OUT	—	8	— pF

Note 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the input-referred trip points.
2: V_HYST at differential temperatures is estimated using: V_HYST(T_A) = V_HYST + (T_A - 25^)TC_1 + (T_A - 25^)^2TC_2.
3: Input bias current at temperature is not tested for the SC-70-5 package.
4: Do not short the output above V_SS + 10V . Limit the output current to Absolute Maximum Rating of 30 mA. The minimum V_PU test limit was V_DD before Dec. 2004 (week code 52).

AC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD = +1.6V to +5.5V , V_SS = GND , T_A = 25°C , V_IN+ = V_DD/2 , Step = 200 mV, Overdrive = 100 mV, R_PU = 2.74 k to V_PU = V_DD , and C_L = 36 pF (Refer to Figure 1-2 and Figure 1-3).
Parameters	Sym	Min	Typ	Max	Units	Conditions
Fall Time	t_F	—	0.7	—	μs	(Note 1)
Propagation Delay (High-to-Low)	t_PHL	—	4.0 8.0 μs
Propagation Delay (Low-to-High)	t_PLH	—	3.0	8.0	μs	(Note 1)
Propagation Delay Skew	t_PDS	—	-1.0	—	μs	(Note 1 and Note 2)
Maximum Toggle Frequency	f_MAX	— 225	—	kHz	V	_DD = 1.6V
	f_MAX	— 165	—	kHz	V	_DD = 5.5V
Input Noise Voltage	E_ni	— 200	—	μV	_P-P	10 Hz to 100 kHz

Note 1: t_R and t_PLH depend on the load ( R_L and C_L ); these specifications are valid for the indicated load only.
2: Propagation Delay Skew is defined as: t_PDS = t_PLH - t_PHL .

MCP6548 CHIP SELECT (CS) CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD = +1.6V to +5.5V , V_SS = GND , T_A = 25°C , V_IN + = V_DD/2 , V_IN - = V_SS , R_PU = 2.74 k to V_PU = V_DD , and C_L = 36 pF (Refer to Figure 1-1 and Figure 1-3).
Parameters Sym Min	Typ Max	Units Conditions
Low Specifications
Logic Threshold, Low	V_IL	V_SS	—0.2	V_DD	V
Input Current, Low	I_CSL	—5 —	pA			= V_SS
High Specifications
Logic Threshold, High	V_IH	0.8 V_DD	—	V_DD	V
Input Current, High	I_CSH	—1 —	pA			= V_DD
Input High, V_DD Current	I_DD	—	18	—pA		= V_DD
Input High, GND Current	I_SS	—	-20	—	pA	= V_DD
Comparator Output Leakage	I_O(LEAK)	—1 —	pA			V_OUT = V_SS+10V , = V_DD
Dynamic Specifications
Low to Comparator Output Low Turn-on Time	t_ON	—2	50	ms		= 0.2V_DD to V_OUT = V_DD/2 , V_IN - = V_DD
High to Comparator Output High Z Turn-off Time	t_OFF	—	10	—	μs	= 0.8V_DD to V_OUT = V_DD/2 , V_IN - = V_DD
Hysteresis	V_CS\_HYST	—0.6	—	V		V_DD = 5V

CS V_IL V_IH t_ON t_OFF V_OUT High-Z High-Z I_SS -20 pA (typ.) -0.6 μA (typ.) -20 pA (typ.) I_CS 1 pA (typ.) 5 pA (typ.) 1 pA (typ.)

FIGURE 1-1: Timing Diagram for the CS pin on the MCP6548.

VIN- VIN+ = VDD/2 100 mV tPHL 100 mV tPLH VOH VOUT VOL VOL

FIGURE 1-2: Propagation Delay Timing Diagram.

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD = +1.6V to +5.5V and V_SS = GND .
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range T	_A	-40 —	+85 °C
Operating Temperature Range	T_A	-40 —	+125 °C	Note
Storage Temperature Range	T_A	-65 —	+150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SC-70	θ_JA	— 33	1 —	°C/W
Thermal Resistance, 5L-SOT-23	θ_JA	—	220.7	—	°C/W
Thermal Resistance, 8L-MSOP	θ_JA	—	211	— °C/W
Thermal Resistance, 8L-PDIP θ	JA	— 89	3 —	°C/W
Thermal Resistance, 8L-SOIC	θ_JA	—	149.5	—	°C/W
Thermal Resistance, 14L-PDIP	θ_JA	—	70	—	°C/W
Thermal Resistance, 14L-SOIC	θ_JA	— 95	3 —	°C/W
Thermal Resistance, 14L-TSSOP	θ_JA	— 100	—	°C/W

Note: The MCP6546/6R/6U/7/8/9 I-Temp family operates over this extended temperature range, but with reduced performance. In any case, the Junction Temperature ( T_J ) must not exceed the absolute maximum specification of +150°C.

1.1 Test Circuit Configuration

This test circuit configuration is used to determine the AC and DC specifications.

VDD 200 kΩ 200 kΩ VIN = VSS MCP654X VSS = 0V 100 kΩ VPU = VDD RPU = (2 mA)/ VDD VOUT =36 pF

FIGURE 1-3: AC and DC Test Circuit for the Open-Drain Output Comparators.

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, V_DD = +1.6V to +5.5V, V_SS = GND , T_A = +25^ , V_IN^+ = V_DD/2 , V_IN^- = GND , R_PU = 2.74 k to V_PU = V_DD , and C_L = 36 pF .

FIGURE 2-1: Input Offset Voltage at V_CM = V_SS .

FIGURE 2-4: Input Hysteresis Voltage at V_CM = V_SS .

FIGURE 2-2: Input Offset Voltage Drift at V_CM = V_SS .

FIGURE 2-5: Input Hysteresis Voltage Linear Temp. Co. (TC1) at VCM = VSS

FIGURE 2-3: The MCP6546/6R/6U/7/8/9 Comparators Show No Phase Reversal.

FIGURE 2-6: Input Hysteresis Voltage Quadratic Temp. Co. (TC 2 ) at V CM = V _SS .

Note: Unless otherwise indicated, V_DD = +1.6V to +5.5V, V_SS = GND , T_A = +25^ , V_IN^+ = V_DD/2 , V_IN^- = GND , R_PU = 2.74 k to V_PU = V_DD , and C_L = 36 pF .

FIGURE 2-7: Input Offset Voltage vs. Ambient Temperature at V_CM = V_SS .

FIGURE 2-10: Input Hysteresis Voltage vs. Ambient Temperature at V_CM = V_SS

FIGURE 2-8: Input Offset Voltage vs. Common-mode Input Voltage at V_DD = 1.6V .

FIGURE 2-11: Input Hysteresis Voltage vs. Common-mode Input Voltage at V_DD = 1.6V .

FIGURE 2-9: Input Offset Voltage vs. Common-mode Input Voltage at V_DD = 5.5V .

FIGURE 2-12: Input Hysteresis Voltage vs. Common-mode Input Voltage at V_DD = 5.5V .

Note: Unless otherwise indicated, V_DD = +1.6V to +5.5V, V_SS = GND , T_A = +25^ , V_IN^+ = V_DD/2 , V_IN^- = GND , R_PU = 2.74 k to V_PU = V_DD , and C_L = 36 pF .

FIGURE 2-13: CMRR, PSRR vs. Ambient Temperature.

FIGURE 2-16: Input Bias Current, Input Offset Current vs. Common-mode Input Voltage.

FIGURE 2-14: Input Bias Current, Input Offset Current vs. Ambient Temperature.

FIGURE 2-17: Quiescent Current vs. Power Supply Voltage.

FIGURE 2-15: Quiescent Current vs. Common-mode Input Voltage at V_DD = 1.6V .

FIGURE 2-18: Quiescent Current vs. Common-mode Input Voltage at V_DD = 5.5V .

Note: Unless otherwise indicated, V_DD = +1.6V to +5.5V, V_SS = GND , T_A = +25^ , V_IN^+ = V_DD/2 , V_IN^- = GND , R_PU = 2.74 k to V_PU = V_DD , and C_L = 36 pF .

FIGURE 2-19: Supply Current vs. Pull-Up Voltage.

FIGURE 2-22: Supply Current vs. Pull-Up to Supply Voltage Difference.

FIGURE 2-20: Supply Current vs. Toggle Frequency.

FIGURE 2-23: Output Short Circuit Current Magnitude vs. Power Supply Voltage.

FIGURE 2-21: Output Voltage Headroom vs. Output Current at V_DD = 1.6V .

FIGURE 2-24: Output Voltage Headroom vs. Output Current at V_DD = 5.5V .

Note: Unless otherwise indicated, V_DD = +1.6V to +5.5V, V_SS = GND , T_A = +25^ , V_IN^+ = V_DD/2 , V_IN^- = GND , R_PU = 2.74 k to V_PU = V_DD , and C_L = 36 pF .

FIGURE 2-25: High-to-Low Propagation Delay.

FIGURE 2-28: Low-to-High Propagation Delay.

FIGURE 2-26: Propagation Delay Skew.

FIGURE 2-29: Propagation Delay vs. Ambient Temperature.

FIGURE 2-27: Propagation Delay vs. Power Supply Voltage.

FIGURE 2-30: Propagation Delay vs. Input Overdrive.

Note: Unless otherwise indicated, V_DD = +1.6V to +5.5V, V_SS = GND , T_A = +25^ , V_IN^+ = V_DD/2 , V_IN^- = GND , R_PU = 2.74 k to V_PU = V_DD , and C_L = 36 pF .

FIGURE 2-31: Propagation Delay vs. Common-mode Input Voltage at V_DD = 1.6V .

FIGURE 2-34: Propagation Delay vs. Common-mode Input Voltage at V_DD = 5.5V .

FIGURE 2-32: Propagation Delay vs. Pull-up Resistor.

FIGURE 2-35: Propagation Delay vs. Load Capacitance.

FIGURE 2-33: Propagation Delay vs. Pull-up Voltage.

FIGURE 2-36: Output Leakage Current (CS = VDD) vs. Output Voltage (MCP6548 only).

Note: Unless otherwise indicated, V_DD = +1.6V to +5.5V, V_SS = GND , T_A = +25^ , V_IN^+ = V_DD/2 , V_IN^- = GND , R_PU = 2.74 k to V_PU = V_DD , and C_L = 36 pF .

FIGURE 2-37: Supply Current (Shoot-through Current) vs. Chip Select (CS) Voltage at V_DD = 1.6V (MCP6548 only).

FIGURE 2-40: Supply Current (Shoot-through Current) vs. Chip Select (CS) Voltage at V_DD = 5.5V (MCP6548 only).

FIGURE 2-38: Supply Current (Charging Current) vs. Chip Select (CS) Pulse at V_DD = 1.6V (MCP6548 only).

FIGURE 2-41: Supply Current (Charging Current) vs. Chip Select (CS) Pulse at V_DD = 5.5V (MCP6548 only).

FIGURE 2-39: Chip Select (CS) Step Response (MCP6548 only).

FIGURE 2-42: Input Bias Current vs. Input Voltage.

3.0 PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP6546	MCP6546	MCP6546R	MCP6546U	MCP6547	MCP6548	MCP6549	Symbol Description
PDIP, SOIC, MSOP	SC-70, SOT-23	SOT-23-5	SC-70, SOT-23-5	PDIP, SOIC, MSOP	PDIP, SOIC, MSOP	PDIP, SOIC, TSSOP
6 1 1	4 1 6 1	OUT, OUTA		Digital Output (Comparator A)
2 4 4	3 2 2 2	V					_IN^-, V_INA^- Inverting Input (Comparator A)
3 3 3	1 3 3 3	V					_IN^+, V_INA^+ Noninverting Input (Comparator A)
7 5 2	5 8 7 4		V				_DD Positive Power Supply
—	—	—	—	5	—	5	V_INB^+ Noninverting Input (Comparator B)
—	—	—	—	6	—	6	V_INB^- Inverting Input (Comparator B)
—	—	—	—	7	—	7	OUTB Digital Output (Comparator B)
—	—	—	—	—	—	8	OUTC Digital Output (Comparator C)
—	—	—	—	—	—	9	V_INC^- Inverting Input (Comparator C)
—	—	—	—	—	—	10	V_INC^+ Noninverting Input (Comparator C)
4 2 5	2 4 4	11	V				_SS Negative Power Supply
—	—	—	—	—	—	12	V_IND^+ Noninverting Input (Comparator D)
—	—	—	—	—	—	13	V_IND^- Inverting Input (Comparator D)
—	—	—	—	—	—	14	OUTD Digital Output (Comparator D)
—	—	—	—	—	8	—	_CS Chip Select
1, 5, 8	—	—	—	—	1, 5	—	NCNo Internal Connection

3.1 Analog Inputs

The comparator noninverting and inverting inputs are high-impedance CMOS inputs with low bias currents.

3.2 CS Digital Input

This is a CMOS, Schmitt-triggered input that places the part into a low-power mode of operation.

3.3 Digital Outputs

The comparator outputs are CMOS, open-drain digital outputs. They are designed to make level shifting and wired-OR easy to implement.

3.4 Power Supply (V SS and VDD)

The positive power supply pin ( V_DD ) is 1.6V to 5.5V higher than the negative power supply pin ( V_SS ). For normal operation, the other pins are at voltages between V_SS and V_DD , except the output pins which can be as high as 10V above V_SS .

Typically, these parts are used in a single (positive) supply configuration. In this case, V_SS is connected to ground and V_DD is connected to the supply. V_DD will need a local bypass capacitor (typically 0.01 F to 0.1 F) within 2 mm of the V_DD pin. These pins can share a bulk capacitor with nearby analog parts (within 100 mm), but it is not required.

4.0 APPLICATION INFORMATION

The MCP6546/6R/6U/7/8/9 family of push-pull output comparators are fabricated on Microchip's state-of-the-art CMOS process. They are suitable for a wide range of applications requiring very low-power consumption.

4.1 Comparator Inputs

4.1.1 PHASE REVERSAL

The MCP6546/6R/6U/7/8/9 comparator family uses CMOS transistors at the input. They are designed to prevent phase inversion when the input pins exceed the supply voltages. Figure 2-3 shows an input voltage exceeding both supplies with no resulting phase inversion.

4.1.2 INPUT VOLTAGE AND CURRENT LIMITS

The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors, and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below V_SS . They also clamp any voltages that go too far above V_DD ; their breakdown voltage is high enough to allow normal operation, and low enough to bypass ESD events within the specified limits.

graph TD
    A["V_DD"] --> B["Bond Pad"]
    C["V_IN+"] --> D["Bond Pad"]
    E["V_SS"] --> F["Bond Pad"]
    B --> G["Input Stage"]
    D --> G
    F --> G
    G --> H["Bond Pad"]
    H --> I["V_IN-"]

FIGURE 4-1: Simplified Analog Input ESD Structures.

In order to prevent damage and/or improper operation of these amplifiers, the circuits they are in must limit the currents (and voltages) at the V_IN^+ and V_IN^- pins (see Absolute Maximum Ratings at the beginning of Section 1.0 “Electrical Characteristics”). Figure 4-3 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins ( V_IN^+ and V_IN^- ) from going too far below ground, and the resistors R_1 and R_2 limit the possible current drawn out of the input pin. Diodes D_1 and D_2 prevent the input pin ( V_IN^+ and V_IN^- ) from going too far above V_DD . When implemented as shown, resistors R_1 and R_2 also limit the current through D_1 and D_2 .

VDD D1 + MCP6G0X - V1 R1 D2 R2 R3 V2 VOUT R1 ≥ VSS - (minimum expected V1) / 2 mA R2 ≥ VSS - (minimum expected V2) / 2 mA

FIGURE 4-2: Protecting the Analog Inputs.

It is also possible to connect the diodes to the left of the resistors R_1 and R_2 . In this case, the currents through diodes D_1 and D_2 need to be limited by some other mechanism. The resistor then serves as in-rush current limiter; the DC current into the input pins ( V_IN^+ and V_IN^- ) should be very small.

A significant amount of current can flow out of the inputs when the Common-mode voltage ( V_CM ) is below ground ( V_SS ); see Figure 2-42. Applications that are high-impedance may need to limit the usable voltage range.

The input stage of this family of devices uses two differential input stages in parallel: one operates at low input voltages and the other at high input voltages. With this topology, the input voltage is 0.3V above V_DD and 0.3V below V_SS . The input offset voltage is measured at both V_SS - 0.3V and V_DD + 0.3V to ensure proper operation.

The MCP6546/6R/6U/7/8/9 family has internally set hysteresis that is small enough to maintain input offset accuracy (<7 mV), and large enough to eliminate output chattering caused by the comparator's own input noise voltage (200 V_p-P ). Figure 4-3 illustrates this capability.

FIGURE 4-3: The MCP6546/6R/6U/7/8/9 Comparators' Internal Hysteresis Eliminates Output Chatter Caused by Input Noise Voltage.

4.2 Open-Drain Output

The open-drain output is designed to make level-shifting and wired-OR logic easy to implement. The output can go as high as 10V for 9V battery-powered applications. The output stage minimizes switching current (shoot-through current from supply-to-supply) when the output changes state. See Figure 2-15, Figure 2-18 and Figure 2-37 through Figure 2-41 for more information.

4.3 MCP6548 Chip Select (CS)

The MCP6548 is a single comparator with a Chip Select (CS) pin. When CS is pulled high, the total current consumption drops to 20 pA (typical). 1 pA (typical) flows through the CS pin, 1 pA (typical) flows through the output pin and 18 pA (typical) flows through the V_DD pin, as shown in Figure 1-1. When this happens, the comparator output is put into a high-impedance state. By pulling CS low, the comparator is enabled. If the CS pin is left floating, the comparator will not operate properly. Figure 1-1 shows the output voltage and supply current response to a CS pulse.

The internal circuitry is designed to minimize glitches when cycling the pin. This helps conserve power, which is especially important in battery-powered applications.

4.4 Externally Set Hysteresis

Greater flexibility in selecting hysteresis, or input trip points, is achieved by using external resistors.

Input offset voltage ( V_OS ) is the center (average) of the (input-referred) low-high and high-low trip points. Input hysteresis voltage ( V_HYST ) is the difference between the same trip points. Hysteresis reduces output chattering when one input is slowly moving past the other, thus reducing dynamic supply current. It also helps in systems where it is best not to cycle between states too frequently (e.g., air conditioner thermostatic control).

4.4.1 INVERTING CIRCUIT

Figure 4-4 shows an inverting circuit for a single-supply application using three resistors, besides the pull-up resistor. The resulting hysteresis diagram is shown in Figure 4-5.

VDD VPU IPU RPU MCP654X + - VIN VDD R2 R3 IOL IRF RF VOUT

FIGURE 4-4: Inverting Circuit with Hysteresis.

FIGURE 4-5: Hysteresis Diagram for the Inverting Circuit.

In order to determine the trip voltages ( V_THL and V_TLH ) for the circuit shown in Figure 4-4, R_2 and R_3 can be simplified to the Thevenin equivalent circuit with respect to V_DD as shown in Figure 4-6.

MCP654X V23○—R23—●—R_F + V_PU R_PU V_OUT

FIGURE 4-6: Thevenin Equivalent Circuit.

EQUATION 4-1:

$$ R _ {2 3} = \frac {R _ {2} R _ {3}}{R _ {2} + R _ {3}} $$

$$ V _ {2 3} = \frac {R _ {3}}{R _ {2} + R _ {3}} \times V _ {D D} $$

Using this simplified circuit, the trip voltage can be calculated using the following equation:

EQUATION 4-2:

$$ V _ {T H L} = V _ {P U} \left(\frac {R _ {2 3}}{R _ {2 3} + R _ {F} + R _ {P U}}\right) + V _ {2 3} \left(\frac {R _ {F} + R _ {P U}}{R _ {2 3} + R _ {F} + R _ {P U}}\right) $$

$$ V _ {T L H} = V _ {O L} \left(\frac {R _ {2 3}}{R _ {2 3} + R _ {F}}\right) + V _ {2 3} \left(\frac {R _ {F}}{R _ {2 3} + R _ {I ^ {\prime}}}\right) $$

V_TLH= trip voltage from low to high

V_THL = trip voltage from high to low

Figure 2-21 and Figure 2-24 can be used to determine typical values for V_OL . This voltage is dependent on the output current I_OL as shown in Figure 4-4. This current can be determined using the equation below:

EQUATION 4-3:

$$ I _ {O L} = I _ {P U} + I _ {R F} $$

$$ I _ {O L} = \left(\frac {V _ {P U} - V _ {O L}}{R _ {P U}}\right) + \left(\frac {V _ {2 3} - V _ {O L}}{R _ {2 3} + R _ {F}}\right) $$

V_OH can be calculated using the equation below:

EQUATION 4-4:

$$ V _ {O H} = (V _ {P U} - V _ {2 3}) \times \left(\frac {R _ {2 3} + R _ {F}}{R _ {2 3} + R _ {F} + R _ {P U}}\right) $$

As explained in Section 4.1 "Comparator Inputs", it is important to keep the noninverting input below V_DD + 0.3V when V_PU > V_DD .

4.5 Supply Bypass

With this family of comparators, the power supply pin ( V_DD for single supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good edge-rate performance.

4.6 Capacitive Loads

Reasonable capacitive loads (e.g., logic gates) have little impact on propagation delay (see Figure 2-27). The supply current increases with increasing toggle frequency (Figure 2-30), especially with higher capacitive loads.

4.7 Battery Life

In order to maximize battery life in portable applications, use large resistors and small capacitive loads. Avoid toggling the output more than necessary. Do not use Chip Select (CS) too frequently, in order to conserve power. Capacitive loads will draw additional power at start-up.

4.8 PCB Surface Leakage

In applications where low input bias current is critical, PCB (Printed Circuit Board) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 10^12 . A 5V difference would cause 5 pA of current to flow. This is greater than the MCP6546/6R/6U/7/8/9 family's bias current at 25^ (1 pA, typical).

The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-7.

V_{IN^-} V_{IN^+} V_{SS} Guard Ring

FIGURE 4-7: Example Guard Ring Layout for Inverting Circuit.

For the Inverting Configuration (Figure 4-4 and Figure 4-7):

a) Connect the guard ring to the noninverting input pin ( V_IN^+ ). This biases the guard ring to the same reference voltage as the comparator (e.g., V_DD/2 or ground).
b) Connect the inverting pin (V IN-) to the input pad, without touching the guard ring.

4.9 Unused Comparators

An unused amplifier in a quad package (MCP6549) should be configured as shown in Figure 4-8. This circuit prevents the output from toggling and causing crosstalk. It uses the minimum number of components and draws minimal current (see Figure 2-15 and Figure 2-18).

½ MCP6549 VDD - + +

FIGURE 4-8: Unused Comparators.

4.10 Typical Applications

4.10.1 PRECISE COMPARATOR

Some applications require higher DC precision. An easy way to solve this problem is to use an amplifier (such as the MCP6041) to gain-up the input signal before it reaches the comparator. Figure 4-9 shows an example of this approach.

VDD VREF + MCP6041 - VIN R1 R2 VREF + VDD VPU RPU MCP6546 VOUT

FIGURE 4-9: Precise Inverting Comparator.

4.10.2 WINDOWED COMPARATOR

Figure 4-10 shows one approach to designing a windowed comparator. The wired-OR connection produces a high output (logic 1) when the input voltage is between V_RB and V_RT (where V_RT > V_RB ).

FIGURE 4-10: Windowed Comparator.

5.0 PACKAGING INFORMATION

5.1 Package Marking Information

5-Lead SC-70 (MCP6546, MCP6546U)

Example: (I-temp)

Device

I-Temp

Code

E-Temp

Code

MCP6546 ACNN Note 2

MCP6546U BBNN Note 2

Note 1: I-Temp parts prior to March 2005 are marked "ACN"

2: SC-70-5 E-Temp parts not available at this release of the data sheet.

AC25

5-Lead SOT-23 (MCP6546, MCP6546R, MCP6546U)

Example: (I-temp)

Device

I-Temp

Code

E-Temp

Code

MCP6546 ACNN GWNN

MCP6546R AHNN

GXNN

MCP6546U

一

AWNN

Note: Applies to 5-Lead SOT-23

AC25

8-Lead PDIP (300 mil) (MCP6546, MCP6547, MCP6548, MCP6549)

Examples:

MCP6546

I/P256

1148

MCP6546

I/P ^R2 256

1148

8-Lead SOIC (150 mil) (MCP6546, MCP6547, MCP6548, MCP6549)

MCP6547

I/SN1148

256

OR

MCP6547

SNe31148

256

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week '01')

NNN Alphanumeric traceability code

e3 Pb-free JEDEC designator for Matte Tin (Sn)

* This package is Pb-free. The Pb-free JEDEC designator ( )

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.

Package Marking Information (Continued)

8-Lead MSOP (MCP6546, MCP6547, MCP6548) Example:

65461 148256

14-Lead PDIP (300 mil) (MCP6549) Example:

XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN

MCP6549-I/P 1148256

OR

MCP6549-E/P e3 1148256

OR

MCP6549 I/P83 1148256

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week '01')

NNN Alphanumeric traceability code

ePb-free JEDEC designator for Matte Tin (Sn)

* This package is Pb-free. The Pb-free JEDEC designator (e3)

Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.

Package Marking Information (Continued)

Example:14-Lead SOIC (150 mil) (MCP6549)

XXXXXXXXXXXX XXXXXXXXXXXX ○ YYWWNNN

MCP6549ISL 1148256

OR

MCP6549 E/SL® 1148256

14-Lead TSSOP (MCP6549) Example:

Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week '01') NNN Alphanumeric traceability code ePb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator (e3)

Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.

5-Lead Plastic Small Outline Transistor (LT) [SC70]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

D b 3 2 1 E1 E 4 e 5

Isometric line drawing of an integrated circuit chip with three leads (no text or symbols)

A A2 A1

C L

Units		MILLIMETERS
Dimension Limitss		MINsNOMsMAX
Number of Pins	Ns	5
Pitchses0.65 BSC
Overall HeightsAs0.80 -	1.10
Molded Package Thickness	A2	0.80	-	1.00
Standoff	A1	0.00	-	0.10
Overall Width	Es1.80	2.10	2.40
Molded Package Width	E1	1.15	1.25	1.35
Overall Length	D	1.80	2.00	2.25
Foot Length	L	0.10	0.20	0.46
Lead Thickness	c	0.08	-	0.26
Lead Width	b	0.15	-	0.40

Notes:

1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.

2.sDimensioning and tolerancing per ASME Y14.5M.

BSC:sBasic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-061B

5-Lead Plastic Small Outline Transistor (LT) [SC70]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

E Gx 3 2 1 C G 4 5 Y X SILK SCREEN

RECOMMENDED LAND PATTERN

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Contact Pitch	E	0.65 BSC
Contact Pad Spacing	C		2.20
Contact Pad Width	X			0.45
Contact Pad Length	Y			0.95
Distance Between Pads	G	1.25
Distance Between Pads	Gx	0.20

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2061A

5-Lead Plastic Small Outline Transistor (OT) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Units		MILLIMETERS
Dimension Limitss		MINsNOMsMAX
Number of Pins	Ns	5
Lead Pitchses0.95 BSC
Outside Lead Pitchse1s1.90 BSC
Overall HeightsA 0.90 -		1.45
Molded Package Thickness	A2	0.89	-	1.30
Standoff	A1	0.00	-	0.15
Overall Width	E	2.20	-	3.20
Molded Package Width	E1	1.30	-	1.80
Overall Length	D	2.70	-	3.10
Foot Length	L	0.10	-	0.60
Footprint	L1	0.35	-	0.80
Foot Angle		0°	-	30°
Lead Thickness	c	0.08	-	0.26
Lead Width	b	0.20	-	0.51

Notes:

1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.
   2.sDimensioning and tolerancing per ASME Y14.5M.

BSC:sBasic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-091B

5-Lead Plastic Small Outline Transistor (OT) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

X Y Z C G SILK SCREEN E GX

RECOMMENDED LAND PATTERN

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Contact Pitch	E	0.95 BSC
Contact Pad Spacing	C		2.80
Contact Pad Width (X5)	X			0.60
Contact Pad Length (X5)	Y			1.10
Distance Between Pads	G	1.70
Distance Between Pads	GX	0.35
Overall Width	Z			3.90

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091A

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Units		INCHES
Dimension Limitss		MINsNOMsMAX
Number of Pins	Ns	8
Pitchses.100 BSC
Top to Seating PlanesAs-s-s.210
Molded Package Thickness	A2	.115	.130	.195
Base to Seating Plane	A1	.015s-s-
Shoulder to Shoulder Width	E	.290	.310	.325
Molded Package Width	E1	.240	.250	.280
Overall Length	D	.348	.365	.400
Tip to Seating Plane	L	.115	.130	.150
Lead Thickness	c	.008	.010	.015
Upper Lead Width	b1	.040	.060	.070
Lower Lead Width	b	.014	.018	.022
Overall Row Spacing §	eB	-s-s.430

Notes:

1. sPin 1 visual index feature may vary, but must be located with the hatched area.
   2.s§ Significant Characteristic.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
   4.sDimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-018B

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Microchip Technology Drawing No. C04-057C Sheet 1 of 2

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Isometric line drawing of an integrated circuit chip with multiple pins (no text or symbols)

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Number of Pins	N	8
Pitch	e	1.27 BSC
Overall Height	A	-	-	1.75
Molded Package Thickness	A2	1.25	-	-
Standoff §	A1	0.10	-	0.25
Overall Width	E	6.00 BSC
Molded Package Width	E1	3.90 BSC
Overall Length	D	4.90 BSC
Chamfer (Optional)	h	0.25	-	0.50
Foot Length	L	0.40	-	1.27
Footprint	L1	1.04 REF
Foot Angle		0°	-	8°
Lead Thickness	c	0.17	-	0.25
Lead Width	b	0.31	-	0.51
Mold Draft Angle Top		5°	-	15°
Mold Draft Angle Bottom		5°	-	15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing No. C04-057C Sheet 2 of 2

8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

E C SILK SCREEN Y1 X1

RECOMMENDED LAND PATTERN

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Contact Pitch	E	1.27 BSC
Contact Pad Spacing	C		5.40
Contact Pad Width (X8)	X1			0.60
Contact Pad Length (X8)	Y1			1.55

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-2057A

8-Lead Plastic Micro Small Outline Package (MS) [MSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

2X 0.20 H D/2 A E/2 D E1 E1/2 N E E NOTE 1 1 2 N/2 0.25 C e B NX b ⊕ 0.13 M C A-B D TOP VIEW A A2 A1 SIDE VIEW C 0.10 C SEE DETAIL C END VIEW

Microchip Technology Drawing C04-111C Sheet 1 of 2

8-Lead Plastic Micro Small Outline Package (MS) [MSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

SEATING PLANE C L (L1) GAUGE PLANE c φ

DETAIL C

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Number of Pins	N		8
Pitch	e	0.65 BSC
Overall Height	A	-	-	1.10
Molded Package Thickness	A2	0.75	0.85	0.95
Standoff	A1	0.00	-	0.15
Overall Width	E	4.90 BSC
Molded Package Width	E1	3.00 BSC
Overall Length	D	3.00 BSC
Foot Length	L	0.40	0.60	0.80
Footprint	L1	0.95 REF
Foot Angle		0^	-	8^
Lead Thickness	c	0.08	-	0.23
Lead Width	b	0.22	-	0.40

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-111C Sheet 2 of 2

14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

NOTE 1 2X 0.10 C D NOTE 5 N E1 1 2 3 e B NOTE 5 D A D E 0.10 C A-B 2X 0.20 C 2X N/2 TIPS NX b ⊕ 0.25① C A-B D

TOP VIEW

// 0.10 C A A2 A1 SIDE VIEW 0.10 C NX SEATING PLANE C A

h H SEE VIEW C c

VIEW A-A

Microchip Technology Drawing No. C04-065C Sheet 1 of 2

14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

α 4X Θ φ L (L1) 4X β

Isometric line drawing of an integrated circuit chip with multiple pins (no text or symbols)

VIEW C

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Number of Pins	N	14
Pitch	e	1.27 BSC
Overall Height	A	-	-	1.75
Molded Package Thickness	A2	1.25	-	-
Standoff §	A1	0.10	-	0.25
Overall Width	E	6.00 BSC
Molded Package Width	E1	3.90 BSC
Overall Length	D	8.65 BSC
Chamfer (Optional)	h	0.25	-	0.50
Foot Length	L	0.40	-	1.27
Footprint	L1	1.04 REF
Lead Angle		0°	-	-
Foot Angle		0°	-	8°
Lead Thickness	c	0.10	-	0.25
Lead Width	b	0.31	-	0.51
Mold Draft Angle Top		5°	-	15°
Mold Draft Angle Bottom		5°	-	15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimension D does not include mold flash, protrusions or gate burrs, which shall not exceed 0.15 mm per end. Dimension E1 does not include interlead flash or protrusion, which shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.

Microchip Technology Drawing No. C04-065C Sheet 2 of 2

14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Gx C G SILK SCREEN Y E X

RECOMMENDED LAND PATTERN

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Contact Pitch	E	1.27 BSC
Contact Pad Spacing	C		5.40
Contact Pad Width	X			0.60
Contact Pad Length	Y			1.50
Distance Between Pads	Gx	0.67
Distance Between Pads	G	3.90

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2065A

14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Microchip Technology Drawing C04-087C Sheet 1 of 2

14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Isometric line drawing of an integrated circuit chip with multiple pins (no text or symbols)

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Number of Pins	N	14
Pitch	e	0.65 BSC
Overall Height	A	-	-	1.20
Molded Package Thickness	A2	0.80	1.00	1.05
Standoff	A1	0.05	-	0.15
Overall Width	E	6.40 BSC
Molded Package Width	E1	4.30	4.40	4.50
Molded Package Length	D	4.90	5.00	5.10
Foot Length	L	0.45	0.60	0.75
Footprint	(L1)	1.00 REF
Foot Angle	φ	0°	-	8°
Lead Thickness	c	0.09	-	0.20
Lead Width	b	0.19	-	0.30

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing No. C04-087C Sheet 2 of 2

14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

C1 E G X1 Y1 SILK SCREEN

RECOMMENDED LAND PATTERN

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Contact Pitch	E	0.65 BSC
Contact Pad Spacing	C1		5.90
Contact Pad Width (X14)	X1			0.45
Contact Pad Length (X14)	Y1			1.45
Distance Between Pads	G	0.20

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2087A

APPENDIX A: REVISION HISTORY

Revision H (November 2022)

The following is the list of modifications:

• Updated Section 5.1, Package Marking Information
• Made minor formatting changes throughout the document.

Revision G (February 2012)

The following is the list of modifications:

• Updated the Package Types drawing to correct the device representation of the SC-70 package.
• Updated package temperatures in the Temperature Characteristics table.
• Corrected the marking information table for the 5-Lead SC-70 package (MCP6546 and MCP6546U) in Section 5.1, Package Marking Information.
• Updated the package outline drawings in Section 5.1, Package Marking Information, to show all views for each package.
• Minor editorial changes.

Revision F (September 2007)

The following is the list of modifications:

• Corrected polarity of MCP6546U SOT-23-5 pin-out diagram on the first page.
• Updated package outline drawings in Section 5.1, Package Marking Information per Marcom.

Revision E (September 2006)

The following is the list of modifications:

• Added MCP6546U pinout for the SOT-23-5 package.
• Clarified Absolute Maximum Analog Input Voltage and Current Specifications.
• Added application information on unused comparators.
• Added disclaimer to package outline drawings.

Revision D (May 2006)

The following is the list of modifications:

• Added E-Temp parts.
• Changed minimum pull-up voltage specification (V_PU) to 1.6V for parts starting Dec. 2004 (week code 52); previous parts are specified at a minimum of V_DD .
• Changed V_HYST temperature specifications to linear and quadratic temperature coefficients.
• Changed specifications and plots to include E-Temp parts.
• Added Section 3.0, Pin Descriptions.
• Corrected package markings (Section 5.1, Package Marking Information).
• Added Appendix A: "Revision History".

Revision C (May 2003)

- Undocumented changes.

Revision B (December 2002)

- Undocumented changes.

Revision A (February 2002)

• Original Release of this Document.

NOTES:

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device

Temperature Range

Package

Device: MCP6546: Single Comparator

MCP6546T: Single Comparator (Tape and Reel) (SC-70, SOT-23, SOIC, MSOP)

MCP6546RT: Single Comparator (Rotated - Tape and Reel) (SOT-23 only)

MCP6546UT: Single Comparator (Tape and Reel) (SC-70, SOT-23)(SOT-23-5 is E-Temp only)

MCP6547: Dual Comparator

MCP6547T: Dual Comparator

(Tape and Reel for SOIC and MSOP)

MCP6548: Single Comparator with CS

MCP6548T: Single Comparator with CS

(Tape and Reel for SOIC and MSOP)

MCP6549: Quad Comparator

MCP6549T: Quad Comparator

(Tape and Reel for SOIC and TSSOP)

Temperature Range: I = -40^ to +85^

E^*=-40^ to +125^

* SC-70-5 E-Temp parts not available at this release of the data sheet.

Package: LT = Plastic Package (SC-70), 5-lead

OT = Plastic Small Outline Transistor (SOT-23), 5-lead

MS = Plastic MSOP, 8-lead

P = Plastic DIP (300 mil Body), 8-lead, 14-lead

SN = Plastic SOIC (150 mil Body), 8-lead

SL = Plastic SOIC (150 mil Body), 14-lead (MCP6549)

ST = Plastic TSSOP (4.4mm Body), 14-lead (MCP6549)

Examples:

a) MCP6546T-I/LT: Tape and Reel, Industrial Temperature, 5LD SC-70.

b) MCP6546T-I/OT: Tape and Reel, Industrial Temperature, 5LD SOT-23.

c) MCP6546-I/MS: Tape and Reel, Industrial Temperature, 8LD MSOP.

d) MCP6546-E/P: Extended Temperature, 8LD PDIP.

e) MCP6546-E/SN: Extended Temperature, 8LD SOIC.

a) MCP6546RT-I/OT: Tape and Reel, Industrial Temperature, 5LD SOT23.

a) MCP6546UT-E/LT: Tape and Reel, Industrial Temperature, 5LD SC-70

b) MCP6546UT-E/OT: Tape and Reel, Extended Temperature, 5LD SOT23.

a) MCP6547-I/MS: Industrial Temperature, 8LD MSOP.

b) MCP6547T-I/MS: Tape and Reel, Industrial Temperature, 8LD MSOP.

c) MCP6547-I/P: Industrial Temperature, 8LD PDIP.

d) MCP6547-E/SN: Extended Temperature, 8LD SOIC.

a) MCP6548-I/SN: Industrial Temperature, 8LD SOIC.

b) MCP6548T-I/SN: Tape and Reel, Industrial Temperature, 8LD SOIC.

c) MCP6548-I/P: Industrial Temperature, 8LD PDIP.

d) MCP6548-E/SN: Extended Temperature, 8LD SOIC.

a) MCP6549T-I/SL: Tape and Reel, Industrial Temperature, 14LD SOIC.

b) MCP6549T-E/SL: Tape and Reel, Extended Temperature, 14LD SOIC.

c) MCP6549-I/P: Industrial Temperature, 14LD PDIP.

d) MCP6549-E/ST: Extended Temperature, 14LD TSSOP.

NOTES:

Note the following details of the code protection feature on Microchip products:

• Microchip products meet the specifications contained in their particular Microchip Data Sheet.
- Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions.
- Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
- Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is "unbreakable" Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products.

This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this information in any other manner violates these terms. Information regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at https://www.microchip.com/en-us/support/design-help/client-support-services.

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Trademarks

The Microchip name and logo, the Microchip logo, Adaptec, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, Trusted Time, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

© 2002-2022, Microchip Technology Incorporated and its subsidiaries.

All Rights Reserved.

ISBN: 978-1-6683-1529-3

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