AT86RF231 - Electronic component Microchip - Free user manual and instructions

USER MANUAL AT86RF231 Microchip

– Receiver Sensitivity -101 dBm

- Programmable Output Power from -17 dBm up to +3 dBm

• Ultra-Low Current Consumption:

- SLEEP = 0.02 μA

- TRX_OFF = 0.4 mA

- RX_ON = 12.3 mA

- BUSY_TX = 14 mA (at max. Transmit Power of +3 dBm)

- Ultra-Low Supply Voltage (1.8V to 3.6V) with Internal Regulator

- Optimized for Low BoM Cost and Ease of Production:

– Few External Components Necessary (Crystal, Capacitors and Antenna)

– Excellent ESD Robustness

- Easy to Use Interface:

- Registers, Frame Buffer and AES Accessible through Fast SPI

- Only Two Microcontroller GPIO Lines Necessary

– One Interrupt Pin from Radio Transceiver

– Clock Output with Prescaler from Radio Transceiver

• Radio Transceiver Features:

- 128-byte FIFO (SRAM) for Data Buffering

- Programmable Clock Output, to Clock the Host Microcontroller or as Timer Reference

- Integrated RX/TX Switch

– Fully Integrated, Fast Settling PLL to support Frequency Hopping

- Battery Monitor

– Fast Wake-Up Time < 0.4 msec

• Special IEEE 802.15.4-2006 Hardware Support:

– FCS Computation and Clear Channel Assessment

– RSSI Measurement, Energy Detection and Link Quality Indication

• MAC Hardware Accelerator:

– Automated Acknowledgement, CSMA-CA and Retransmission

- Automatic Address Filtering

- Automated FCS Check

- Extended Feature Set Hardware Support:

– AES 128-bit Hardware Accelerator

– RX/TX Indication (external RF Front-End Control)

- RX Antenna Diversity

– Supported PSDU data rates: 250 kb/s, 500 kb/s, 1 Mb/s and 2 Mb/s

– True Random Number Generation for Security Application

- Industrial and Extended Temperature Range:

-40^ to +85^ and -40^ to +125^

• I/O and Packages:

- 32-pin Low-Profile QFN Package 5 × 5 × 0.9 ~mm^3

- RoHS/Fully Green

• Compliant to IEEE 802.15.4-2006 and IEEE 802.15.4-2003

- Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-T66, RSS-210

ATMEL®

AVR®

Low Power

2.4 GHz

Transceiver for

ZigBee,

IEEE 802.15.4,

6LoWPAN,

RF4CE, SP100,

WirelessHART,

and ISM

Applications

AT86RF231-ZU

AT86RF231-ZF

1. Pin-out Diagram

Figure 1-1. AT86RF231 Pin-out Diagram

AVSS AVSS AVSS AVDD EVDD AVSS XTAL1 XTAL2 32 31 30 29 28 27 26 25 DIG3 1 24 IRQ DIG4 2 AVSS /SEL MOSI AVSS 3 AT86RF231 RFP 4 DVSS RFN 5 MISO AVSS 6 SCLK DVSS 7 DVSS /RST 8 CLKM 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 DIG1 DIG2 SLP_TR DVSS DVDD DVDD DEVDD DVSS

Note: The exposed paddle is electrically connected to the die inside the package. It shall be soldered to the board to ensure electrical and thermal contact and good mechanical stability.

1.1 Pin Descriptions

Table 1-1. Pin Description AT86RF231

Pins Name Type Description
1 DIG3	Digital output (Ground)		1. RX/TX Indicator, see Section 11.52. If disabled, pull-down enabled (AVSS)
2 DIG4	Digital output (Ground)		1. RX/TX indicator (DIG3 inverted), see Section 11.52. If disabled, pull-down enabled (AVSS)
3 AVS	S Ground Ground for RF signals
4 RFP	RF I/O Differential RF signal
5 RFN	RF I/O Differential RF signal
6 AVS	S Ground Ground for RF signals
7 DVSS	S Ground Digital ground
8 /RST	Digital input Chip reset		active low
9 DIG1	Digital output (Ground)		1. Antenna Diversity RF switch control, see Section 11.42. If disabled, pull-down enabled (DVSS)
10	DIG2 Digital output (Ground)		1. Antenna Diversity RF switch control (DIG1 inverted), see Section 11.42. Signal IRQ_2 (RX_START) for RX Frame Time Stamping, see Section 11.63. If functions disabled, pull-down enabled (DVSS)
11	SLP_TR	Digital input	Controls sleep, transmit start, receive states; active high, see Section 6.5
12	DVSS Ground Digital ground
13	DVDD	Supply	Regulated 1.8V voltage regulator; digital domain, see Section 9.4
14	DVDD	Supply	Regulated 1.8V voltage regulator; digital domain, see Section 9.4
15	DEVDD	Supply	External supply voltage; digital domain
16	DVSS Ground Digital ground
17	CLKM	Digital output	Master clock signal output; low if disabled, see Section 9.6
18	DVSS Ground Digital ground
19	SCLK	Digital input	SPI clock
20	MISO Digital output SPI data output (Master Input Slave Output)
21	DVSS Ground Digital ground
22	MOSI Digital input SPI data input (Master Output Slave Input)
23	/SEL	Digital input	SPI select, active low
24	IRQ	Digital output	1. Interrupt request signal; active high or active low; configurable2. Frame Buffer Empty Indicator; active high, see Section 11.7
25	XTAL2	Analog input	Crystal pin, see Section 9.6
26	XTAL1	Analog input	Crystal pin or external clock supply, see Section 9.6
27	AVSS	Ground Analog ground
28	EVDD	Supply	External supply voltage, analog domain
29	AVDD	Supply	Regulated 1.8V voltage regulator; analog domain, see Section 9.4
30 AVS Ground Analog ground
31 AVS Ground Analog ground
32 AV$S Ground Analog ground
Paddle AVSS Ground Analog ground; Exposed			paddle of QFN package

1.2 Analog and RF Pins

1.2.1 Supply and Ground Pins

EVDD, DEVDD

EVDD and DEVDD are analog and digital supply voltage pins of the AT86RF231 radio transceiver.

AVDD, DVDD

AVDD and DVDD are outputs of the internal 1.8V voltage regulators. The voltage regulators are controlled independently by the radio transceivers state machine and are activated dependent on the current radio transceiver state. The voltage regulators can be configured for external supply.

For details, refer to Section 9.4 "Voltage Regulators (AVREG, DVREG)" on page 110.

AVSS, DVSS

AVSS and DVSS are analog and digital ground pins respectively. The analog and digital power domains should be separated on the PCB.

1.2.2 RF Pins

RFN, RFP

A differential RF port (RFP/RFN) provides common-mode rejection to suppress the switching noise of the internal digital signal processing blocks. At board-level, the differential RF layout ensures high receiver sensitivity by rejecting any spurious emissions originated from other digital ICs such as a microcontroller.

A simplified schematic of the RF front end is shown in Figure 1-2 on page 5.

Figure 1-2. Simplified RF Front-end Schematic

AT86RF231PCB RFP RFN 0.9V M0 CM Feedback LNA RX PA TX RXTX

The RF port is designed for a 100Ω differential load. A DC path between the RF pins is allowed. A DC path to ground or supply voltage is not allowed. Therefore, when connecting an RF-load providing a DC path to the power supply or ground, AC-coupling is required as indicated in Table 1-2 on page 6.

The RF port DC values depend on the operating state, refer to Section 7. "Operating Modes" on page 33. In TRX_OFF state, when the analog front-end is disabled (see Section 7.1.2.3 "TRX_OFF - Clock State" on page 35), the RF pins are pulled to ground, preventing a floating voltage.

In transmit mode, a control loop provides a common-mode voltage of 0.9V. Transistor M0 is off, allowing the PA to set the common-mode voltage. The common-mode capacitance at each pin to ground shall be < 30 pF to ensure the stability of this common-mode feedback loop.

In receive mode, the RF port provides a low-impedance path to ground when transistor M0, see Figure 1-2 on page 5, pulls the inductor center tap to ground. A DC voltage drop of 20 mV across the on-chip inductor can be measured at the RF pins.

1.2.3 Crystal Oscillator Pins

XTAL1, XTAL2

The pin XTAL1 is the input of the reference oscillator amplifier (XOSC), XTAL2 is the output. A detailed description of the crystal oscillator setup and the related XTAL1/XTAL2 pin configuration can be found in Section 9.6 "Crystal Oscillator (XOSC)" on page 116.

When using an external clock reference signal, XTAL1 shall be used as input pin.

For further details, refer to Section 9.6.3 "External Reference Frequency Setup" on page 117.

1.2.4 Analog Pin Summary

Table 1-2. Analog Pin Behavior - DC values

Pin Values and	Conditions Comments
RFP/RFN	V_DC = 0.9V (BUSY\_TX) V_DC = 20 mV (receive states) V_DC = 0 mV (otherwise)	DC level at pins RFP/RFN for various transceiver statesAC coupling is required if an antenna with a DC path to ground is used.Serial capacitance and capacitance of each pin to ground must be < 30 pF.
XTAL1/ XTAL2	V_DC = 0.9V at both pins C_PAR = 3 pF	DC level at pins XTAL1/XTAL2 for various transceiver statesParasitic capacitance ( C_PAR ) of the pins must be considered as additional load capacitance to the crystal.
DVDD	V_DC = 1.8V (all states, except SLEEP) V_DC = 0 mV (otherwise)	DC level at pin DVDD for various transceiver statesSupply pins (voltage regulator output) for the digital 1.8V voltage domain,recommended bypass capacitor 1 μF.
AVDD	V_DC = 1.8V (all states, except P_ON, SLEEP, RESET, and TRX_OFF) V_DC = 0 mV (otherwise)	DC level at pin AVDD for various transceiver statesSupply pin (voltage regulator output) for the analog 1.8V voltage domain,recommended bypass capacitor 1 μF.

1.3 Digital Pins

The AT86RF231 provides a digital microcontroller interface. The interface comprises a slave SPI (/SEL, SCLK, MOSI and MISO) and additional control signals (CLKM, IRQ, SLP_TR, /RST and DIG2). The microcontroller interface is described in detail in Section 6. "Microcontroller Interface" on page 16.

Additional digital output signals DIG1...DIG4 are provided to control external blocks, i.e. for Antenna Diversity RF switch control or as an RX/TX Indicator, see Section 11.4 "Antenna Diversity" on page 142 and Section 11.5 "RX/TX Indicator" on page 147. After reset, these pins are pulled-down to digital ground (DIG1/DIG2) or analog ground (DIG3/DIG4).

1.3.1 Driver Strength Settings

The driver strength of all digital output pins (MISO, IRQ, DIG1, DIG2, DIG3, DIG4) and CLKM pin can be configured using register 0x03 (TRX_CTRL_0), see Table 1-3 on page 7.

Table 1-3. Digital Output Driver Configuration

Pins Default Driver Strength Recommendation/Comment
MISO, IRQ, DIG1,..., DIG4 2 mA Adjustable to 2 mA, 4 mA, 6 mA and 8 mA
CLKM 4 mA Adjustable to 2 mA, 4 mA, 6 mA and 8 mA

The capacitive load should be as small as possible as, not larger than 50 pF when using the 2 mA minimum driver strength setting. Generally, the output driver strength should be adjusted to the lowest possible value in order to keep the current consumption and the emission of digital signal harmonics low.

1.3.2 Pull-Up and Pull-Down Configuration

All digital input pins are internally pulled-up or pulled-down in radio transceiver state P_ON, see Section 7.1.2.1 "P_ON - Power-On after VDD" on page 34. Table 1-4 on page 7 summarizes the pull-up and pull-down configuration.

Table 1-4. Pull-Up / Pull-Down Configuration of Digital Input Pins in P_ON State

Pins H pull-up,	L pull-down = =
/RST H
/SEL H
SCLK	L
MOSI	L
SLP_TR	L

In all other radio transceiver states, no pull-up or pull-down circuitry is connected to any of the digital input pins mentioned in Table 1-4 on page 7. In RESET state, the pull-up / pull-down configuration is disabled.

1.3.3 Register Description

Register 0x03 (TRX_CTRL_0):

The TRX_CTRL_0 register controls the drive current of the digital output pads and the CLKM clock rate.

Bit 76543210

0x03 PAD_IO PAD_IO_CLKM CLKM_SHA_SEL CLKM_CTRL TRX_CTRL_0 Read/Write R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 1 1 0 0 1

- Bit [7:6] - PAD_IO

The register bits set the output driver current of all digital output pads, except CLKM.

Table 1-5. Digital Output Driver Strength

Register Bit	Value	Description
PAD_IO	0^(1)	2 mA
	1	4 mA
	2	6 mA
	3	8 mA

Note: 1. Reset values of register bits are underlined characterized in the document.

- Bit [5:4] - PAD_IO_CLKM

The register bits set the output driver current of pin CLKM. Refer also to Section 9.6 "Crystal Oscillator (XOSC)" on page 116.

Table 1-6. CLKM Driver Strength

Register Bit	Value	Description
PAD_IO_CLKM	0	2 mA
	1	4 mA
	2	6 mA
	3	8 mA

- Bit 3 - CLKM_SHA_SEL

Refer to Section 9.6 "Crystal Oscillator (XOSC)" on page 116.

- Bit [2:0] - CLKM_CTRL

Refer to Section 9.6 "Crystal Oscillator (XOSC)" on page 116.

2. Disclaimer

Typical values contained in this datasheet are based on simulations and testing. Min and Max values are available when the radio transceiver has been fully characterized.

3. Overview

The AT86RF231 is a feature rich, low-power 2.4 GHz radio transceiver designed for industrial and consumer ZigBee/IEEE 802.15.4, 6LoWPAN, RF4CE and high data rate 2.4 GHz ISM band applications. The radio transceiver is a true SPI-to-antenna solution. All RF-critical components except the antenna, crystal and de-coupling capacitors are integrated on-chip. Therefore, the AT86RF231 is particularly suitable for applications like:

• 2.4 GHz IEEE 802.15.4 and ZigBee systems
- 6LoWPAN and RF4CE systems
- Wireless sensor networks
- Industrial control, sensing and automation (SP100, WirelessHART)
• Residential and commercial automation
- Health care
- Consumer electronics
- PC peripherals

The AT86RF231 can be operated by using an external microcontroller like Atmel's AVR microcontrollers. A comprehensive software programming description can be found in reference [6] , AT86RF231 Software Programming Model.

4. General Circuit Description

This single-chip radio transceiver provides a complete radio transceiver interface between an antenna and a microcontroller. It comprises the analog radio, digital modulation and demodulation including time and frequency synchronization and data buffering. The number of external components is minimized such that only the antenna, the crystal and decoupling capacitors are required. The bidirectional differential antenna pins (RFP, RFN) are used for transmission and reception, thus no external antenna switch is needed.

The AT86RF231 block diagram is shown in Figure 4-1 on page 10.

Figure 4-1. AT86RF231 Block Diagram

graph TD
    A["DIG1/2"] --> B["AD"]
    B --> C["LNA"]
    C --> D["PPF BPF Limiter ADC"]
    D --> E["PLL PA"]
    E --> F["EXT. PA and Power Control"]
    F --> G["XTAL1"]
    F --> H["XOSC"]
    F --> I["AVREG"]
    J["RFP"] --> C
    K["RFN"] --> C
    L["XTAL2"] --> M["Configuration Registers"]
    N["FX Data"] --> E
    O["FTN, BATMON"] --> D
    P["AGC"] --> D
    Q["RSSI"] --> R["Control Logic"]
    S["Frame Buffer"] --> T["TX BBP"]
    U["AES"] --> V["DVREG"]
    W["SCLK"] --> X["SPI (Slave)"]
    Y["/SEL"] --> T
    Z["MISO"] --> T
    AA["MOSI"] --> T
    AB["SCLK"] --> X
    AC["/SEL"] --> T
    AD["/SEL"] --> T
    AE["/SEL"] --> X
    AF["/SEL"] --> X
    AG["/SEL"] --> X
    AH["/SEL"] --> X
    AI["/SEL"] --> X
    AJ["/SEL"] --> X
    AK["/SEL"] --> X
    AL["/SEL"] --> X
    AM["/SEL"] --> X
    AN["/SEL"] --> X
    AO["/SEL"] --> X
    AP["/SEL"] --> X
    AQ["/SEL"] --> X
    AR["/SEL"] --> X
    AS["/SEL"] --> X
    AT["/SEL"] --> X
    AU["/SEL"] --> X
    AV["/SEL"] --> X
    AW["/SEL"] --> X
    AX["/SEL"] --> X
    AY["/SEL"] --> X

The received RF signal at pins RFN and RFP is differentially fed through the low-noise amplifier (LNA) to the RF filter (PPF) to generate a complex signal, driving the integrated channel filter (BPF). The limiting amplifier provides sufficient gain to drive the succeeding analog-to-digital converter (ADC) and generates a digital RSSI signal. The ADC output signal is sampled by the digital base band receiver (RX BBP).

The transmit modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping and 32-length block coding (spreading) according to [1] and [2]. The modulation signal is generated in the digital transmitter (TX BBP) and applied to the fractional-N frequency synthesis (PLL), to ensure the coherent phase modulation required for demodulation of O-QPSK signals. The frequency-modulated signal is fed to the power amplifier (PA).

A differential pin pair DIG3/DIG4 can be enabled to control an external RF front-end.

Two on-chip low-dropout voltage regulators (A|DVREG) provide the analog and digital 1.8V supply.

An internal 128-byte RAM for RX and TX (Frame Buffer) buffers the data to be transmitted or the received data.

The configuration of the AT86RF231, reading and writing of Frame Buffer is controlled by the SPI interface and additional control lines.

The AT86RF231 further contains comprehensive hardware-MAC support (Extended Operating Mode) and a security engine (AES) to improve the overall system power efficiency and timing. The stand-alone 128-bit AES engine can be accessed in parallel to all PHY operational transactions and states using the SPI interface, except during SLEEP state.

For applications not necessarily targeting IEEE 802.15.4 compliant networks, the radio transceiver also supports alternative data rates up to 2 Mb/s.

For long-range applications or to improve the reliability of an RF connection the RF performance can further be improved by using an external RF front-end or Antenna Diversity. Both operation modes are supported by the AT86RF231 with dedicated control pins without the interaction of the microcontroller.

Additional features of the Extended Feature Set, see Section 11. "AT86RF231 Extended Feature Set" on page 128, are provided to simplify the interaction between radio transceiver and microcontroller.

5. Application Circuits

5.1 Basic Application Schematic

A basic application schematic of the AT86RF231 with a single-ended RF connector is shown in Figure 5-1 on page 12. The 50Ω single-ended RF input is transformed to the 100Ω differential RF port impedance using balun B1. The capacitors C1 and C2 provide AC coupling of the RF input to the RF port, optional capacitor C4 improves matching if required.

Figure 5-1. Basic Application Schematic

AT86RF231 DIG3 AVSS AVSS AVSS AVDD EVDD AVSS XTAL1 XTAL2 DIG4 AVSS RFP RFN AVSS DVSS /RST DIG1 DIG2 SLP_TR DVSS DVDD DVDD DEVDD DVSS CB1 CB2 CX1 CX2 XTAL VDD VDD CX1 CX2 XTAL 25 26 27 28 29 30 31 32 IRQ 24 /SEL 23 MOSI 22 DVSS 21 MISO 20 SCLK 19 DVSS 18 R1 CLKM 17 C3 C4 B1 C1 C2 VDD

The power supply decoupling capacitors (CB2, CB4) are connected to the external analog supply pin (EVDD, pin 28) and external digital supply pin (DEVDD, pin 15). Capacitors CB1 and CB3 are bypass capacitors for the integrated analog and digital voltage regulators to ensure stable operation. All decoupling and bypass capacitors should be placed as close as possible to the pins and should have a low-resistance and low-inductance connection to ground to achieve the best performance.

The crystal (XTAL), the two load capacitors (CX1, CX2), and the internal circuitry connected to pins XTAL1 and XTAL2 form the crystal oscillator. To achieve the best accuracy and stability of the reference frequency, large parasitic capacitances should be avoided. Crystal lines should be

routed as short as possible and not in proximity of digital I/O signals. This is especially required for the High Data Rate Modes, refer to Section 11.3 "High Data Rate Modes" on page 137.

Crosstalk from digital signals on the crystal pins or the RF pins can degrade the system performance. Therefore, a low-pass filter (C3, R1) is placed close to the CLKM output pin to reduce the emission of CLKM signal harmonics. This is not needed if the CLKM pin is not used as a microcontroller clock source. In that case, the output should be turned off during device initialization.

The ground plane of the application board should be separated into four independent fragments, the analog, the digital, the antenna and the XTAL ground plane. The exposed paddle shall act as the reference point of the individual grounds.

Table 5-1. Example Bill of Materials (BoM) for Basic Application Schematic

Designator	Description Value Manufacture Part Number Comment
B1 SMD balun	2.45 GHz Wuerth 748421245 2.45 GHz Balun		Johanson Technology	2450FB15L0001 2.45 GHz	Balun / Filter
B1 (alternatively)	SMD balun / filter 2.45 GHz
CB1 CB3	LDO VREG bypass capacitor	1 μF	AVX Murata	0603YD105KAT2A GRM188R61C105KA12D	X5R (0603)	10%	16V
CB2 CB4	Power Supply decoupling
CX1, CX2 Crystal load capacitor		12 pF	AVX Murata	06035A120JA GRP1886C1H120JA01	COG (0603)	5%	50V
C1, C2	RF coupling capacitor	22 pF	Epcos Epcos AVX	B37930 B37920 06035A220JAT2A	COG	5%
					(0402 or 0603)
C3	CLKM low-pass filter capacitor	2.2 pF	AVX Murata	06035A229DA GRP1886C1H2R0DA01	COG (0603)	±0.5 pF
					Designed for f_CLKM =1 MHz
C4 (optional)	RF matching	0.47 pF			Depends on final PCB implementation
R1	CLKM low-pass filter resistor	680Ω			Designed for f_CLKM =1 MHz
XTAL	Crystal	CX-4025 16 MHz SX-4025 16 MHz	ACAL Taitjen Siward	XWBBPL-F-1 A207-011

Note: Please note that pins DIG1...4 are connected to the ground in the Basic Application Schematic, refer to Figure 5-1 on page 12. Special programming of these pins require a different schematic, refer to “Extended Feature Set Application Schematic” on page 14.

5.2 Extended Feature Set Application Schematic

The AT86RF231 supports additional features like:

• Security Module (AES) see Section 11.1
• High Data Rate Mode see Section 11.3
• Antenna Diversity uses pins DIG1/2 see Section 11.4
• RX/TX indicator uses pins DIG3/4 see Section 11.5
• RX Frame Time Stamp uses pin DIG2 see Section 11.6

An extended feature set application schematic illustrating the use of the AT86RF231 Extended Feature Set, see Section 11. "AT86RF231 Extended Feature Set" on page 128, is shown in Figure 5-2 on page 14. Although this example shows all additional hardware features combined, it is possible to use all features separately or in various combinations.

Figure 5-2. Extended Feature Application Schematic

ANT0 SW2 ANT1 RF-Switch N2 LNA PA N1 RF-Switch Balun B1SW1 AT86RF231 DIG3 AVSS AVSS AVSS AVDD EVDD AVSS XTAL1 XTAL2 DIG4 AVSS RFP RFN AVSS DVSS /RST DIG1 DIG2 SLP_TR DVSS DVDD DVDD DEVDD DVSS CB3 CB4 CB1 CB2 CX1 CX2 XTAL IRQ 24 /SEL 23 MOSI 22 DVSS 21 MISO 20 SCLK 19 DVSS 18 CLKM 17 R1 C3 V_DD Digital Interface

In this example, a balun (B1) transforms the differential RF signal at the radio transceiver RF pins (RFP/RFN) to a single ended RF signal, similar to the Basic Application Schematic; refer to Figure 5-1 on page 12. The RF-Switches (SW1, SW2) separate between receive and transmit path in an external RF front-end.

These switches are controlled by the RX/TX Indicator, represented by the differential pin pair DIG3/DIG4, refer to Section 11.5 "RX/TX Indicator" on page 147.

During receive the radio transceiver searches for the most reliable RF signal path using the Antenna Diversity algorithm. One antenna is selected (SW2) by the Antenna Diversity RF switch

control pins DIG1/DIG2, the RF signal is amplified by an optional low-noise amplifier (N2) and fed to the radio transceiver using the second RX/TX switch (SW1).

During transmit the AT86RF231 TX signal is amplified using an external PA (N1) and fed to the antennas via an RF switch (SW2). In this example RF switch SW2 further supports Antenna Diversity controlled by the differential pin pair DIG1/DIG2.

The security engine (AES) and High Data Rate Modes do not require specific circuitry to operate. The security engine (AES) has to be configured in advance, for details refer to Section 11.1 "Security Module (AES)" on page 128. The High Data Rate Modes are enabled by register bits OQPSK_DATA_RATE (register 0x0C, TRX_CTRL_2), for details refer to Section 11.3 "High Data Rate Modes" on page 137.

6. Microcontroller Interface

This section describes the AT86RF231 to microcontroller interface. The interface comprises a slave SPI and additional control signals; see Figure 6-1 on page 16. The SPI timing and protocol are described below.

Figure 6-1. Microcontroller to AT86RF231 Interface

graph LR
    A["Microcontroller"] -->|/SEL| B["SPI - Master"]
    A -->|MOSI| B
    A -->|MISO| B
    A -->|SCLK| B
    A -->|GPIO1/CLK| B
    A -->|GPIO2/IRQ| B
    A -->|GPIO3| B
    A -->|GPIO4| B
    A -->|GPIO5| B
    B -->|/SEL| C["AT86RF231"]
    B -->|MOSI| C
    B -->|MISO| C
    B -->|SCLK| C
    B -->|CLKM| C
    B -->|IRQ| C
    B -->|SLP_TR| C
    B -->|/RST| C
    B -->|DIG2| C
    C -->|/SEL| D["SPI - Slave"]
    C -->|MOSI| D
    C -->|MISO| D
    C -->|SCLK| D
    C -->|CLKM| D
    C -->|IRQ| D
    C -->|SLP_TR| D
    C -->|/RST| D
    C -->|DIG2| D

Microcontrollers with a master SPI such as Atmel's AVR family interface directly to the AT86RF231. The SPI is used for register, Frame Buffer, SRAM and AES access. The additional control signals are connected to the GPIO/IRQ interface of the microcontroller.

Table 6-1 on page 16 introduces the radio transceiver I/O signals and their functionality.

Table 6-1. Signal Description of Microcontroller Interface

Signal Description
/SEL SPI select	signal, active low
MOSI SPI data	(master output slave input) signal
MISO SPI data	(master input slave output) signal
SCLK SPI clock	signal
CLKM Clock output, refer to Section 9.6.4 usable as:-microcontroller clock source-high precision timing reference-MAC timer reference
IRQ Interrupt request signal, further used as:-Frame Buffer Empty Indicator, refer to Section 11.7
SLP_TR	Multipurpose control signal (functionality is state dependent, see Section 6.5):-Sleep/Wakeup enable/disable SLEEP state-TX start BUSY_TX_(ARET) state-disable/enable CLKM RX_(AACK)_ON state
/RST AT86RF231 reset signal, active low
DIG2	Optional, IRQ_2 (RX_START) for RX Frame Time Stamping, see Section 11.6

6.1 SPI Timing Description

Pin 17 (CLKM) can be used as a microcontroller master clock source. If the microcontroller derives the SPI master clock (SCLK) directly from CLKM, the SPI operates in synchronous mode, otherwise in asynchronous mode.

In synchronous mode, the maximum SCLK frequency is 8 MHz.

In asynchronous mode, the maximum SCLK frequency is limited to 7.5 MHz. The signal at pin CLKM is not required to derive SCLK and may be disabled to reduce power consumption and spurious emissions.

Figure 6-2 on page 17 and Figure 6-3 on page 17 illustrate the SPI timing and introduces its parameters. The corresponding timing parameter definitions t_1 - t_9 are defined in Section 12.4 "Digital Interface Timing Characteristics" on page 157.

Figure 6-2. SPI Timing, Global Map and Definition of Timing Parameters t 5 , t 6 , t 8 and t 9

/SEL SCLK MOSI MISO t0 t1 t2 t3 t4 t5 t6 t7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Figure 6-3. SPI Timing, Detailed Drawing of Timing Parameter t_1 to t_4

/SEL SCLK MOSI MISO t1 t2 Bit 7 Bit 6 Bit 5 Bit 7 Bit 6 Bit 5

The SPI is based on a byte-oriented protocol and is always a bidirectional communication between master and slave. The SPI master starts the transfer by asserting /SEL = L. Then the master generates eight SPI clock cycles to transfer one byte to the radio transceiver (via MOSI). At the same time, the slave transmits one byte to the master (via MISO). When the master wants to receive one byte of data from the slave it must also transmit one byte to the slave. All bytes are transferred with MSB first. An SPI transaction is finished by releasing /SEL = H.

An SPI register access consists of two bytes, a Frame Buffer or SRAM access of at least two or more bytes as described in Section 6.2 "SPI Protocol" on page 19.

/SEL = L enables the MISO output driver of the AT86RF231. The MSB of MISO is valid after t1 (see Section 12.4 "Digital Interface Timing Characteristics" on page 157 parameter 12.4.3) and is updated at each falling edge of SCLK. If the driver is disabled, there is no internal pull-up circuitry connected to it. Driving the appropriate signal level must be ensured by the master device or an external pull-up resistor. Note, when both /SEL and /RST are active, the MISO output driver is also enabled.

Referring to Figure 6-2 on page 17 and Figure 6-3 on page 17 MOSI is sampled at the rising edge of the SCLK signal and the output is set at the falling edge of SCLK. The signal must be stable before and after the rising edge of SCLK as specified by t_3 and t_4 , refer to Section 12.4 "Digital Interface Timing Characteristics" on page 157 parameters 12.4.5 and 12.4.6.

This SPI operational mode is commonly known as "SPI mode 0".

6.2 SPI Protocol

Each SPI sequence starts with transferring a command byte from the SPI master via MOSI (see Table 6-2 on page 19) with MSB first. This command byte defines the SPI access mode and additional mode-dependent information.

Table 6-2. SPI Command Byte definition

Bit 7 Bit 6 Bit 5	Bit 4 Bit	3 Bit 2 Bit	1 Bit 0	Access	Mode Access Type
1 0 Register address [5:0]						Register accessWrite access	Read access
1 1 Register address [5:0]
0	0	1	Reserved			Frame Buffer accessWrite access	Read access
0 1	1		Reserved				access
0	0	0	Reserved			SRAM accessWrite access	Read access
0 1	0		Reserved				access

Each SPI transfer returns bytes back to the SPI master on MISO. The content of the first byte (see value "PHY_STATUS" in Figure 6-4 on page 19 to Figure 6-14 on page 23) is set to zero after reset. To transfer status information of the radio transceiver to the microcontroller, the content of the first byte can be configured with register bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1). For details, refer to Section 6.3.1 "Register Description - SPI Control" on page 24.

In Figure 6-4 on page 19 to Figure 6-14 on page 23 and the following chapters logic values stated with XX on MOSI are ignored by the radio transceiver, but need to have a valid logic level. Return values on MISO stated as XX shall be ignored by the microcontroller.

The different access modes are described within the following sections.

6.2.1 Register Access Mode

A register access mode is a two-byte read/write operation initiated by /SEL = L. The first transferred byte on MOSI is the command byte including an identifier bit (bit7 = 1), a read/write select bit (bit 6), and a 6-bit register address.

On read access, the content of the selected register address is returned in the second byte on MISO (see Figure 6-4 on page 19).

Figure 6-4. Packet Structure - Register Read Access

byte 1 (command byte) byte 2 (data byte) MOSI 1 0 ADDRESS[5:0] XX MISO PHY_STATUS(1) READ DATA[7:0]

Note: 1. Each SPI access can be configured to return radio controller status information (PHY_STATUS) on MISO, for details refer to Section 6.3 "Radio Transceiver Status information" on page 24.

On write access, the second byte transferred on MOSI contains the write data to the selected address (see Figure 6-5 on page 20).

Figure 6-5. Packet Structure - Register Write Access

byte 1 (command byte) byte 2(data-byte) MOSI 1 | 1 ADDRESS[5:0] WRITE DATA[7:0] PHY_STATUS XXMISO

Each register access must be terminated by setting /SEL = H.

Figure 6-6 on page 20 illustrates a typical SPI sequence for a register access sequence for write and read respectively.

Figure 6-6. Example SPI Sequence - Register Access Mode

graph LR
    subgraph Signal Waveform
        A["/SEL"] --> B["Register Write Access"]
        C["SCLK"] --> D["Register Read Access"]
        E["MOSI"] --> F["WRITE COMMAND"] --> G["WRITE DATA"] --> H["READ COMMAND"] --> I["XX"] --> J["MISO"]
        K["MISO"] --> L["PHY_STATUS XX"] --> M["PHY_STATUS READ DATA"] --> N["..."]
    end
    style A fill:#f9f,stroke:#333
    style C fill:#f9f,stroke:#333
    style E fill:#ccf,stroke:#333
    style K fill:#ccf,stroke:#333

6.2.2 Frame Buffer Access Mode

The 128-byte Frame Buffer can hold the PHY service data unit (PSDU) data of one IEEE 802.15.4 compliant RX or one TX frame of maximum length at a time. A detailed description of the Frame Buffer can be found in Section 9.3 "Frame Buffer" on page 107. An introduction to the IEEE 802.15.4 frame format can be found in Section 8.1 "Introduction - IEEE 802.15.4 - 2006 Frame Format" on page 79.

Frame Buffer read and write accesses are used to read or write frame data (PSDU and additional information) from or to the Frame Buffer. Each access starts with /SEL = L followed by a command byte on MOSI. If this byte indicates a frame read or write access, the next byte PHR[7:0] indicates the frame length followed by the PSDU data, see Figure 6-7 on page 20 and Figure 6-8 on page 21.

On Frame Buffer read access, PHY header (PHR) and PSDU are transferred via MISO starting with the second byte. After the PSDU data, one more byte is transferred containing the link quality indication (LQI) value of the received frame, for details refer to Section 8.6 "Link Quality Indication (LQI)" on page 99. Figure 6-7 on page 20 illustrates the packet structure of a Frame Buffer read access.

Figure 6-7. Packet Structure - Frame Read Access

byte 1 (command byte) byte 2 (data byte) byte 3 (data byte) MOSI 0 0 1 reserved[4:0] XX XX ... XX XX MISO PHY_STATUS PHR[7:0] PSDU[7:0] ... PSDU[7:0] LQI[7:0]

Note, the Frame Buffer read access can be terminated at any time without any consequences by setting /SEL = H, e.g. after reading the PHR byte only.

On Frame Buffer write access the second byte transferred on MOSI contains the frame length (PHR field) followed by the payload data (PSDU) as shown by Figure 6-8 on page 21.

Figure 6-8. Packet Structure - Frame Write Access

byte 1 (command byte) byte 2 (data byte) byte 3 (data byte) 0 res[er]ed[R[7:0]]MOS PSDU[7:0] ... PSDU[7:0] PSDU[7:0] PHY_STATUSMISO XX XX ... XX XX

The number of bytes n for one frame access is calculated as follows:

• Read Access: n = 3 + frame_length
  [PHY_STATUS, PHR byte, PSDU data, and LQI byte]
• Write Access: n = 2 + frame_length
  [command byte, PHR byte, and PSDU data]

The maximum value of frame_length is 127 bytes. That means that n ≤ 130 for Frame Buffer read and n ≤ 129 for Frame Buffer write accesses.

Each read or write of a data byte increments automatically the address counter of the Frame Buffer until the access is terminated by setting /SEL = H. A Frame Buffer read access may be terminated (/SEL = H) at any time without affecting the Frame Buffer content. Another Frame Buffer read operation starts again at the PHR field.

The content of the Frame Buffer is only overwritten by a new received frame or a Frame Buffer write access.

Figure 6-9 on page 21 and Figure 6-10 on page 22 illustrate an example SPI sequence of a Frame Buffer access to read and write a frame with 4-byte PSDU respectively.

Figure 6-9. Example SPI Sequence - Frame Buffer Read of a Frame with 4-byte PSDU

/SEL SCLK MOSI COMMAND XX XX XX XX XX XX MISO PHY_STATUS PHR PSDU 1 PSDU 2 PSDU 3 PSDU 4 LQI

Figure 6-10. Example SPI Sequence - Frame Buffer Write of a Frame with 4 byte PSDU

/SEL SCLK MOSI MISO COMMAND PHR PSDU 1 PSDU 2 PSDU 3 PSDU 4 PHY_STATUS X XXXX XXXX

Access violations during a Frame Buffer read or write access are indicated by interrupt IRQ_6 (TRX_UR). For further details, refer to Section 9.3 "Frame Buffer" on page 107.

Notes

• The Frame Buffer is shared between RX and TX; therefore, the frame data are overwritten by new incoming frames. If the TX frame data are to be retransmitted, it must be ensured that no frame was received in the meanwhile.
• To avoid overwriting during receive Dynamic Frame Buffer Protection can be enabled, refer to Section 11.8 “Dynamic Frame Buffer Protection” on page 154.
• It is not possible to retransmit received frames without a Frame Buffer read and write access cycle.
• For exceptions, e.g. receiving acknowledgement frames in Extended Operating Mode (TX_ARET) refer to Section 7.2.4 "TX_ARET_ON - Transmit with Automatic Retry and CSMA-CA Retry" on page 64.

6.2.3 SRAM Access Mode

The SRAM access mode allows accessing dedicated bytes within the Frame Buffer. This may reduce the SPI traffic.

The SRAM access mode is useful, for instance, if a transmit frame is already stored in the Frame Buffer and dedicated bytes (e.g. sequence number, address field) need to be replaced before retransmitting the frame. Furthermore, it can be used to access only the LQI value after frame reception. A detailed description of the user accessible frame content can be found in Section 9.3 "Frame Buffer" on page 107.

Each SRAM access starts with /SEL = L. The first transferred byte on MOSI shall be the command byte and must indicate an SRAM access mode according to the definition in Table 6-2 on page 19. The following byte indicates the start address of the write or read access. The address space is 0x00 to 0x7F for radio transceiver receive or transmit operations.

On SRAM read access, one or more bytes of read data are transferred on MISO starting with the third byte of the access sequence (see Figure 6-11 on page 22).

Figure 6-11. Packet Structure - SRAM Read Access

byte 1 (command byte) byte 2 (address) byte 3 (data byte) MOSI 0 0 0 reserved[4:0] 0 ADDRESS[6:0] XX ... MISO PHY_STATUS XX DATA[7:0] ... byte n-1 (data byte) byte n (data byte)

On SRAM write access, one or more bytes of write data are transferred on MOSI starting with the third byte of the access sequence (see Figure 6-12 on page 23).

On SRAM read or write accesses do not attempt to read or write bytes beyond the SRAM buffer size.

Figure 6-12. Packet Structure - SRAM Write Access

byte 1 (command byte) byte 2 (address) byte 3 (data byte) 0 es#eA[7:0]OS 0 ADDRESS[6:0] ... DATA[7:0] DATA[7:0] PHY_STATUSMISO XX XX ... XX XX

As long as /SEL = L, every subsequent byte read or byte write increments the address counter of the Frame Buffer until the SRAM access is terminated by /SEL = H.

Figure 6-13 on page 23 and Figure 6-14 on page 23 illustrate an example SPI sequence of a SRAM access to read and write a data package of 5-byte length respectively.

Figure 6-13. Example SPI Sequence - SRAM Read Access of a 5 byte Data Package

/SEL SCLK MOSI COMMAND ADDRESS XX XX XX XX XX XX MISO PHY_STATUS XX DATA 1 DATA 2 DATA 3 DATA 4 DATA 5

Figure 6-14. Example SPI Sequence - SRAM Write Access of a 5 byte Data Package

graph LR
    A["/SEL"] --> B["SCLK"]
    B --> C["MOSI"]
    C --> D["MISO"]
    D --> E["PHY_STATUS"]
    E --> F["XX"]
    F --> G["XX"]
    G --> H["XX"]
    H --> I["XX"]
    I --> J["XX"]
    J --> K["XX"]

Notes

• The SRAM access mode is not intended to be used as an alternative to the Frame Buffer access modes (see Section 6.2.2 "Frame Buffer Access Mode" on page 20).
• If the SRAM access mode is used to read PSDU data, the Frame Buffer contains all PSDU data except the frame length byte (PHR). The frame length information can be accessed only using Frame Buffer access.
• Frame Buffer access violations are not indicated by a TRX_UR interrupt when using the SRAM access mode, for further details refer to Section 9.3.3 "Interrupt Handling" on page 109.

6.3 Radio Transceiver Status information

Each SPI access can be configured to return status information of the radio transceiver (PHY_STATUS) to the microcontroller using the first byte of the data transferred via MISO.

The content of the radio transceiver status information can be configured using register bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1). After reset, the content on the first byte send on MISO to the microcontroller is set to 0x00.

6.3.1 Register Description - SPI Control

Register 0x04 (TRX\_CTRL\_1):

The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver.

Bit 76543210

+0x04	PA_EXT_EN	IRQ_2_EXT_EN	TX_AUTO_CRC_ON	RX_BL_CTRL	SPI_CMD_MODE		IRQ_MASK_MODE	IRQ_POLARITY	TRX_CTRL_1
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0 0 1 0 0 0	0 0

- Bit 7 - PA\_EXT\_EN

Refer to Section 11.5 "RX/TX Indicator" on page 147.

- Bit 6 - IRQ\_2\_EXT\_EN

Refer to Section 11.6 "RX Frame Time Stamping" on page 150.

- Bit 5 - TX\_AUTO\_CRC\_ON

Refer to Section 8.2 "Frame Check Sequence (FCS)" on page 85.

- Bit 4 - RX\_BL\_CTRL

Refer to Section 11.7 "Frame Buffer Empty Indicator" on page 152.

- Bit [3:2] - SPI\_CMD\_MODE

Each SPI transfer returns bytes back to the SPI master. The content of the first byte can be configured using register bits SPI_CMD_MODE. The transfer of the following status information can be configured as follows:

Table 6-3. Radio Transceiver Status Information - PHY_STATUS

Register Bit	Value	Description
SPI_CMD_MODE	0	default (empty, all bits 0x00)
	1	monitor TRX_STATUS register; see Section 7.1.5
	2	monitor PHY_RSSI register; see Section 8.3
	3	monitor IRQ_STATUS register; see Section 6.6

- Bit 1 - IRQ\_MASK\_MODE

Refer to Section 6.6 "Interrupt Logic" on page 29.

- Bit 0 - IRQ\_POLARITY

Refer to Section 6.6 "Interrupt Logic" on page 29.

6.4 Radio Transceiver Identification

The AT86RF231 can be identified by four registers. One register contains a unique part number and one register the corresponding version number. Two additional registers contain the JEDEC manufacture ID.

6.4.1 Register Description - AT86RF231 Identification

Register 0x1C (PART_NUM):

B i t 7 6 5 4 3 2 1 0 +0x1C PART_NUM[7:0] PART_NUM R e a d / W r i t e R R R e s e t V a l u e 0 0

- Bit [7:0] - PART\_NUM

This register contains the radio transceiver part number.

Table 6-4. Radio Transceiver Part Number

Register Bit Value	Description
PART_NUM	3	AT86RF231 part number

Register 0x1D (VERSION_NUM):

Bit +0x1D VERSION_NUM[7:0] VERSION_NUM Read/Write R R R R R R R Reset Value 0 0 0 0 0 0 1 0

- Bit [7:0] - VERSION\_NUM

This register contains the radio transceiver version number.

Table 6-5. Radio Transceiver Version Number

Register Bit Value	Description
VERSION_NUM	2	Revision A

Register 0x1E (MAN_ID_0):

Bit +0x1E MAN_ID_0[7:0] Read/Write R R R R R R Reset Value 0 0 0 1 1 1 1 1 MAN_ID_O

- Bit [7:0] - MAN\_ID\_0

Bits [7:0] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_0. Bits [15:8] are stored in register 0x1F (MAN_ID_1). The highest 16 bits of the ID are not stored in registers.

Table 6-6. JEDEC Manufacturer ID - Bits [7:0]

Register Bit Value Description
MAN_ID_0 0x1F	____	Atmel JEDEC manufacturer ID,Bits [7:0] of 32 bit manufacturer ID: 00 00 00 1F

Register 0x1F (MAN_ID_1):

B i t 7 6 5 4 3 2 1 0 +0x1F MAN_ID_1[7:0] MAN_ID_1 R e a d / W r i t e R R e s e t V a l u e 0 0

- Bit [7:0] - MAN\_ID\_1

Bits [15:8] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_1. Bits [7:0] are stored in register 0x1E (MAN_ID_0). The higher 16 bits of the ID are not stored in registers.

Table 6-7. JEDEC Manufacturer ID - Bits [15:8]

Register Bit Value Description
MAN_ID_1	0x00	Atmel JEDEC manufacturer ID,Bits [15:8] of 32 bit manufacturer ID: 00 00 00 1F

6.5 Sleep/Wake-up and Transmit Signal (SLP\_TR)

Pin 11 (SLP_TR) is a multi-functional pin. Its function relates to the current state of the AT86RF231 and is summarized in Table 6-8 on page 27. The radio transceiver states are explained in detail Section 7. "Operating Modes" on page 33.

Table 6-8. SLP_TR Multi-functional Pin

Transceiver Status Function Transition Description
PLL_ON TX start Starts frame transmission	L H
TX_ARET_ON TX start Starts TX_ARET transactionH
TRX_OFF Sleep Takes the radio transceiver into SLHEP state, CLKM disabled
SLEEP Wakeup Takes the radio transceiver back into TRX_OFF state, level sensitive
RX_ON	Disable CLKM	L H	Takes the radio transceiver into RX_ON_NOCLK state and disables CLKM
RX_ON_NOCLK	Enable CLKM	H L	Takes the radio transceiver into RX_ON state and enables CLKM
RX_AACK_ON	Disable CLKM	L H	Takes the radio transceiver into RX_AACK_ON_NOCLK state and disables CLKM
RX_AACK_ON_NOCLK	Enable CLKM	H L	Takes the radio transceiver into RX_AACK_ON state and enables CLKM

In states PLL_ON and TX_ARET_ON, pin SLP_TR is used as trigger input to initiate a TX transaction. Here pin SLP_TR is sensitive on rising edge only.

After initiating a state change by a rising edge at pin SLP_TR in radio transceiver states TRX_OFF, RX_ON or RX_AACK_ON, the radio transceiver remains in the new state as long as the pin is logical high and returns to the preceding state with the falling edge.

SLEEP state

The SLEEP state is used when radio transceiver functionality is not required, and thus the AT86RF231 can be powered down to reduce the overall power consumption.

A power-down scenario is shown in Figure 6-15 on page 28. When the radio transceiver is in TRX_OFF state the microcontroller forces the AT86RF231 to SLEEP by setting SLP_TR = H. If pin 17 (CLKM) provides a clock to the microcontroller this clock is switched off after 35 clock cycles. This enables a microcontroller in a synchronous system to complete its power-down routine and prevent deadlock situations. The AT86RF231 awakes when the microcontroller releases pin SLP_TR. This concept provides the lowest possible power consumption.

The CLKM clock frequency settings for 250 kHz and 62.5 kHz are not intended to directly clock the microcontroller. When using these clock rates, CLKM is turned off immediately when entering SLEEP state.

Figure 6-15. Sleep and Wake-up Initiated by Asynchronous Microcontroller Timer

SLP_TR CLKM 35 CLKM clock cycles CLKM off tTR15 async timer elapses (microcontroller)

Note: Timing figure t_TR15 refer to section Table 7-1 on page 42.

RX\_ON and RX\_AACK\_ON states

For synchronous systems, where CLKM is used as a microcontroller clock source and the SPI master clock (SCLK) is directly derived from CLKM, the AT86RF231 supports an additional power-down mode for receive operating states (RX_ON and RX_AACK_ON).

If an incoming frame is expected and no other applications are running on the microcontroller, it can be powered down without missing incoming frames.

This can be achieved by a rising edge on pin SLP_TR that turns off the CLKM. Then the radio transceiver state changes from RX_ON or RX_AACK_ON (Extended Operating Mode) to RX_ON_NOCLK or RX_AACK_ON_NOCLK respectively.

In case that a frame is received (e.g. indicated by an IRQ_2 (RX_START) interrupt) the clock output CLKM is automatically switched on again.

This scenario is shown in Figure 6-16 on page 28. In RX_ON state, the clock at pin 17 (CLKM) is switched off after 35 clock cycles when setting the pin SLP_TR = H.

The CLKM clock frequency settings for 250 kHz and 62.5 kHz are not intended to directly clock the microcontroller. When using these clock rates, CLKM is turned off immediately when entering RX_ON_NOCLK and RX_AACK_ON_NOCLK respectively.

In states RX_(AACK)_ON_NOCLK and RX_(AACK)_ON, the radio transceiver current consumptions are equivalent. However, the RX_(AACK)_ON_NOCLK current consumption is reduced by the current required for driving pin 17 (CLKM).

Figure 6-16. Wake-Up Initiated by Radio Transceiver Interrupt

radio transceiver IRQ issued typ. 5 µs SLP_TR CLKM 35 CLKM clock cycles-CLKM off

6.6 Interrupt Logic

6.6.1 Overview

The AT86RF231 differentiates between nine interrupt events (eight physical interrupt registers, one shared by two functions). Each interrupt is enabled by setting the corresponding bit in the interrupt mask register 0x0E (IRQ_MASK). Internally, each pending interrupt is stored in a separate bit of the interrupt status register. All interrupt events are OR-combined to a single external interrupt signal (IRQ, pin 24). If an interrupt is issued (pin IRQ = H), the microcontroller shall read the interrupt status register 0x0F (IRQ_STATUS) to determine the source of the interrupt. A read access to this register clears the interrupt status register and thus the IRQ pin, too.

Interrupts are not cleared automatically when the event that caused them vanishes. Exceptions are IRQ_0 (PLL_LOCK) and IRQ_1 (PLL_UNLOCK) because the occurrence of one clears the other.

The supported interrupts for the Basic Operating Mode are summarized in Table 6-9 on page 29.

Table 6-9. Interrupt Description in Basic Operating Mode

IRQ Name Description Section
IRQ_7 (BAT_LOW) Indicates a supply voltage below the programmed threshold. 9.5.4
IRQ_6 (TRX_UR) Indicates a Frame Buffer access violation. 9.3.3
IRQ_5 (AMI) Indicates address matching. 7.2.3.5
IRQ_4 (CCA_ED_DONE)	Multi-functional interrupt:1. AWAKE_END:Indicates radio transceiver reached TRX_OFF state after P_ON, RESET, or SLEEP states.2. CCA_ED_DONE:Indicates the end of a CCA or ED measurement.	7.1.2.38.4.48.5.4
IRQ_3 (TRX_END)	RX: Indicates the completion of a frame reception.TX: Indicates the completion of a frame transmission.	7.1.37.1.3
IRQ_2 (RX_START)	Indicates the start of a PSDU reception. The TRX_STATE changes to BUSY_RX, the PHR is valid to read from Frame Buffer.	7.1.3
IRQ_1 (PLL_UNLOCK)	Indicates PLL unlock. If the radio transceiver is BUSY_TX / BUSY_TX_ARET state, the PA is turned off immediately.	9.7.5
IRQ_0 (PLL_LOCK)	Indicates PLL lock.	9.7.5

The interrupt IRQ_4 has two meanings, depending on the current radio transceiver state, refer to register 0x01 (TRX_STATUS).

After P_ON, SLEEP, or RESET, the radio transceiver issues an interrupt IRQ_4 (AWAKE_END) when it enters state TRX_OFF.

The second meaning is only valid for receive states. If the microcontroller initiates an energy-detect (ED) or clear-channel-assessment (CCA) measurement, the completion of the measurement is indicated by interrupt IRQ_4 (CCA_ED_DONE), refer to Section 8.4.4 "Interrupt Handling" on page 92 and Section 8.5.4 "Interrupt Handling" on page 95 for details.

After P_ON or RESET all interrupts are disabled. During radio transceiver initialization it is recommended to enable IRQ_4 (AWAKE_END) to be notified once the TRX_OFF state is entered.

Note that AWAKE_END interrupt can usually not be seen when the transceiver enters TRX_OFF state after RESET, because register 0x0E (IRQ_MASK) is reset to mask all interrupts. In this case, state TRX_OFF is normally entered before the microcontroller could modify the register.

The interrupt handling in Extended Operating Mode is described in Section 7.2.5 “Interrupt Handling” on page 67.

If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be read from IRQ_STATUS register even if the interrupt itself is masked. However, in that case no timing information for this interrupt is provided.

The IRQ pin polarity can be configured with register bit IRQ_POLARITY (register 0x04, TRX_CTRL_1). The default behavior is active high, which means that pin IRQ = H issues an interrupt request.

If "Frame Buffer Empty Indicator" is enabled during Frame Buffer read access the IRQ pin has an alternative functionality, refer to Section 11.7 "Frame Buffer Empty Indicator" on page 152 for details.

6.6.2 Register Description

Register 0x0E (IRQ\_MASK):

The IRQ_MASK register is used to enable or disable individual interrupts. An interrupt is enabled if the corresponding bit is set to 1. All interrupts are disabled after power up sequence (P_ON state) or reset (RESET state).

Bit 76543210 +0x0E MASK_BAT_LOW MASK_TRK_UR MASK_AMI MASK_CCA_ED_DONE MASK_TRX_END Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000

If an interrupt is enabled it is recommended to read the interrupt status register 0x0F (IRQ_STATUS) first to clear the history.

Register 0x0F (IRQ\_STATUS):

The IRQ_STATUS register contains the status of the pending interrupt requests.

Bit	7	6	5	4	3	2	1	0
+0x0F	BAT_LOW	TRX_UR	AMI	CCA_ED_DONE	TRX_END	RX_START	PLL_UNLOCK	PLL_LOCK	IRQ_STATUS
Read/Write	R	R	R	R	R	R	R	R
Initial Value	0	0	0	0	0	0	0	0

By reading the register after an interrupt is signaled at pin 24 (IRQ) the source of the issued interrupt can be identified. A read access to this register resets all interrupt bits, and so clears the IRQ_STATUS register.

If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be read from IRQ_STATUS register even if the interrupt itself is masked. However in that case no timing information for this interrupt is provided.

If register bit IRQ_MASK_MODE is set, it is recommended to read the interrupt status register 0x0F (IRQ_STATUS) first to clear the history.

Register 0x04 (TRX\_CTRL\_1):

The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver.

Bit 76543210

+0x04	PA_EXT_EN	IRQ_2_EXT_EN	TX_AUTO_CRC_ON	RX_BL_CTRL	SPI_CMD_MODE		IRQ_MASK_MODE	IRQ_POLARITY	TRX_CTRL_1
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset Value	0 0 1 0 0 0 0 0

- Bit 7 - PA\_EXT\_EN

Refer to Section 11.5 "RX/TX Indicator" on page 147.

- Bit 6 - IRQ\_2\_EXT\_EN

The timing of a received frame can be determined by a separate pin. If register bit IRQ_2_EXT_EN is set to 1, the reception of a PHR is directly issued on pin 10 (DIG2), similar to interrupt IRQ_2 (RX_START). Note that this pin is also active even if the corresponding interrupt event IRQ_2 (RX_START) mask bit in register 0x0E (IRQ_MASK) is set to 0. The pin remains at high level until the end of the frame receive procedure.

For further details refer to Section 11.6 "RX Frame Time Stamping" on page 150.

- Bit 5 - TX\_AUTO\_CRC\_ON

Refer to Section 8.2 "Frame Check Sequence (FCS)" on page 85.

- Bit 4 - RX\_BL\_CTRL

Refer to Section 11.7 "Frame Buffer Empty Indicator" on page 152.

- Bit [3:2] - SPI\_CMD\_MODE

Refer to Section 6.3 "Radio Transceiver Status information" on page 24.

- Bit 1 - IRQ\_MASK\_MODE

The AT86RF231 supports polling of interrupt events. Interrupt polling can be enabled by register bit IRQ_MASK_MODE. Even if an interrupt request is masked by the corresponding bit in register 0x0E (IRQ_MASK), the event is indicated in register 0x0F (IRQ_STATUS).

Table 6-10. Interrupt Polling Configuration

Register Bit	Value	Description
IRQ_MASK_MODE	0	Interrupt polling disabled
	1	Interrupt polling enabled

- Bit 0 - IRQ\_POLARITY

The default polarity of the IRQ pin is active high. The polarity can be configured to active low via register bit IRQ_POLARITY, see Table 6-11 on page 32.

Table 6-11. Configuration of Pin 24 (IRQ)

Register Bit Value Description
IRQ_POLARITY 0	_	pin IRQ high active
	1 pin IRQ low active

This setting does not affect the polarity of the Frame Buffer Empty Indicator, refer to Section 11.7 "Frame Buffer Empty Indicator" on page 152. The Frame Buffer Empty Indicator is always active high.

7. Operating Modes

7.1 Basic Operating Mode

This section summarizes all states to provide the basic functionality of the AT86RF231, such as receiving and transmitting frames, the power up sequence and sleep. The Basic Operating Mode is designed for IEEE 802.15.4 and ISM applications; the corresponding radio transceiver states are shown in Figure 7.1 on page 33.

Figure 7-1. Basic Operating Mode State Diagram (for timing refer to Table 7-1 on page 42)

graph TD
    A["TRX_OFF (Clock State)"] -->|1| B["P_ON (Power-on after VDD)"]
    A -->|2| C["SLEEP (Sleep State)"]
    A -->|3| D["RESET"]
    A -->|4| E["BUSY_TX (Transmit State)"]
    A -->|5| F["RX_ON (Rx Listen State)"]
    A -->|6| G["BUSY_RX (Receive State)"]
    A -->|7| H["PLL_ON (PLL State)"]
    A -->|8| I["RX_ON"]
    A -->|9| J["PLL_ON"]
    A -->|10| K["FX_START"]
    A -->|11| L["FX Darf"]
    A -->|12| M["FX Delay Off"]
    A -->|13| N["FX Delay Off"]
    A -->|14| O["FX Delay Off"]
    P["XOSC=ON Pull=OFF"] -->|12| Q["FORCE_TRX_OFF (all states except SLEEP)"]
    R["XOSC=OFF Pull=OFF"] -->|13| S["/RST = H (all states except P_ON)"]
    T["RXR_ON"] -->|6| U["FX Darf"]
    V["RXR_ON"] -->|7| W["FX Delay Off"]
    X["RXR_ON"] -->|8| Y["FX Delay Off"]
    Z["RXR_ON"] -->|9| AA["FX Delay Off"]
    AB["RXR_ON"] -->|10| AC["FX Darf"]
    AD["RXR_ON"] -->|11| AE["FX Delay Off"]
    AF["RXR_ON"] -->|12| AG["FX Delay Off"]
    AH["RXR_ON"] -->|13| AI["FX Delay Off"]
    AJ["RXR_ON"] -->|14| AK["FX Delay Off"]
    AL["RXR_ON"] -->|SHR Detected| AM["FX Darf"]
    AN["RXR_ON"] -->|SLP_TR = H | AO["FX Delay Off"]
    AP["RXR_ON"] -->|SLP_TR = L | AQ["FX Delay Off"]
    AR["RXR_ON"] -->|SLP_TR = H or TX_START| AS["FX Delay Off"]
    AT["X State Transition number, see Table 7-1"] --> AU["Legend: Blue: SPI Write to Register TRX_STATE (0x02)"]
    AV["X State Transition number, see Table 7-1"] --> AW["Red: Control signals via IC Pin"]
    AX["X State Transition number, see Table 7-1"] --> AY["Green: Event"]

7.1.1 State Control

The radio transceiver states are controlled either by writing commands to register bits TRX_CMD (register 0x02, TRX_STATE), or directly by two signal pins: pin 11 (SLP_TR) and

pin 8 (/RST). A successful state change can be verified by reading the radio transceiver status from register 0x01 (TRX_STATUS).

If TRX_STATUS = 0x1F (STATE_TRANSITION_IN_PROGRESS) the AT86RF231 is on a state transition. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS.

Pin SLP_TR is a multifunctional pin, refer to Section 6.5 "Sleep/Wake-up and Transmit Signal (SLP_TR)" on page 27. Dependent on the radio transceiver state, a rising edge of pin SLP_TR causes the following state transitions:

• TRX_OFF SLEEP (level sensitive)
• RX_ON RX_ON_NOCLK (level sensitive)
• PLL_ON BUSY_TX

Whereas the falling edge of pin SLP_TR causes the following state transitions:

• SLEEP TRX_OFF (level sensitive)
• RX_ON_NOCLK RX_ON (level sensitive)

Pin 8 (/RST) causes a reset of all registers (register bits CLKM_CTRL are shadowed, for details refer to Section 9.6.4 "Master Clock Signal Output (CLKM)" on page 117) and forces the radio transceiver into TRX_OFF state. However, if the device was in P_ON state it remains in the P_ON state.

For all states except SLEEP, the state change commands FORCE_TRX_OFF or TRX_OFF lead to a transition into TRX_OFF state. If the radio transceiver is in active receive or transmit states (BUSY_ *), the command FORCE_TRX_OFF interrupts these active processes, and forces an immediate transition to TRX_OFF. In contrast a TRX_OFF command is stored until an active state (receiving or transmitting) has been finished. After that the transition to TRX_OFF is performed.

For a fast transition from receive or active transmit states to PLL_ON state the command FORCE_PLL_ON is provided. In contrast to FORCE_TRX_OFF this command does not disable the PLL and the analog voltage regulator AVREG. It is not available in states SLEEP, P_ON, RESET, TRX_OFF, and all *_NOCLK states.

The completion of each requested state change shall always be confirmed by reading the register bits TRX_STATUS (register 0x01, TRX_STATUS).

7.1.2 Basic Operating Mode Description

7.1.2.1 P\_ON - Power-On after V DD

When the external supply voltage ( V_DD ) is firstly applied to the AT86RF231, the radio transceiver goes into the P_ON state performing an on-chip reset. The crystal oscillator is activated and the default 1 MHz master clock is provided at pin 17 (CLKM) after the crystal oscillator has stabilized. CLKM can be used as a clock source to the microcontroller. The SPI interface and digital voltage regulator are enabled.

The on-chip power-on-reset sets all registers to their default values. A dedicated reset signal from the microcontroller at pin 8 (/RST) is not necessary, but recommended for hardware / software synchronization reasons.

All digital inputs are pulled-up or pulled-down during P_ON state, refer to Section 1.3.2 "Pull-Up and Pull-Down Configuration" on page 7. This is necessary to support microcontrollers where GPIO signals are floating after power on or reset. The input pull-up and pull-down circuitry is disabled when the radio transceiver leaves the P_ON state. Output pins DIG1/DIG2 are pulled-down to digital ground, whereas pins DIG3/DIG4 are pulled-down to analog ground, unless their configuration is changed.

Prior to leaving P_ON, the microcontroller must set the pins to the default operating values: SLP_TR = L, /RST = H and /SEL = H.

All interrupts are disabled by default. Thus, interrupts for state transition control are to be enabled first, e.g. enable IRQ_4 (AWAKE_END) to indicate a state transition to TRX_OFF state or interrupt IRQ_0 (PLL_LOCK) to signal a locked PLL in PLL_ON state. In P_ON state a first access to the radio transceiver registers is possible after a default 1 MHz master clock is provided at pin 17 (CLKM), refer to Table 7-1 on page 42.

Once the supply voltage has stabilized and the crystal oscillator has settled (see Section 12.5 "General RF Specifications" on page 158, parameter 12.5.7), a valid SPI write access to register bits TRX_CMD (register 0x02, TRX_STATE) with the command TRX_OFF or FORCE_TRX_OFF initiate a state change from P_ON towards TRX_OFF state, which is then indicated by an AWAKE_END interrupt if enabled.

7.1.2.2 SLEEP - Sleep State

In SLEEP state, the entire radio transceiver is disabled. No circuitry is operating. The radio transceiver current consumption is reduced to leakage current only. This state can only be entered from state TRX_OFF, by setting the pin SLP_TR = H.

If CLKM is enabled, the SLEEP state is entered 35 CLKM cycles after the rising edge at pin 11 (SLP_TR). At that time CLKM is turned off. If the CLKM output is already turned off (bits CLKM_CTRL = 0 in register 0x03), the SLEEP state is entered immediately. At clock rates 250 kHz and 62.5 kHz, the main clock at pin 17 (CLKM) is turned off immediately.

Setting SLP_TR = L returns the radio transceiver to the TRX_OFF state. During SLEEP the register contents remains valid while the content of the Frame Buffer and the security engine (AES) are cleared.

/RST = L in SLEEP state returns the radio transceiver to TRX_OFF state and thereby sets all registers to their default values. Exceptions are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0). These register bits require a specific treatment, for details see Section 9.6.4 "Master Clock Signal Output (CLKM)" on page 117.

7.1.2.3 TRX\_OFF - Clock State

In TRX_OFF the crystal oscillator is running and the master clock is available at pin 17 (CLKM) after the crystal oscillator has stabilized. The SPI interface and digital voltage regulator are enabled, thus the radio transceiver registers, the Frame Buffer and security engine (AES) are accessible (see Section 9.3 "Frame Buffer" on page 107 and Section 11.1 "Security Module (AES)" on page 128).

In contrast to P_ON state the pull-up and pull-down configuration is disabled.

Pin 11 (SLP_TR) and pin 8 (/RST) are available for state control. Note that the analog front-end is disabled during TRX_OFF.

Entering the TRX_OFF state from P_ON, SLEEP, or RESET state is indicated by interrupt IRQ_4 (AWAKE_END).

7.1.2.4 PLL\_ON - PLL State

Entering the PLL_ON state from TRX_OFF state enables the analog voltage regulator (AVREG) first. After the voltage regulator has been settled, the PLL frequency synthesizer is enabled. When the PLL has been settled at the receive frequency to a channel defined by register bits CHANNEL (register 0x08, PHY_CC_CCA), a successful PLL lock is indicated by issuing an interrupt IRQ_0 (PLL_LOCK).

If an RX_ON command is issued in PLL_ON state, the receiver is immediately enabled. If the PLL has not been settled before the state change nevertheless takes place. Even if the register bits TRX_STATUS (register 0x01, TRX_STATUS) indicates RX_ON, actual frame reception can only start once the PLL has locked.

The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4.

7.1.2.5 RX\_ON and BUSY\_RX - RX Listen and Receive State

In RX_ON state the receiver blocks and the PLL frequency synthesizer are enabled.

The AT86RF231 receive mode is internally separated into RX_ON state and BUSY_RX state. There is no difference between these states with respect to the analog radio transceiver circuitry, which are always turned on. In both states the receiver and the PLL frequency synthesizer are enabled.

During RX_ON state the receiver listens for incoming frames. After detecting a valid synchronization header (SHR), the AT86RF231 automatically enters the BUSY_RX state. The reception of a valid PHY header (PHR) generates an IRQ_2 (RX_START) and receives and demodulates the PSDU data.

During PSDU reception the frame data are stored continuously in the Frame Buffer until the last byte was received. The completion of the frame reception is indicated by an interrupt IRQ_3 (TRX_END) and the radio transceiver reenters the state RX_ON. At the same time the register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is updated with the result of the FCS check (see Section 8.2 "Frame Check Sequence (FCS)" on page 85).

Received frames are passed to the frame filtering unit, refer to Section 7.2.3.5 "Frame Filtering" on page 61. If the content of the MAC addressing fields (refer to IEEE 802.15.4-2006, Section 7.2.1) of a frame matches to the expected addresses, which is further dependent on the addressing mode, an address match interrupt IRQ_5 (AMI) is issued, refer to Section 6.6 "Interrupt Logic" on page 29. The expected address values are to be stored in registers 0x20 - 0x2B (Short address, PAN-ID and IEEE address). Frame filtering is available in Basic and Extended Operating Mode, refer to Section 7.2.3.5 "Frame Filtering" on page 61.

Leaving state RX_ON is only possible by writing a state change command to register bits TRX_CMD in register 0x02 (TRX_STATE).

7.1.2.6 RX\_ON\_NOCLK - RX Listen State without CLKM

If the radio transceiver is listening for an incoming frame and the microcontroller is not running an application, the microcontroller may be powered down to decrease the total system power consumption. This specific power-down scenario for systems running in clock synchronous mode (see Section 6. "Microcontroller Interface" on page 16), is supported by the AT86RF231 using the state RX_ON_NOCLK.

This state can only be entered by setting pin 11 (SLP_TR) = H while the radio transceiver is in the RX_ON state, refer to Section 7.1.2.5 "RX_ON and BUSY_RX - RX Listen and Receive State" on page 36. Pin 17 (CLKM) is disabled 35 clock cycles after the rising edge at the SLP_TR pin, see Figure 6-16 on page 28. This allows the microcontroller to complete its power-down sequence.

Note that for CLKM clock rates 250 kHz and 62.5 kHz the master clock signal CLKM is switched off immediately after rising edge of SLP_TR.

The reception of a frame shall be indicated to the microcontroller by an interrupt indicating the receive status. CLKM is turned on again, and the radio transceiver enters the BUSY_RX state (see Section 6.5 "Sleep/Wake-up and Transmit Signal (SLP_TR)" on page 27 and Figure 6-16 on page 28). Using this radio transceiver state it is essential to enable at least one interrupt indicating the reception status. Otherwise the reception of a frame does not activate CLKM and the microcontroller remains in its power-down mode.

After the receive transaction has been completed, the radio transceiver enters the RX_ON state. The radio transceiver only reenters the RX_ON_NOCLK state, when the next rising edge of pin SLP_TR pin occurs.

If the AT86RF231 is in the RX_ON_NOCLK state, and pin SLP_TR is reset to logic low, it enters the RX_ON state, and it starts to supply clock on the CLKM pin again.

In states RX_ON_NOCLK and RX_ON, the radio transceiver current consumptions are equivalent. However, the RX_ON_NOCLK current consumption is reduced by the current required for driving pin 17 (CLKM).

Note

- A reset in state RX_ON_NOCLK requires further to reset pin SLP_TR to logic low, otherwise the radio transceiver enters directly the SLEEP state.

7.1.2.7 BUSY\_TX - Transmit State

A transmission can only be initiated in state PLL_ON. There are two ways to start a transmission:

• Rising edge of pin 11 (SLP_TR)
• TX_START command to register bits TRX_CMD (register 0x02, TRX_STATE).

Either of these causes the radio transceiver into the BUSY_TX state.

During the transition to BUSY_TX state, the PLL frequency shifts to the transmit frequency. The actual transmission of the first data chip of the SHR starts after 16 s to allow PLL settling and PA ramp-up, see Figure 7-6 on page 41. After transmission of the SHR, the Frame Buffer content is transmitted. In case the PHR indicates a frame length of zero, the transmission is aborted.

After the frame transmission has completed, the AT86RF231 automatically turns off the power amplifier, generates an IRQ_3 (TRX_END) interrupt and returns into PLL_ON state.

7.1.2.8 RESET State

The RESET state is used to set back the state machine and to reset all registers of the AT86RF231 to their default values, exception are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0). These register bits require a specific treatment, for details see Section 9.6.4 "Master Clock Signal Output (CLKM)" on page 117.

A reset forces the radio transceiver into TRX_OFF state. If the device is still in the P_ON state it remains in the P_ON state though.

A reset is initiated with pin /RST = L and the state is left after setting /RST = H. The reset pulse should have a minimum length as specified in Section 12.4 "Digital Interface Timing Characteristics" on page 157 see parameter 12.4.13.

During reset the microcontroller has to set the radio transceiver control pins SLP_TR and /SEL to their default values.

An overview about the register reset values is provided in Table 14-1 on page 170.

7.1.3 Interrupt Handling

All interrupts provided by the AT86RF231 (see Table 6-9 on page 29) are supported in Basic Operating Mode.

For example, interrupts are provided to observe the status of radio transceiver RX and TX operations.

On receive IRQ_2 (RX_START) indicates the detection of a valid PHR first, IRQ_5 (AMI) an address match and IRQ_3 (TRX_END) the completion of the frame reception.

On transmit IRQ_3 (TRX_END) indicates the completion of the frame transmission.

Figure 7-2 on page 39 shows an example for a transmit/receive transaction between two devices and the related interrupt events in Basic Operating Mode. Device 1 transmits a frame containing a MAC header (in this example of length 7), payload and valid FCS. The frame is received by Device 2 which generates the interrupts during the processing of the incoming frame. The received frame is stored in the Frame Buffer.

The first interrupt IRQ_2 (RX_START) signals the reception of a valid PHR.

If the received frame passes the address filter, refer to Section 7.2.3.5 "Frame Filtering" on page 61, an address match interrupt IRQ_5 (AMI) is issued after the reception of the MAC header (MHR).

In Basic Operating Mode the third interrupt IRQ_3 (TRX_END) is issued at the end of the received frame. In Extended Operating Mode, refer to Section 7.2 "Extended Operating Mode" on page 47; the interrupt is only issued if the received frame passes the address filter and the FCS is valid. Further exceptions are explained in Section 7.2 "Extended Operating Mode" on page 47.

Processing delay t_IRQ is a typical value, refer to Section 12.4 “Digital Interface Timing Characteristics” on page 157.

Figure 7-2. Timing of RX_START, AMI and TRX_END Interrupts in Basic Operating Mode

-16 0 128 160 192 192+(9+m)*32 Time [µs] TRX_STATE PLL_ON BUSY_TX PLL_ON SLP_TR IRQ Typ. Processing Delay 16 µs Number of Octets 4 1 1 7 m 2 Frame Content Preamble SFD PHR MHR MSDU FCS TRX_STATE RX_ON RX_ON BUSY_RX IRQ Interrupt latency tIRQ tIRQ tIRQ TX (Device1) Frame on Air TRX_ENDIRQ STRAME (Device 2)

7.1.4 Basic Operating Mode Timing

The following paragraphs depict state transitions and their timing properties. Timing figures are explained in Table 7-1 on page 42 and Section 12.4 “Digital Interface Timing Characteristics” on page 157.

7.1.4.1 Power-on Procedure

The power-on procedure to P_ON state is shown in Figure 7-3 on page 39.

Figure 7-3. Power-on Procedure to P_ON State

0 100 400 Time [µs] Event V_DD on CLKM on State P_ON Block XOSC, DVREG Time When the external supply voltage ( V_DD ) is firstly supplied to the AT86RF231, the radio transceiver enables the crystal oscillator (XOSC) and the internal 1.8 V voltage regulator for the digital domain (DVREG). After t_TR1 = 330 s (typ.), the master clock signal is available at pin 17 (CLKM) at default rate of 1 MHz. If CLKM is available the SPI is already enabled and can be used to control the transceiver. As long as no state change towards state TRX\_OFF is performed the radio transceiver remains in P\_ON state.

7.1.4.2 Wake-up Procedure

The wake-up procedure from SLEEP state is shown in Figure 7-4 on page 40. Figure 7-4. Wake-up Procedure from SLEEP State 

Event CLKM on IRQ_4 (AWAKE_END)SLP_TR = L State SLEEP TRX_OFF Block XOSC, DVREG XOSC, DVREGFTN Time tTR2

The radio transceivers SLEEP state is left by releasing pin SLP\_TR to logic low. This restarts the XOSC and DVREG. After t_TR2 = 380 s (typ.) the radio transceiver enters TRX\_OFF state. The internal clock signal is available and provided to pin 17 (CLKM), if CLKM was enabled. This procedure is similar to the Power-On Procedure. However the radio transceiver continues the state change automatically to the TRX\_OFF state. During this the filter-tuning network (FTN) calibration is performed. Entering TRX\_OFF state is signaled by IRQ\_4 (AWAKE\_END), if this interrupt was enabled by the appropriate mask register bit.

7.1.4.3 PLL\_ON and RX\_ON States

The transition from TRX\_OFF to PLL\_ON and RX\_ON mode is shown in Figure 7-5 on page 40. Figure 7-5. Transmission from TRX\_OFF to PLL\_ON and RX\_ON State 

0 100 Time [µs] Event State TRX_OFF Block Command Time IRQ_0 (PLL_LOCK) PLL_ON RX_ON AVREG PLL /RX PLL_ON R_ON tTR4 tTR8

Note: If TRX\_CMD = RX\_ON in TRX\_OFF state RX\_ON state is entered immediately, even if the PLL has not settled. In TRX\_OFF state, entering the commands PLL\_ON or RX\_ON initiates a ramp-up sequence of the internal 1.8V voltage regulator for the analog domain (AVREG). RX\_ON state can be entered any time from PLL\_ON state regardless whether the PLL has already locked, which is indicated by IRQ\_0 (PLL\_LOCK).

7.1.4.4 BUSY\_TX and RX\_ON States

The transition from PLL\_ON to BUSY\_TX state and subsequent to RX\_ON state is shown in Figure 7-6 on page 41. Figure 7-6. PLL\_ON to BUSY\_TX to RX\_ON Timing 

Time [µs] Pin SLP_TR State PLL_ON RX_ONBUSY_TX Block PLL PA PA, TX PLL RX Command—or command TX_START RX_ON Time → tTR10 ← ← tTR11 →

Starting from PLL\_ON state it is further assumed that the PLL is already locked. A transmission is initiated either by a rising edge of pin 11 (SLP\_TR) or by command TX\_START. The PLL settles to the transmit frequency and the PA is enabled. t_TR10 = 16 μs after initiating the transmission the AT86RF231 changes into BUSY\_TX state and the internally generated SHR is transmitted. After that the PSDU data are transmitted from the Frame Buffer. After completing the frame transmission, indicated by IRQ\_3 (TRX\_END), the PLL settles back to the receive frequency within t_TR11 = 32 s in state PLL\_ON. If during TX\_BUSY the radio transmitter is programmed to change to a receive state it automatically proceeds the state change to RX\_ON state after finishing the transmission.

7.1.4.5 Reset Procedure

The radio transceiver reset procedure is shown in Figure 7-7 on page 41. Figure 7-7. Reset Procedure 

0 x x + 10 x + 40 Time [µs] Event [IRQ_4 (AWAKE_END)] State various TRX_OFF Block XOSC, DVREG FTN XOSC, DVREG Pin /RST Time >t10 t >t11 TR13

Note: Timing figure t TR13 refers to Table 7-1 on page 42, t_10 , t_11 refers to Section 12.4 "Digital Interface Timing Characteristics" on page 157. /RST = L sets all registers to their default values. Exceptions are register bits CLKM\_CTRL (register 0x03, TRX\_CTRL\_0), refer to Section 9.6.4 "Master Clock Signal Output (CLKM)" on page 117. After releasing the reset pin (/RST = H) the wake-up sequence including an FTN calibration cycle is performed, refer to Section 9.8 "Automatic Filter Tuning (FTN)" on page 125. After that the TRX\_OFF state is entered. Figure 7-7 on page 41 illustrates the reset procedure once the P\_ON state was left and the radio transceiver was not in SLEEP state. The reset procedure is identical for all originating radio transceiver states except of state P\_ON and SLEEP state. Instead, here the procedure described in Section 7.1.2.1 "P\_ON - Power-On after VDD" on page 34 must be followed to enter the TRX\_OFF state. If the radio transceiver was in SLEEP state, the XOSC and DVREG are enabled before entering TRX\_OFF state. If register TRX\_STATUS indicates STATE\_TRANSITION\_IN\_PROGRESS during system initialization until the AT86RF231 reaches TRX\_OFF, do not try to initiate a further state change while the radio transceiver is in this state.

Notes

- The reset impulse should have a minimum length t_10 = 625 ns as specified in Section 12.4 "Digital Interface Timing Characteristics" on page 157, see parameter 12.4.13. - An access to the device should not occur earlier than t_11 625 ns after releasing the pin /RST; refer to Section 12.4 "Digital Interface Timing Characteristics" on page 157, parameter 12.4.14. - A reset overrides an SPI command request that might be queued.

7.1.4.6 State Transition Timing Summary

The transition numbers correspond to Figure 7-1 on page 33 and do not include SPI access time if not otherwise stated. See measurement setup in Figure 5-1 on page 12. Table 7-1. State Transition Timing

No	Symbol Transition Time [μs], (type) Comments
1	t_TR1	P_ON	⇒	until CLKM available	330	Depends on external capacitor at DVDD (1 μF nom) and crystal oscillator setup (CL = 10 pF)
2	t_TR2	SLEEP TRX_OFF	380			Depends on external capacitor at DVDD (1 μF nom) and crystal oscillator setup (CL = 10 pF)TRX_OFF state indicated by IRQ_4 (AWAKE_END)
3	t_TR3	TRX_OFF SLEEP	35*1/f	CLKM		For f_CLKM > 250 kHz
4	t_TR4	TRX_OFF PLL_ON	110 Depends on external capacitor at AVDD (1 μF nom)
5	t_TR5	PLL_ON	⇒	TRX_OFF	1
6	t_TR6	TRX_OFF RX_ON			110 Depends on external capacitor at AVDD (1 μF nom)
7	t_TR7	RX_ON	⇒	TRX_OFF	1
8	t_TR8	PLL_ON RX_ON
9	t_TR9	RX_ON	⇒	PLL_ON	1	Transition time is also valid for TX_ARET_ON, RX_AACK_ON
No	Symbol	Transition			Time [μs], (type)	Comments
10	t_TR10	PLL_ON BUS	SY≥TX	16		When asserting pin 11 (SLP_TR) or TRX_CMD = TX_START first symbol transmission is delayed by 16 μs delay (PLL settling and PA ramp up)
11	t_TR11	BUSY_TX P	LL≥ON	32 PLL settling time from TX_BUS	SY to PLL_ON state
12	t_TR12	All states TRX	OFF	1		Using TRX_CMD = FORCE_TRX_OFF (see register 0x02, TRX_STATE),Not valid for SLEEP state
13	t_TR13	RESET TRX	OFF	37 Valid for P	ON or SLEEP state
14	t_TR14	Various states	⇒	PLL_ON	1	Using TRX_CMD = FORCE_PLL_ON (see register 0x02, TRX_STATE),Not valid for SLEEP, P_ON, RESET, TRX_OFF and *_NOCLK

The state transition timing is calculated based on the timing of the individual blocks shown in Figure 7-3 on page 39 to Figure 7-7 on page 41. The worst case values include maximum operating temperature, minimum supply voltage, and device parameter variations. Table 7-2. Analog Block Initialization and Settling Time

No	Symbol	Block	Time [μs], (type)	Time [μs], (max)	Comment
15	t_TR15	XOSC	330	1000	Leaving SLEEP state, depends on crystal Q factor and load capacitor
16	t_TR16	FTN		25 FTN tuning time fixed
17	t_TR17	DVREG	60	1000	Depends on external bypass capacitor at DVDD (CB3 = 1 μF nom., 10 μF worst case), depends on V_DD
18	t_TR18	AVREG	60	1000	Depends on external bypass capacitor at AVDD (CB1 = 1 μF nom, 10 μF worst case), depends on V_DD
19	t_TR19	PLL, initial	110	155	PLL settling time TRX_OFF⇒PLL_ON, including 60 μs AVREG settling time
20	t_TR20	PLL settling	11	24	Settling time between channels switch
21	t_TR21	PLL, CF cal	35		PLL center frequency calibration, refer to Section 9.7.4
22	t_TR22	PLL, DCU cal	6		PLL DCU calibration, refer to Section 9.7.4
23	t_TR23	PLL, RX⇒TX	16		Maximum PLL settling time RX⇒TX
24	t_TR24	PLL, TX⇒RX	32		Maximum PLL settling time TX⇒RX
25	t_TR25	RSSI, update	2		RSSI update period in receive states, refer to Section 8.3.2
26	t_TR26	ED	140		ED measurement period, refer to Section 8.4.2
27	t_TR27	SHR, sync	96		Typical SHR synchronisation period, refer to Section 8.4.2
28	t_TR28	CCA	140		CCA measurement period, refer to Section 8.5.2
29	t_TR29	Random value	1		Random value update period, refer to Section 11.2.1

7.1.5 Register Description

Register 0x01 (TRX\_STATUS):

A read access to TRX\_STATUS register signals the current radio transceiver state. A state change is initiated by writing a state transition command to register bits TRX\_CMD (register 0x02, TRX\_STATE). Alternatively a state transition can be initiated by the rising edge of pin 11 (SLP\_TR) in the appropriate state. This register is used for Basic and Extended Operating Mode, refer to Section 7.2 “Extended Operating Mode” on page 47. Bit 76543210

+0x01	CCA_DONE	CCA_STATUS	Reserved	TRX_STATUS					TRX_STATUS
Read/Write	R	R	R	R	R	R	R	R
Reset Value	0 0 0 0 0 0 0

\- Bit 7 - CCA\_DONE Refer to Section 8.5 "Clear Channel Assessment (CCA)" on page 94. \- Bit 6 - CCA\_STATUS Refer to Section 8.5 "Clear Channel Assessment (CCA)" on page 94. \- Bit 5 - Reserved \- Bit [4:0] - TRX\_STATUS The register bits TRX\_STATUS signals the current radio transceiver status. If the requested state transition is not completed yet, the TRX\_STATUS returns STATE\_TRANSITION\_IN\_PROGRESS. Do not try to initiate a further state change while the radio transceiver is in STATE\_TRANSITION\_IN\_PROGRESS. State transition timings are defined in Table 7-1 on page 42. Table 7-3. Radio Transceiver Status, Register Bits TRX\_STATUS

Register Bits Value State Description
TRX_STATUS 0x00	____	P_ON
	0x01 BUSY_RX
	0x02 BUSY_TX
	0x06 RX_ON
	0x08 TRX_OFF (CLK Mode)
	0x09 PLL_ON (TX_ON)
	0x0F^(3)	SLEEP
	0x11^(1)	BUSY_RX_AACK
	0x12^(1)	BUSY_TX_ARET
	0x16^(1)	RX_AACK_ON
	0x19^(1)	TX_ARET_ON
	0x1C RX_ON_NOCLK
	0x1D^(1)	RX_AACK_ON_NOCLK
	0x1E^(1)	BUSY_RX_AACK_NOCLK
	0x1F^(2)	STATE_TRANSITION_IN_PROGRESS
		All other values are reserved

Notes: 1. Extended Operating Mode only, refers to Section 7.2 "Extended Operating Mode" on page 47. 2. Do not try to initiate a further state change while the radio transceiver is in STATE\_TRANSITION\_IN\_PROGRESS state. 3. In SLEEP state register not accessible.

Register 0x02 (TRX\_STATE):

The radio transceiver states are controlled via register bits TRX\_CMD, which receives the state transition commands. This register is used for Basic and Extended Operating Mode, refer to Section 7.2 “Extended Operating Mode” on page 47. 

B i t 7 6 5 4 3 2 +0x02 TRAC_STATUS TRX_CMD TRX_STATE Read/Write R R R R/W R/W R/W R/W R/W Reset Value 0 0 0 0 0 0 0

- Bit [7:5] - TRAC\_STATUS

Refer to Section 7.2.7 "Register Description - Control Registers" on page 68.

- Bit [4:0] - TRX\_CMD

A write access to register bits TRX\_CMD initiate a radio transceiver state transition towards the new state as defined by the write access: Table 7-4. State Control Command, Register Bits TRX\_CMD

Register Bit	Value	State Description
TRX_CMD	0x00	NOP
	0x02	TX_START
	0x03	FORCE_TRX_OFF
	0x04^(1)	FORCE_PLL_ON
	0x06	RX_ON
	0x08	TRX_OFF (CLK Mode)
	0x09	PLL_ON (TX_ON)
	0x16^(2)	RX_AACK_ON
	0x19^(2)	TX_ARET_ON
		All other values are reserved and mapped to NOP

Notes: 1. FORCE\_PLL\_ON is not valid for states SLEEP, P\_ON, RESET, TRX\_OFF, and all \*\_NOCLK states, as well as STATE\_TRANSITION\_IN\_PROGRESS towards these states. 2. Extended Operating Mode only, refers to Section 7.2.7 "Register Description - Control Registers" on page 68.

7.2 Extended Operating Mode

The Extended Operating Mode is a hardware MAC accelerator and goes beyond the basic radio transceiver functionality provided by the Basic Operating Mode. It handles time critical MAC tasks, requested by the IEEE 802.15.4 standard, by hardware, such as automatic acknowledgement, automatic CSMA-CA and retransmission. This results in a more efficient IEEE 802.15.4 software MAC implementation including reduced code size and may allow the use of a smaller microcontroller or to operate at low clock rates. The Extended Operating Mode is designed to support IEEE 802.15.4-2006 compliant frames; the mode is backward compatible to IEEE 802.15.4-2003 and supports non IEEE 802.15.4 compliant frames. This mode comprises the following procedures:

Automatic acknowledgement (RX\_AACK) divides into the tasks:

• Frame reception and automatic FCS check - Configurable addressing fields check - Interrupt indicating address match - Interrupt indicating frame reception, if it passes address filtering and FCS check - Automatic ACK frame transmission (if the received frame passed the address filter and FCS check and if an ACK is required by the frame type and ACK request) - Support of slotted acknowledgment using SLP\_TR pin

Automatic CSMA-CA and Retransmission (TX\_ARET) divides into the tasks:

• CSMA-CA including automatic CCA retry and random back-off • Frame transmission and automatic FCS field generation - Reception of ACK frame (if an ACK was requested) • Automatic frame retry if ACK was expected but not received - Interrupt signaling with transaction status Automatic FCS check and generation, refer to Section 8.2 "Frame Check Sequence (FCS)" on page 85, is used by the RX\_AACK and TX\_ARET modes. In RX\_AACK mode, an automatic FCS check is always performed for incoming frames. In TX\_ARET mode, an ACK, received within the time required by IEEE 802.15.4, is accepted if the FCS is valid, and if the sequence number of the ACK matches the sequence number of the previously transmitted frame. Dependent on the value of the frame pending subfield in the received acknowledgement frame the transaction status is set, see Table 7-16 on page 70. An AT86RF231 state diagram including the Extended Operating Mode states is shown in Figure 7-8 on page 48. Yellow marked states represent the Basic Operating Mode; blue marked states represent the Extended Operating Mode. Figure 7-8. Extended Operating Mode State Diagram 

graph TD
    A["TRX_OFF (Clock State)"] -->|12 13| B["BUSY_RX (Receive State)"]
    A -->|12 13| C["RX_ON (Rx Listen State)"]
    A -->|12 13| D["PLL_ON (PLL State)"]
    A -->|12 13| E["SLEEP (Sleep State)"]
    A -->|12 13| F["RESET"]
    A -->|12 13| G["BUSY_TX (Transmit State)"]
    A -->|12 13| H["BUSY_RX_AACK"]
    A -->|12 13| I["RX_ON_NOCLK (Rx Listen State)"]
    A -->|12 13| J["RX_AACK_ON_NOCLK"]
    A -->|12 13| K["TX_ARET_ONRX_AACK_BOSY_TX_ARET"]
    A -->|12 13| L["P_ON (Power-on after V_DD)"]
    A -->|12 13| M["SLEEP (Sleep State)"]
    A -->|12 13| N["RESET"]
    A -->|12 13| O["FX_TR=H"]
    A -->|12 13| P["FX_TR=L"]
    A -->|12 13| Q["FX_TR=H"]
    A -->|12 13| R["FX_TR=H"]
    A -->|12 13| S["FX_TR=H"]
    A -->|12 13| T["FX_TR=H"]
    A -->|12 13| U["FX_TR=H"]
    A -->|12 13| V["FX_TR=H"]
    A -->|12 13| W["FX_TR=H"]
    A -->|12 13| X["FX_TR=H"]
    A -->|12 13| Y["FX_TR=H"]
    A -->|12 13| Z["FX_TR=H"]
    A -->|12 13| AA["FX_TR=H"]
    A -->|12 13| AB["FX_TR=H"]
    A -->|12 13| AC["FX_TR=H"]
    A -->|12 13| AD["FX_TR=H"]
    A -->|12 13| AE["FX_TR=H"]
    A -->|12 13| AF["FX_TR=H"]
    A -->|12 13| AG["FX_TR=H"]
    A -->|12 13| AH["FX_TR=H"]
    A -->|12 13| AI["FX_TR=H"]
    A -->|12 13| AJ["FX_TR=H"]
    A -->|12 13| AK["FX_TR=H"]
    A -->|12 13| AL["FX_TR=H"]
    A -->|12 13| AM["FX_TR=H"]
    A -->|12 13| AN["FX_TR=H"]
    A -->|12 13| AO["FX_TR=H"]
    A -->|12 13| AP["FX_TR=H"]
    A -->|12 13| AQ["FX_TR=H"]
    A -->|12 13| AR["FX_TR=H"]
    A -->|12 13| AS["FX_TR=H"]
    A -->|12 13| AT["FX_TR=H"]
    A -->|12 13| AU["FX_TR=H"]
    A -->|12 13| AV["FX_TR=H"]
    A -->|12 13| AW["FX_TR=H"]
    A -->|12 13| AX["FX_TR=H"]
    A -->|12 13| AY["FX_TR=H"]
    A -->|12 13| AZ["FX_TR=H"]
    A -->|12 13| BA["FX_TR=H"]
    A -->|12 13| BB["FX_TR=H"]
    A -->|12 13| BC["FX_TR=H"]
    A -->|12 13| BD["FX_TR=H"]
    A -->|12 13| BE["FX_TR=H"]
    A -->|12 13| BF["FX_TR=H"]
    A -->|12 13| BG["FX_TR=H"]
    A -->|12 13| BH["FX_TR=H"]
    A -->|12 13| BI["FX_TR=H"]
    A -->|12 13| BJ["FX_TR=H"]
    A -->|12 13| BK["FX_TR=H"]
    A -->|12 13| BL["FX_TR=H"]
    A -->|12 13| BM["FX_TR=H"]
    A -->|12 13| BN["FX_TR=H"]
    A -->|12 13| BO["FX_TR=H"]
    A -->|12 13| BP["FX_TR=H"]
    A -->|12 13| BQ["FX_TR=H"]

Legend: Blue: SPI Write to Register TRX\_STATE (0x02) Red: Control signals via IC Pin Green: Event Basic Operating Mode States Extended Operating Mode States

7.2.1 State Control

The Extended Operating Mode states RX\_AACK and TX\_ARET are controlled via register bits TRX\_CMD (register 0x02, TRX\_STATE), which receives the state transition commands. The states are entered from TRX\_OFF or PLL\_ON state as illustrated by Figure 7-8 on page 48. The completion of each state change command shall always be confirmed by reading the register 0x01 (TRX\_STATUS).

RX\_AACK - Receive with Automatic ACK

A state transition to RX\_AACK\_ON from PLL\_ON or TRX\_OFF is initiated by writing the command RX\_AACK\_ON to the register bits TRX\_CMD. The state change can be confirmed by reading register 0x01 (TRX\_STATUS), those changes to RX\_AACK\_ON or BUSY\_RX\_AACK on success. The latter one is returned if a frame is currently about being received. The RX\_AACK state is left by writing command TRX\_OFF or PLL\_ON to the register bits TRX\_CMD. If the AT86RF231 is within a frame receive or acknowledgment procedure (BUSY\_RX\_AACK) the state change is executed after finish. Alternatively, the commands FORCE\_TRX\_OFF or FORCE\_PLL\_ON can be used to cancel the RX\_AACK transaction and change into radio transceiver state TRX\_OFF or PLL\_ON, respectively.

TX\_ARET - Transmit with Automatic Retry and CSMA-CA Retry

Similarly, a state transition to TX\_ARET\_ON from PLL\_ON or TRX\_OFF is initiated by writing command TX\_ARET\_ON to register bits TRX\_CMD. The radio transceiver is in the TX\_ARET\_ON state after TRX\_STATUS (register 0x01) changes to TX\_ARET\_ON. The TX\_ARET transaction is started with a rising edge of pin 11 (SLP\_TR) or writing the command TX\_START to register bits TRX\_CMD. The TX\_ARET state is left by writing the command TRX\_OFF or PLL\_ON to the register bits TRX\_CMD. If the AT86RF231 is within a CSMA-CA, a frame-transmit or an acknowledgment procedure (BUSY\_TX\_ARET) the state change is executed after finish. Alternatively the command FORCE\_TRX\_OFF or FORCE\_PLL\_ON can be used to instantly terminate the TX\_ARET transaction and change into radio transceiver state TRX\_OFF or PLL\_ON, respectively.

Note

\- A state change request from TRX\_OFF to RX\_AACK\_ON or TX\_ARET\_ON internally passes the state PLL\_ON to initiate the radio transceiver. Thus the readiness to receive or transmit data is delayed accordingly. It is recommended to use interrupt IRQ\_0 (PLL\_LOCK) as an indicator.

7.2.2 Configuration

The use of the Extended Operating Mode is based on Basic Operating Mode functionality. Only features beyond the basic radio transceiver functionality are described in the following sections. For details on the Basic Operating Mode refer to Section 7.1 "Basic Operating Mode" on page 33. When using the RX\_AACK or TX\_ARET modes, the following registers needs to be configured.

RX\_AACK configuration steps:

- Short address, PAN-ID and IEEE address registers 0x20 - 0x2B - Configure RX\_AACK properties registers 0x2C, 0x2E - Handling of Frame Version Subfield – Handling of Pending Data Indicator – Characterize as PAN coordinator – Handling of Slotted Acknowledgement • Additional Frame Filtering Properties registers 0x17, 0x2E - Promiscuous Mode - Enable or disable automatic ACK generation – Handling of reserved frame types The addresses for the address match algorithm are to be stored in the appropriate address registers. Additional control of the RX\_AACK mode is done with register 0x17 (XAH\_CTRL\_1) and register 0x2E (CSMA\_SEED\_1). As long as a short address has not been set, only broadcast frames and frames matching the IEEE address can be received. Configuration examples for different device operating modes and handling of various frame types can be found in Section 7.2.3.1 "Description of RX\_AACK Configuration Bits" on page 54.

TX\_ARET configuration steps:

- Leave register bit TX\_AUTO\_CRC\_ON = 1 register 0x04, TRX\_CTRL\_1 - Configure CSMA-CA - MAX\_FRAME\_RETRIES register 0x2C, XAH\_CTRL\_0 - MAX\_CSMA\_RETRIES register 0x2C, XAH\_CTRL\_0 - CSMA\_SEED registers 0x2D, 0x2E - MAX\_BE, MIN\_BE register 0x2F, CSMA\_BE \- Configure CCA (see Section 8.5) MAX\_FRAME\_RETRIES (register 0x2C) defines the maximum number of frame retransmissions. The register bits MAX\_CSMA\_RETRIES (register 0x2C) configure the number of CSMA-CA retries after a busy channel is detected. The CSMA\_SEED\_0 and CSMA\_SEED\_1 register bits (registers 0x2D, 0x2E) define a random seed for the back-off-time random-number generator in the AT86RF231. The MAX\_BE and MIN\_BE register bits (register 0x2F) sets the maximum and minimum CSMA back-off exponent (according to [1]).

7.2.3 RX\_AACK\_ON - Receive with Automatic ACK

The general functionality of the RX\_AACK procedure is shown in Figure 7-9 on page 53. The gray shaded area is the standard flow of an RX\_AACK transaction for IEEE 802.15.4 compliant frames, refer Section 7.2.3.2 "Configuration of IEEE Scenarios" on page 55. All other procedures are exceptions for specific operating modes or frame formats, refer to Section 7.2.3.3 "Configuration of non IEEE 802.15.4 Compliant Scenarios" on page 58. The frame filtering operations is described in detail in Section 7.2.3.5 "Frame Filtering" on page 61. In RX\_AACK\_ON state, the radio transceiver listens for incoming frames. After detecting a valid PHR, the radio transceiver parses the frame content of the MAC header (MHR), refer to Section 8.1.2 "MAC Protocol Layer Data Unit (MPDU)" on page 80. Generally, at nodes, configured as a normal device or PAN coordinator, a frame is not indicated if the frame filter does not match and the FCS is invalid. Otherwise, the interrupt IRQ\_3 (TRX\_END) is issued after the completion of the frame reception. The microcontroller can then read the frame. An exception applies if promiscuous mode is enabled; see Section 7.2.3.2 "Configuration of IEEE Scenarios" on page 55, in that case an IRQ\_3 (TRX\_END) interrupt is issued, even if the FCS fails. If the content of the MAC addressing fields of the received frame (refer to IEEE 802.15.4 section 7.2.1) matches one of the configured addresses, dependent on the addressing mode, an address match interrupt IRQ\_5 (AMI) is issued, refer to Section 7.2.3.5 "Frame Filtering" on page 61. The expected address values are to be stored in registers 0x20 - 0x2B (Short address, PAN-ID and IEEE address). Frame filtering as described in Section 7.2.3.5 "Frame Filtering" on page 61 is also valid for Basic Operating Mode. During reception the AT86RF231 parses bit [5] (ACK Request) of the frame control field of the received data or MAC command frame to check if an ACK reply is expected. In that case and if the frame passes the third level of filtering, see IEEE 802.15.4-2006, section 7.5.6.2, the radio transceiver automatically generates and transmits an ACK frame. The content of the frame pending subfield of the ACK response is set by register bit AACK\_SET\_PD (register 0x2E, CSMA\_SEED\_1) when the ACK frame is sent in response to a data request MAC command frame, otherwise this subfield is set to 0. The sequence number is copied from the received frame. Optionally, the start of the transmission of the acknowledgement frame can be influenced by register bit AACK\_ACK\_TIME. Default value (according to standard IEEE 802.15.4) is 12 symbol times after the reception of the last symbol of a data or MAC command frame. If the register bit AACK\_DIS\_ACK (register 0x2E, CSMA\_SEED\_1) is set, no acknowledgement frame is sent even if an acknowledgment frame was requested. This is useful for operating the MAC hardware accelerator in promiscuous mode, see Section 7.2.3.2 "Configuration of IEEE Scenarios" on page 55. The status of the RX\_AACK operation is indicated by register bits TRAC\_STATUS (register 0x02, TRAC\_STATUS), see Section 7.2.7 "Register Description - Control Registers" on page 68. During the operations described above the AT86RF231 remains in BUSY\_RX\_AACK state. Figure 7-9. Flow Diagram of RX\_AACK 

graph TD
    A["TRX_STATE = RX_AACK_ON"] --> B{SHR detected}
    B -->|Y| C["TRX_STATE = BUSY_RX_AACK"]
    C --> D["Generate IRQ_2 (RX_START)"]
    D --> E["Scanning MHR"]
    E --> F{Frame Filtering}
    F -->|N| G["Generate IRQ_5 (AMI)"]
    F -->|Y| H["FCS valid (see Note 2)"]
    H --> I["Generate IRQ_3 (TRX_END)"]
    I --> J{ACK requested (see Note 3)}
    J -->|N| K{Slotted Operation == 0}
    J -->|Y| L["AACK_ACK_TIME == 0"]
    K --> M{AACK_ACK_TIME == 0}
    L --> N["AACK_ACK_TIME == 0"]
    M --> O["Wait 2 symbol periods"]
    N --> P["Wait 6 symbol periods"]
    O --> Q["Wait 12 symbol periods"]
    P --> R["Wait 2 symbol periods"]
    Q --> S{pin 11 (SLP_TR) rising edge}
    R --> S
    S --> T["Transmit ACK"]
    T --> U["TRX_STATE = RX_AACK_ON"]

    V["Promiscuous Mode"] --> W["Frame reception"]
    W --> X{AACK_PROM_MODE == 1}
    X -->|N| Y["FCF[2:0"] > 3]
    X -->|Y| Z["AACK_UPLD_RES_FT == 1"]
    Z --> AA{FCS valid}
    AA -->|N| AB["Generate IRQ_3 (TRX_END)"]
    AA -->|Y| AC["Generate IRQ_3 (TRX_END)"]
    AB --> AD["End"]
    AC --> AD
    subgraph Promiscuous Mode
        V
        W
        X
        Y
        Z
        AA
        AC
        end

    subgraph Reserved Frames
        V
        Y
        Z
        AA
        AC
        end

    note1["Note 1: Address match, Promiscuous Mode and Reserved Frames:<br>- A radio transceiver in Promiscuous Mode, or configured to receive Reserved Frames handles received frames passing the third level of filtering<br>- For details refer to the description of Promiscuous Mode and Reserved Frame Types"]
    note2["Note 2: FCS check is omitted for Promiscous Mode"]
    note3["Note 3: Additional conditions:<br>- ACK requested &<br>- ACK_DIS_ACK==0 &<br>- frame_version<=AACK_FVN_MODE"]

7.2.3.1 Description of RX\_AACK Configuration Bits

Overview

Table 7-5 on page 54 summarizes all register bits which affect the behavior of an RX\_AACK transaction. For address filtering it is further required to setup address registers to match to the expected address. Configuration and address bits are to be set in TRX\_OFF or PLL\_ON state prior to switching to RX\_AACK mode. A graphical representation of various operating modes is illustrated in Figure 7-9 on page 53. Table 7-5. Overview of RX\_AACK Configuration Bits

Register Register Register Name DescriptionAddress Bits
0x20,0x210x22,0x230x24......0x2B		SHORT_ADDR_0/1PAN_ADDR_0/1IEEE_ADDR_0......IEEE_ADDR_7	Set node addresses
0x0C 7 RX_SAFE_MODE Protect buffer after frame receive
0x17 1 AACK_PROM_MODE Support promiscuous mode
0x17 2 AACK_ACK_TIME Change auto acknowledge start time
0x17 4 AACK_UPLD_RES_FT Enable reserved frame type reception, needed to receive non-standard compliant frames
0x17	5	AACK_FLTR_RES_FT	Filter reserved frame types like data frame type, needed for filtering of non-standard compliant frames
0x2C 0 SLOTTED_OPERATION If set, acknowledgment transmission has to be triggered by pin 11 (SLP_TR)
0x2E 3 AACK_I_AM_COORD If set, the device is a PAN coordinator
0x2E	4 AACK_DIS_ACK Disable generation of acknowledgment
0x2E	5 AACK_SET_PD Set frame pending subfield in Frame Control Field (FCF), refer to Section 8.1.2.2
0x2E	7:6	AACK_FVN_MODE	Controls the ACK behavior, depending on FCF frame version number

The usage of the RX\_AACK configuration bits for various operating modes of a node is explained in the following sections. Configuration bits not mentioned in the following two sections should be set to their reset values according to Table 14-1 on page 170. All registers mentioned in Table 7-5 on page 54 are described in Section 7.2.6 “Register Summary” on page 68. Note, that the general behavior of the "AT86RF231 Extended Feature Set", Section 11. "AT86RF231 Extended Feature Set" on page 128, settings: • OQPSK\_DATA\_RATE (PSDU data rate) - SFD\_VALUE (alternative SFD value) • ANT\_DIV (Antenna Diversity) - RX\_PDT\_LEVEL (blocking frame reception of lower power signals) are completely independent from RX\_AACK mode. Each of these operating modes can be combined with the RX\_AACK mode.

7.2.3.2 Configuration of IEEE Scenarios

Normal Device

Table 7-6 on page 55 shows a typical RX\_AACK configuration of an IEEE 802.15.4 device operating as a normal device, rather than a PAN coordinator or router. Table 7-6. Configuration of IEEE 802.15.4 Devices

Register Register Register Name DescriptionAddress Bits
0x20,0x210x22,0x230x24,......0x2B		SHORT_ADDR_0/1PAN_ADDR_0/1IEEE_ADDR_0......IEEE_ADDR_7	Set node addresses
0x0C 7 RX	SAFE_MODE	0	_: disable frame protection1: enable frame protection
0x2C	0	SLOTTED_OPERATION	0: if transceiver works in unslotted mode1: if transceiver works in slotted mode
0x2E	7:6	AACK_FVN_MODE	Controls the ACK behavior, depending on FCF frame version number0x00: acknowledges only frames with version number 0, i.e. according to IEEE 802.15.4-2003 frames0x01: acknowledges only frames with version number 0 or 1, i.e. frames according to IEEE 802.15.4-20060x10: acknowledges only frames with version number 0 or 1 or 20x11: acknowledges all frames, independent of the FCF frame version number

Notes

- If no short address has been configured before the device has been assigned one by the PAN-coordinator, only frames directed to either the broadcast address or the IEEE address are received. - In IEEE 802.15.4-2003 standard the frame version subfield did not yet exist but was marked as reserved. According to this standard, reserved fields have to be set to zero. On the other hand, IEEE 802.15.4-2003 standard requires ignoring reserved bits upon reception. Thus, there is a contradiction in the standard which can be interpreted in two ways: 1. If a network should only allow access to nodes which use the IEEE 802.15.4-2003, then AACK\_FVN\_MODE should be set to 0. 2. If a device should acknowledge all frames independent of its frame version, AACK\_FVN\_MODE should be set to 3. However, this can result in conflicts with co-existing IEEE 802.15.4-2006 standard compliant networks. The same holds for PAN coordinators, see Table 7-7 on page 56.

PAN-Coordinator

Table 7-7. Configuration of a PAN Coordinator

Register Register Register Name DescriptionAddress Bits
0x20,0x210x22,0x230x24,......0x2B		SHORT_ADDR_0/1PAN_ADDR_0/1IEEE_ADDR_0......IEEE_ADDR_7	Set node addresses
0x0C 7 RX_SAFE_MODE 0			_: disable frame protection1: enable frame protection
0x2C 0 SLOTTED_OPERATION 0			_: if transceiver works in unslotted mode1: if transceiver works in slotted mode
0x2E 3 ACK_I_AM_COORD 1: device is PAN coordinator
0x2E 5 ACK_SET_PD 0			_: frame pending subfield is not set in FC1: frame pending subfield is set in FCF
0x2E 7:6 AACK_FVN_MODE Controls the ACK behavior, depending on FCFframe version number0x00: acknowledges only frames with versionnumber 0, i.e. according to IEEE 802.15.4-2003frames0x01: acknowledges only frames with versionnumber 0 or 1, i.e. frames according to IEEE802.15.4-20060x10: acknowledges only frames with versionnumber 0 or 1 or 20x11: acknowledges all frames, independent ofthe FCF frame version number

Promiscuous Mode

The promiscuous mode is described in IEEE 802.15.4-2006, section 7.5.6.2. This mode is further illustrated in Figure 7-9 on page 53. According to IEEE 802.15.4-2006 when in promiscuous mode, the MAC sub layer shall pass received frames with correct FCS to the next higher layer and shall not be processed further. That implies that frames should never be acknowledged. Only second level filter rules as defined by IEEE 802.15.4-2006, section 7.5.6.2, are applied to the received frame. Table 7-8 on page 57 shows the typical configuration of a device operating promiscuous mode. Table 7-8. Configuration of Promiscuous Mode

Register Register Address Bits		ister Name Description
0x20,0x210x22,0x230x24,...0x2B		SHORT_ADDR_0/1PAN_ADDR_0/1IEEE_ADDR_0...IEEE_ADDR_7	Address shall be set: 0x00
0x17 1 ACK_PROM_MODE 1: Enable promiscuous Mode
0x2E 4 ACK_DIS_ACK 1: Disable generation of acknowledgment
0x2E 7:6 AACK_FVN_MODE Controls the ACK behavior, depending on FCF frame version number0x00: acknowledges only frames with version number 0, i.e. according to IEEE 802.15.4-2003 frames0x01: acknowledges only frames with version number 0 or 1, i.e. frames according to IEEE 802.15.4-20060x10: acknowledges only frames with version number 0 or 1 or 20x11: acknowledges all frames, independent of the FCF frame version number

If the radio transceiver is in promiscuous mode, second level of filtering according to IEEE 802.15.4-2006, section 7.5.6.2, is applied to a received frame. However, an IRQ\_3 (TRX\_END) is issued even if the FCS is invalid. Thus, it is necessary to read register bit RX\_CRC\_VALID (register 0x06, PHY\_RSSI) after IRQ\_3 (TRX\_END) in order to verify the reception of a frame with a valid FCS. If a device, operating in promiscuous mode, receives a frame with a valid FCS which further passed the third level of filtering according to IEEE 802.15.4-2006, section 7.5.6.2, an acknowledgement frame would be transmitted. According to the definition of the promiscuous mode a received frame shall not be acknowledged, even if it is requested. Thus register bit AACK\_DIS\_ACK (register 0x2E, CSMA\_SEED\_1) has to be set to 1. In all receive modes an IRQ\_5 (AMI) interrupt is issued, when the received frame matches the node's address according to the filter rules described in Section 7.2.3.5 "Frame Filtering" on page 61 Alternatively, in Basic Operating Mode RX\_ON state, when a valid PHR is detected, an IRQ\_2 (RX\_START) is generated and the frame is received. The end of the frame reception is signalized with an IRQ\_3 (TRX\_END). At the same time the register bit RX\_CRC\_VALID (register 0x06, PHY\_RSSI) is updated with the result of the FCS check (see Section 8.2 "Frame Check Sequence (FCS)" on page 85). According to the promiscuous mode definition the RX\_CRC\_VALID bit needs to be checked in order to dismiss corrupted frames.

7.2.3.3 Configuration of non IEEE 802.15.4 Compliant Scenarios

Sniffer

Table 7-9 on page 58 shows an RX\_AACK configuration to setup a sniffer device. Other RX\_AACK configuration bits, refer to Table 7-5 on page 54, should be set to their reset values. All frames received are indicated by an IRQ\_2 (RX\_START) and IRQ\_3 (TRX\_END). After frame reception register bit RX\_CRC\_VALID (register 0x06, PHY\_RSSI) is updated with the result of the FCS check (see Section 8.2 "Frame Check Sequence (FCS)" on page 85). The RX\_CRC\_VALID bit needs to be checked in order to dismiss corrupted frames. Table 7-9. Configuration of a Sniffer Device

Register Register Address Bits	ister Name Description
0x17 1 ACK_PROM_MODE 1: Enable promiscuous Mode
0x2E 4 ACK_DIS_ACK 1: Disable generation of acknowledgment

This operating mode is similar to the promiscuous mode.

Reception of Reserved Frames

In RX\_AACK mode, frames with reserved frame types, refer to Section 8.1.2.2 "Frame Control Field (FCF)" on page 80, can also be handled. This might be required when implementing proprietary, non-standard compliant, protocols. It is an extension of the address filtering in RX\_AACK mode. Received frames are either handled similar to data frames, or may be allowed to completely bypass the address filter. Table 7-10 on page 58 shows the required configuration for a node to receive reserved frames, Figure 7-9 on page 53 shows the corresponding flow chart. Table 7-10. RX\_AACK Configuration to Receive Reserved Frame Types

Register Register Address Bits		ister Name Description
0x20,0x210x22,0x230x24,......0x2B		SHORT_ADDR_0/1PAN_ADDR_0/1IEEE_ADDR_0......IEEE_ADDR_7	Set node addresses
0x0C 7 RX_SAFE_MODE 0			_: disable frame protection1: enable frame protection
0x17	4	AACK_UPLD_RES_FT	1: Enable reserved frame type reception
0x17 5 ACK_FLTR_RES_FT Filter reserved			frame types like data frame type,see note below0: disable1: enable
0x2C 0 SLOTTED_OPERATION 0			_: if transceiver works in unslotted mode1: if transceiver works in slotted mode

Table 7-10. RX\_AACK Configuration to Receive Reserved Frame Types (Continued)

0x2E 3 AACK_I_AM_COORD 0: device is not PAN coordinator1: device is PAN coordinator

0x2E 4 AACK_DIS_ACK 0: Enable generation of acknowledgment1: Disable generation of acknowledgment

0x2E 7:6 AACK_FVN_MODE Controls the ACK behavior, depending on FCF frame version number0x00: acknowledges only frames with version number 0, i.e. according to IEEE 802.15.4-2003 frames0x01: acknowledges only frames with version number 0 or 1, i.e. frames according to IEEE 802.15.4-20060x10: acknowledges only frames with version number 0 or 1 or 20x11: acknowledges all frames, independent of the FCF frame version number

There are two different options for handling reserved frame types. 1. AACK\_UPLD\_RES\_FT = 1, AACK\_FLT\_RES\_FT = 0: Any non-corrupted frame with a reserved frame type is indicated by an IRQ\_3 (TRX\_END) interrupt. No further address filtering is applied on those frames. An IRQ\_5 (AMI) interrupt is never generated and the acknowledgment subfield is ignored. 2. AACK\_UPLD\_RES\_FT = 1, AACK\_FLT\_RES\_FT = 1: If AACK\_FLT\_RES\_FT = 1 any frame with a reserved frame type is filtered by the address filter similar to a data frame as described in the standard. This implies the generation of the IRQ\_5 (AMI) interrupts upon address match. An IRQ\_3 (TRX\_END) interrupt is only generated if the address matched and the frame was not corrupted. An acknowledgment is only send, when the ACK request subfield was set in the received frame and an IRQ\_3 (TRX\_END) interrupt occurred. 3. AACK\_UPLD\_RES\_FT = 0: Any received frame indicated as a reserved frame is discarded.

Short Acknowledgment Frame (ACK) Start Timing

Register bit AACK\_ACK\_TIME (register 0x17, XAH\_CTRL\_1), see Table 7-11 on page 60, defines the symbol time between frame reception and transmission of an acknowledgment frame. Table 7-11. Overview of RX\_AACK Configuration Bits

Register Register Address Bit	ister Name Description
0x17 2 ACK_ACK_TIME		0: Standard compliant acknowledgement timing of 12 symbol periods. In slotted acknowledgement operation mode, the acknowledgment frame transmission can be triggered 6 symbol periods after reception of the frame earliest.1: Reduced acknowledgment timing of 2 symbol periods (32 μs).

Note that this feature can be used in all scenarios, independent of other configurations. However, shorter acknowledgment timing is especially useful when using High Data Rate Modes to increase battery lifetime and to improve the overall data throughput; refer to Section 11.3 "High Data Rate Modes" on page 137.

7.2.3.4 RX\_AACK\_NOCLK - RX\_AACK\_ON without CLKM

If the AT86RF231 is listening for an incoming frame and the microcontroller is not running an application, the microcontroller can be powered down to decrease the total system power consumption. This special power-down scenario for systems running in clock synchronous mode (see Section 6. "Microcontroller Interface" on page 16) is supported by the AT86RF231 using the state RX\_AACK\_ON\_NOCLK. The radio transceiver functionality in this state is based on that in state RX\_AACK\_ON with pin 17 (CLKM) disabled. The RX\_AACK\_NOCLK state is entered from RX\_AACK\_ON by a rising edge at pin 11 (SLP\_TR). The return to RX\_AACK\_ON state results either from a successful frame reception or a falling edge on pin SLP\_TR. The CLKM pin is disabled 35 clock cycles after the rising edge at SLP\_TR pin. This allows the microcontroller to complete its power-down sequence. This is not valid for clock rates 250 kHz and 62.5 kHz, where the main clock at pin 17 (CLKM) is switched off immediately. In case of the reception of a valid frame, IRQ\_3 (TRX\_END) is issued and pin 17 (CLKM) is turned on. A timing diagram is shown in Figure 6-16 on page 28. A received frame is considered valid if it passes address filtering and has a correct FCS. If an ACK was requested the radio transceiver enters BUSY\_RX\_AACK state and follows the procedure described in Section 7.2.3 "RX\_AACK\_ON - Receive with Automatic ACK" on page 51. After the transaction has been completed, the radio transceiver reenters the RX\_AACK\_ON state. The radio transceiver reenters the RX\_AACK\_ON\_NOCLK state only, when the next rising edge at SLP\_TR pin occurs. It is not recommended to operate the receiver in state RX\_AACK\_NOCLK with register bit SLOTTED\_OPERATION (register 0x2C, XAH\_XTRL\_0) set, refer to "Register Description - Control Registers" on page 68.

7.2.3.5 Frame Filtering

Frame Filtering is an evaluation whether or not a received frame is dedicated for this node. To accept a received frame and to generate an address match interrupt IRQ\_5 (AMI) a filtering procedure as described in IEEE 802.15.4-2006, section 7.5.6.2 (Third level of filtering) is applied to the frame. The AT86RF231 RX\_AACK mode accepts only frames that satisfy all of the following requirements (quote from IEEE 802.15.4-2006, section 7.5.6.2): 1. The Frame Type subfield shall not contain a reserved frame type. 2. The Frame Version subfield shall not contain a reserved value. 3. If a destination PAN identifier is included in the frame, it shall match macPANId or shall be the broadcast PAN identifier (0xFFFF). 4. If a short destination address is included in the frame, it shall match either macShortAddress or the broadcast address (0xFFFF). Otherwise, if an extended destination address is included in the frame, it shall match aExtendedAddress. 5. If the frame type indicates that the frame is a beacon frame, the source PAN identifier shall match macPANId unless macPANId is equal to 0xFFFF, in which case the beacon frame shall be accepted regardless of the source PAN identifier. 6. If only source addressing fields are included in a data or MAC command frame, the frame shall be accepted only if the device is the PAN coordinator and the source PAN identifier matches macPANId. The AT86RF231 requires satisfying two additional rules: 7. The frame type indicates that the frame is not an ACK frame (refer to Table 8-4 on page 82). 8. At least one address field must be configured. Address match, indicated by interrupt IRQ\_5 (AMI), is further controlled by the content of subfields of the frame control field of a received frame according to the following rule: If (Destination Addressing Mode = 0 OR 1) AND (Source Addressing Mode = 0) no IRQ\_5 (AMI) is generated, refer to Section 8.1.2.2 "Frame Control Field (FCF)" on page 80. This effectively causes all acknowledgement frames not to be announced, which otherwise always pass the filter, regardless of whether they are intended for this device or not. For backward compatibility to IEEE 802.15.4-2003 third level filter rule 2 (Frame Version) can be disabled by register bits AACK\_FVN\_MODE (register 0x2E, CSMA\_SEED\_1). Frame filtering is available in Extended and Basic Operating Mode, refer to Section 7.1 "Basic Operating Mode" on page 33, a frame passing the frame filtering generates an IRQ\_5 (AMI), if enabled.

Notes

- Filter rule 1 is affected by register bits AACK\_FLTR\_RES\_FT and AACK\_UPLD\_RES\_FT, Section 7.2.7 "Register Description - Control Registers" on page 68. - Filter rule 2 is affected by register bits AACK\_FVN\_MODE, Section 7.2.7 "Register Description - Control Registers" on page 68.

7.2.3.6 RX\_AACK Slotted Operation - Slotted Acknowledgement

AT86RF231 supports slotted acknowledgement operation, refer to IEEE 802.15.4-2006, section 7.5.6.4.2, in conjunction with the microcontroller. In RX\_AACK mode with register bit SLOTTED\_OPERATION (register 0x2C, XAH\_CTRL\_0) set, the transmission of an acknowledgement frame has to be controlled by the microcontroller. If an ACK frame has to be transmitted, the radio transceiver expects a rising edge on pin 11 (SLP\_TR) to actually start the transmission. This waiting state is signaled 6 symbol periods after the reception of the last symbol of a data or MAC command frame by register bits TRAC\_STATUS (register 0x02, XAH\_CTRL\_0), which are set to SUCCESS\_WAIT\_FOR\_ACK in that case. In networks using slotted operation the start of the acknowledgment frame, and thus the exact timing, must be provided by the microcontroller. A timing example of an RX\_AACK transaction with register bit SLOTTED\_OPERATION (register 0x2C, XAH\_CTRL\_0) set is shown in Figure 7-10 on page 62. The acknowledgement frame is ready to transmit 6 symbol times after the reception of the last symbol of a data or MAC command frame. The transmission of the acknowledgement frame is initiated by the microcontroller with the rising edge of pin 11 (SLP\_TR) and starts t_TR10 = 16 s later. The interrupt latency t_IRQ is specified in Section 12.4 "Digital Interface Timing Characteristics" on page 157, parameter 12.4.17. Figure 7-10. Example Timing of an RX\_AACK Transaction for Slotted Operation 

64 5120 704 1026 time [µs] Frame Type 9FD Data Frame (Length = 10, ACK=1) ACK Frame TRX_STATE RX_AACK_ON BUSY_RX_AACK RX_AACK_ON RX/TX RX TX RX IRQ TRX_END RX/TX Typ. Processing Delay tRC 96 µs ACK transmission initiated by microcontroller (8 symbols) SLP_TR waiting period signalled by register bits TRAC_STATUS SLP_TR tree

If register bit AACK\_ACK\_TIME (register 0x17, XAH\_CTRL\_1) is set, an acknowledgment frame can be sent already 2 symbol times after the reception of the last symbol of a data or MAC command frame.

7.2.3.7 RX\_AACK Mode Timing

A timing example of an RX\_AACK transaction is shown in Figure 7-11 on page 63. In this example a data frame of length 10 with an ACK request is received. The AT86RF231 changes to state BUSY\_RX\_AACK after SFD detection. The completion of the frame reception is indicated by a TRX\_END interrupt. Interrupts IRQ\_2 (RX\_START) and IRQ\_5 (AMI) are disabled in this example. The ACK frame is automatically transmitted after a default wait period of 12 symbols (192 s), register bit AACK\_ACK\_TIME = 0 (reset value). The interrupt latency t_IRQ is specified in Section 12.4 “Digital Interface Timing Characteristics” on page 157, parameter 12.4.17. Figure 7-11. Example Timing of an RX\_AACK Transaction 

64 5120 704 1088 time [µs] Frame Type Data Frame (Length = 10, ACK=1) ACK Frame TRX_STATE RX_AACK_ON BUSY_RX_ACK RX_AACK_ON RX/TX RX-TX RX IRQ Typ. Processing Delay t_ro 192 µs (12 symbols) Frame on Air RX/TX

If register bit AACK\_ACK\_TIME (register 0x17, XAH\_CTRL\_1) is set, an acknowledgment frame is sent already 2 symbol times after the reception of the last symbol of a data or MAC command frame.

7.2.4 TX\_ARET\_ON - Transmit with Automatic Retry and CSMA-CA Retry

Figure 7-12. Flow Diagram of TX\_ARET 

graph TD
    A["TRX_STATE = TX_ARET_ON"] --> B["frame_rctr = 0"]
    B --> C{Start TX}
    C -->|N| D["TRX_STATE = BUSY_TX_ARET TRAC_STATUS = INVALID"]
    C -->|Y| E["Max_CSMA_RETRIES <7"]
    E --> F["csma_rctr = 0"]
    F --> G["Random Back-Off csma_rctr = csma_rctr + 1 CCA"]
    G --> H{CCA Result}
    H -->|N| I["csma_rctr > MAX_CSMA_RETRIES"]
    H -->|Y| J["Success"]
    I --> K["Transmit Frame frame_rctr = frame_rctr + 1"]
    K --> L{ACK requested}
    L -->|N| M["Receive ACK until timeout"]
    L -->|Y| N{ACK valid}
    N -->|N| O["force_rctr > MAX_FRAME_RETRIES"]
    N -->|Y| P["TRAC_STATUS = NO_ACK"]
    O --> Q["Data Pending"]
    Q --> R["TRAC_STATUS = SUCCESS_DATA_PENDING"]
    Q --> S["TRAC_STATUS = SUCCESS"]
    Q --> T["TRAC_STATUS = CHANNEL_ACCESS_FAILURE"]
    R --> U["Issue IRQ_3 (TRX_END) interrupt"]
    S --> U
    T --> U
    U --> V["TRX_STATE = TX_ARET_ON"]
    style A fill:#f9f,stroke:#333
    style V fill:#ccf,stroke:#333

Overview

The implemented TX\_ARET algorithm is shown in Figure 7-12 on page 64. In TX\_ARET mode, the AT86RF231 first executes the CSMA-CA algorithm, as defined by IEEE 802.15.4-2006, section 7.5.1.4, initiated by a transmit start event. If the channel is IDLE a frame is transmitted from the Frame Buffer. If the acknowledgement frame is requested the radio transceiver additionally checks for an ACK reply. The completion of the TX\_ARET transmit transaction is indicated by an IRQ\_3 (TRX\_END) interrupt.

Description

Configuration and address bits are to be set in TRX\_OFF or PLL\_ON state prior to switching to TX\_ARET mode. It is further recommended to transfer the PSDU data to the Frame Buffer in advance. The transaction is started by either using pin 11 (SLP\_TR), refer to Section 6.5 "Sleep/Wake-up and Transmit Signal (SLP\_TR)" on page 27, or writing a TX\_START command to register 0x02 (TRX\_STATE). If the CSMA-CA detects a busy channel, it is retried as specified by the register bits MAX\_CSMA\_RETRIES (register 0x2C, XAH\_CTRL\_0). In case that CSMA-CA does not detect a clear channel after MAX\_CSMA\_RETRIES, it aborts the TX\_ARET transaction, issues interrupt IRQ\_3 (TRX\_END), and set the value of the TRAC\_STATUS register bits to CHANNEL\_ACCESS\_FAILURE. During transmission of a frame the radio transceiver parses bit 5 (ACK Request) of the MAC header (MHR) frame control field of the PSDU data (PSDU octet #1) to be transmitted to check if an ACK reply is expected. If an ACK is expected, the radio transceiver automatically switches into receive mode to wait for a valid ACK reply. After receiving an ACK frame the Frame Pending subfield of that frame is parsed and the status register bits TRAC\_STATUS are updated accordingly, refer to Table 7-12 on page 66. This receive procedure does not overwrite the Frame Buffer content. Transmit data in the Frame Buffer is not changed during the entire TX\_ARET transaction. Received frames other than the expected ACK frame are discarded. If no valid ACK is received or after timeout of 54 symbol periods (864 s), the radio transceiver retries the entire transaction, (including CSMA-CA) until the maximum number of retransmissions (as set by the register bits MAX\_FRAME\_RETRIES in register 0x2C (XAH\_CTRL\_0) is exceeded. After that, the microcontroller may read the value of the register bits TRAC\_STATUS (register 0x02, TRX\_STATE) to verify whether the transaction was successful or not. The register bits are set according to the following cases, additional exit codes are described in Section 7.2.6 "Register Summary" on page 68: Table 7-12. Interpretation of TRAC\_STATUS register bits

Value	Name Description
0	SUCCESS The transaction was responded by a valid ACK, or, if noACK is requested, after a successful frame transmission
1	SUCCESS_DATA_PENDING Equivalent to SUCCESS, indicates pending frame dataaccording to the MHR frame control field of the receivedACK response
3	CHANNEL_ACCESS_FAILURE Channel is still busy after MAX_CSMA_RETRIES ofCSMA-CA
5	NO_ACK No acknowledgement frames were received during all retryattempts
7	VALID Entering TX_ARET mode sets TRAC_STATUS = 7

Note that if no ACK is expected (according to the content of the received frame in the Frame Buffer), the radio transceiver issues IRQ\_3 (TRX\_END) directly after the frame transmission has been completed. The value of register bits TRAC\_STATUS (register 0x02, TRX\_STATE) is set to SUCCESS. A value of MAX\_CSMA\_RETRIES = 7 initiates an immediate TX\_ARET transaction without performing CSMA-CA. This is required to support slotted acknowledgement operation. Further the value MAX\_FRAME\_RETRIES is ignored and the TX\_ARET transaction is performed only once. A timing example of a TX\_ARET transaction is shown in Figure 7-13 on page 66. Figure 7-13. Example Timing of a TX\_ARET Transaction 

128 6720 x+352 time [µs]x FrameType Data Frame (Length = 10, ACK=1) ACK Frame TRX_STATE TX_ARET_ON BUSY_TX_ARET TX_ARET_ON RX/TX CSMA-CA TX RX SLP_TR IRQ Typ. Processing Delay tCSMA-CA 16 µs 32 µs tIRQ RX/TX TRX_END

Note: t CSMA-CA defines the random CSMA-CA processing time Here an example data frame of length 10 with an ACK request is transmitted, see Table 7-13 on page 67. After that the AT86RF231 switches to receive mode and expects an acknowledgement response. During the whole transaction including frame transmit, wait for ACK and ACK receive the radio transceiver status register TRX\_STATUS (register 0x01, TRX\_STATUS) signals BUSY\_TX\_ARET. A successful reception of the acknowledgment frame is indicated by IRQ\_3 (TRX\_END). The status register TRX\_STATUS (register 0x01, TRX\_STATUS) changes back to TX\_ARET\_ON. The TX\_ARET status register TRAC\_STATUS changes as well to TRAC\_STATUS = SUCCESS or TRAC\_STATUS = SUCCESS\_DATA\_PENDING if the frame pending subfield of the received ACK frame was set to 1.

7.2.5 Interrupt Handling

The interrupt handling in the Extended Operating Mode is similar to the Basic Operating Mode, refer to Section 7.1.3 "Interrupt Handling" on page 38. The microcontroller enables interrupts by setting the appropriate bit in register 0x0E (IRQ\_MASK). For RX\_AACK and TX\_ARET the following interrupts inform about the status of a frame reception and transmission: Table 7-13. Interrupt Handling in Extended Operating Mode

Mode Interrupt Description
RX_AACK IRQ_2 (RX_START)		Indicates a PHR reception
		IRQ_5 (AMI) Issued at address match
		IRQ_3 (TRX_END) Signals completion of RX_AACK transaction if successful- A received frame must pass the address filter- The FCS is valid
TX_ARET IRQ_3 (TRX_END) Signals completion of TX_ARET transaction
Both IRQ_0	(PLL_LOCK) Entering	RX_AACK_ON or TX_ARET_ON state from TRX_OFF state, the PLL_LOCK interrupt signals that the transaction can be started

RX\_AACK

For RX\_AACK it is recommended to enable IRQ\_3 (TRX\_END). This interrupt is issued only if a frame passes the frame filtering, refer to Section 7.2.3.5 "Frame Filtering" on page 61 and has a valid FCS. This is in contrast to Basic Operating Mode, refer to Section 7.1.3 "Interrupt Handling" on page 38. The use of the other interrupts is optional. On reception of a valid PHR an IRQ\_2 (RX\_START) is issued. IRQ\_5 (AMI) indicates address match, refer to filter rules in Section 7.2.3.5 "Frame Filtering" on page 61, and the completion of a frame reception with a valid FCS is indicated by interrupt IRQ\_3 (TRX\_END). Thus, it can happen that an IRQ\_2 (RX\_START) and/or IRQ\_5 (AMI) are issued, but no IRQ\_3 (TRX\_END) interrupt.

TX ARET

In TX\_ARET interrupt IRQ\_3 (TRX\_END) is only issued after completing the entire TX\_ARET transaction. Acknowledgement frames do not issue IRQ\_5 (AMI) or IRQ\_3 (TRX\_END) interrupts. All other interrupts as described in Section 6.6 "Interrupt Logic" on page 29, are also available in Extended Operating Mode.

7.2.6 Register Summary

The following registers are to be configured to control the Extended Operating Mode: Table 7-14. Register Summary

Reg.-Addr Register Name Description
0x01 TRX_STATUS Radio transceiver status, CCA result
0x02 TRX_STATE Radio transceiver state control, TX_ARET status
0x04 TRX_CTRL_1		TX_AUTO_CRC_ON
0x08 PHY_CC_CCA CCA mode control, see Section 8.5.6
0x09 CCA_THRES CCA threshold settings, see Section 8.5.6
0x17 XAH_CTRL_1 RX_AACK control
0x20 - 0x2B Address filter configuration - Short address, PAN-ID and IEEE address
0x2C	XAH_CTRL_0 TX_ARET control, retries value control
0x2D	CSMA_SEED_0	CSMA-CA seed value
0x2E	CSMA_SEED_1	CSMA-CA seed value, RX_AACK control
0x2F	CSMA_BE	CSMA-CA back-off exponent control

7.2.7 Register Description - Control Registers

Register 0x01 (TRX\_STATUS):

The read-only register TRX\_STATUS signals the present state of the radio transceiver as well as the status of a CCA application. A state change is initiated by writing a state transition command to register bits TRX\_CMD (register 0x02, TRX\_STATE). 

- Bit 7 - CCA\_DONE

Refer to Section 8.5 “Clear Channel Assessment (CCA)” on page 94, not updated in Extended Operating Mode.

- Bit 6 - CCA\_STATUS

Refer to Section 8.5 “Clear Channel Assessment (CCA)” on page 94, not updated in Extended Operating Mode.

- Bit 5 - Reserved

- Bit [4:0] - TRX\_STATUS

The register bits TRX\_STATUS signal the current radio transceiver status. Table 7-15. Radio Transceiver Status

Register Bit Value State	Description
TRX_STATUS 0x00	____	P_ON
	0x01 BUSY_RX
	0x02 BUSY_TX
	0x06 RX_ON
	0x08 TRX_OFF (CLK Mode)
	0x09 PLL_ON (TX_ON)
	0x0F^(1)	SLEEP
	0x11 BUSY_RX_AACK
	0x12 BUSY_TX_ARET
	0x16 RX_AACK_ON
	0x19 TX_ARET_ON
	0x1C RX_ON_NOCLK
	0x1D RX_AACK_ON_NOCLK
	0x1E BUSY_RX_AACK_NOCLK
	0x1F^(2)	STATE_TRANSITION_IN_PROGRESS
		All other values are reserved

Notes: 1. In SLEEP state register not accessible. 2. Do not try to initiate a further state change while the radio transceiver is in STATE\_TRANSITION\_IN\_PROGRESS state.

Register 0x02 (TRX\_STATE):

The AT86RF231 radio transceiver states are controlled via register TRX\_STATE using register bits TRX\_CMD. The read-only register bits TRAC\_STATUS indicate the status or result of an Extended Operating Mode transaction. A successful state transition shall be confirmed by reading register bits TRX\_STATUS (register 0x01, TRX\_STATUS). Register bits TRX\_CMD are used for Extended and Basic Operating Mode, refer to Section 7.1 "Basic Operating Mode" on page 33. 

- Bit [7:5] - TRAC\_STATUS

The status of the RX\_AACK and TX\_ARET procedure is indicated by register bits TRAC\_STATUS. Details of the algorithm and a description of the status information are given in Section 7.2.3 "RX\_AACK\_ON - Receive with Automatic ACK" on page 51 and Section 7.2.4 "TX\_ARET\_ON - Transmit with Automatic Retry and CSMA-CA Retry" on page 64. Table 7-16. TRAC\_STATUS Transaction Status

Register Bits Value Description RX_AACK TX_ARET
TRAC_STATUS 0	_(1)	SUCCESS X X
	1 SUCCESS_DATA_PENDING			X
	2 SUCCESS_WAIT_FOR_ACK	X
	3 CHANNEL_ACCESS_FAILURE			X
	5	NO_ACK		X
	7^(1)	INVALID	XX
		All other values are reserved

Notes: 1. Even though the reset value for register bits TRAC\_STATUS is 0, the RX\_AACK and TX\_ARET procedures set the register bits to TRAC\_STATUS = 7 (INVALID) when it is started.

TX\_ARET

SUCCESS\_DATA\_PENDING: Indicates a successful reception of an ACK frame with frame pending bit set to 1.

RX\_AACK

SUCCESS\_WAIT\_FOR\_ACK: Indicates an ACK frame is about to sent in RX\_AACK slotted acknowledgement. Slotted acknowledgement operation must be enabled with register bit SLOTTED\_OPERATION (register 0x2C, XAH\_XTRL\_0). The microcontroller must pulse pin 11 (SLP\_TR) at the next back-off slot boundary in order to initiate a transmission of the ACK frame. For details refer to IEEE 802.15.4-2006, section 7.5.6.4.2.

- Bit [4:0] - TRX\_CMD

A write access to register bits TRX\_CMD initiate a radio transceiver state transition: Table 7-17. State Control Register

Register Bit	Value	State Description
TRX_CMD	0x00	NOP
	0x02	TX_START
	0x03	FORCE_TRX_OFF
	0x04^(1)(2)	FORCE_PLL_ON
	0x06	RX_ON
	0x08	TRX_OFF (CLK Mode)
	0x09	PLL_ON (TX_ON)
	0x16	RX_AACK_ON
	0x19	TX_ARET_ON
		All other values are reserved and mapped to NOP

Notes: 1. FORCE\_PLL\_ON is not valid for states SLEEP, P\_ON, RESET, TRX\_OFF, and all \*\_NOCLK states, as well as STATE\_TRANSITION\_IN\_PROGRESS towards these states. 2. Using FORCE\_PLL\_ON to interrupt an TX\_ARET transaction, it is recommended to check register bits [7:5] of register address 0x32 for value 0. If this value is different, TRX\_CMD sequence FORCE\_TRX\_OFF shall be used immediately followed by TRX\_CMD sequence PLL\_ON. This performs a state transition to PLL\_ON.

Register 0x04 (TRX\_CTRL\_1):

The TRX\_CTRL\_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit 76543210

+0x04	PA_EXT_EN	IRQ_2_EXT_EN	TX_AUTO_CRC_ON	RX_BL_CTRL	SPI_CMD_MODE		IRQ_MASK_MODE	IRQ_POLARITY	TRX_CTRL_1
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset Value	0 0 1 0 0 0		0 0

\- Bit 7 - PA\_EXT\_EN Refer to Section 11.5 "RX/TX Indicator" on page 147. \- Bit 6 - IRQ\_2\_EXT\_EN Refer to Section 11.6 "RX Frame Time Stamping" on page 150. \- Bit 5 - TX\_AUTO\_CRC\_ON If set, register bit TX\_AUTO\_CRC\_ON enables the automatic FCS generation. For further details refer to Section 8.2 "Frame Check Sequence (FCS)" on page 85. \- Bit 4 - RX\_BL\_CTRL Refer to Section 11.7 "Frame Buffer Empty Indicator" on page 152. \- Bit [3:2] - SPI\_CMD\_MODE Refer to Section 6.3 "Radio Transceiver Status information" on page 24. \- Bit 1 - IRQ\_MASK\_MODE Refer to Section 6.6 "Interrupt Logic" on page 29. \- Bit 0 - IRQ\_POLARITY Refer to Section 6.6 "Interrupt Logic" on page 29.

Register 0x17 (XAH\_CTRL\_1):

The XAH\_CTRL\_1 register is a control register for Extended Operating Mode.

Bit	7	6	5	4	3	2	1	0
+0x17	Reserved		AACK_FLTR_RES_FT	AACK_UPLD_RES_FT	Reserved	AACK_ACK_TIME	AACK_PROM_MODE	Reserved
Read/Write	R/W	R	R/W	R/W	R	R/W	R/W	R
Reset Value	0	0	0	0	0	0	0	0

\- Bit [7:6] - Reserved

- Bit 5 - AACK\_FLTR\_RES\_FT

This register bit shall only be set if AACK\_UPLD\_RES\_FT = 1. If AACK\_FLTR\_RES\_FT = 1 reserved frame types are filtered similar to data frames as specified in IEEE 802.15.4-2006. Reserved frame types are explained in IEEE 802.15.4, section 7.2.1.1.1. If AACK\_FLTR\_RES\_FT = 0 the received reserved frame is only checked for a valid FCS.

- Bit 4 - AACK\_UPLD\_RES\_FT

If AACK\_UPLD\_RES\_FT = 1 received frames indicated as a reserved frame are further processed. For those frames, an IRQ\_3 (TRX\_END) interrupt is generated if the FCS is valid. In conjunction with the configuration bit AACK\_FLTR\_RES\_FT set, these frames are handled like IEEE 802.15.4 compliant data frames during RX\_AACK transaction. An IRQ\_5 (AMI) interrupt is issued, if the addresses in the received frame match the node's addresses. That means, if a reserved frame passes the third level filter rules, an acknowledgement frame is generated and transmitted if it was requested by the received frame. If this is not wanted register bit AACK\_DIS\_ACK (register 0x2E, CSMA\_SEED\_1) has to be set.

- Bit 3 - Reserved

- Bit 2 - AACK\_ACK\_TIME

According to IEEE 802.15.4, section 7.5.6.4.2, the transmission of an acknowledgment frame shall commence 12 symbols (aTurnaroundTime) after the reception of the last symbol of a data or MAC command frame. This is achieved with the reset value of the register bit AACK\_ACK\_TIME. Alternatively, if AACK\_ACK\_TIME = 1 an acknowledgment frame is sent already 2 symbol periods after the reception of the last symbol of a data or MAC command frame. This may be applied to proprietary networks or networks using the High Data Rate Modes to increase battery lifetime and to improve the overall data throughput; refer to Section 11.3 "High Data Rate Modes" on page 137. This setting affects also to acknowledgment frame response time for slotted acknowledgement operation, see Section 7.2.3.6 "RX\_AACK Slotted Operation - Slotted Acknowledgement" on page 62.

- Bit 1 - AACK\_PROM\_MODE

Register bit AACK\_PROM\_MODE enables the promiscuous mode, within the RX\_AACK mode; refer to IEEE 802.15.4-2006, section 7.5.6.5. If this bit is set, every incoming frame with a valid PHR finishes with IRQ\_3 (TRX\_END) interrupt even if the third level filter rules do not match or the FCS is not valid. Register bit RX\_CRC\_VALID (register 0x06, PHY\_RSSI) is set accordingly. Here, if a frame passes the third level filter rules, an acknowledgement frame is generated and transmitted unless disabled by register bit AACK\_DIS\_ACK (register 0x2E, CSMA\_SEED\_1).

- Bit 0 - Reserved

Register 0x2C (XAH\_CTRL\_0):

Register 0x2C (XAH\_CTRL\_0) is a control register for Extended Operating Mode. 

B i t 7 6 5 4 3 2 1 +0x2C MAX_FRAME_RETRIES MAX_CSMA_RETRIES SLOTTED_OPERATION XAH_CTRL_0 Read/Write R/W R/W R/W R/W R/W R/W R/W Reset Value 0 0 1 1 1 0 0 0

- Bit [7:4] - MAX\_FRAME\_RETRIES

The setting of MAX\_FRAME\_RETRIES in TX\_ARET mode specifies the number of attempts to retransmit a frame, when it was not acknowledged by the recipient, before the transaction gets cancelled.

- Bit [3:1] - MAX\_CSMA\_RETRIES

MAX\_CSMA\_RETRIES specifies the number of retries in TX\_ARET mode to repeat the CSMA-CA procedure before the transaction gets cancelled. According IEEE 802.15.4 the valid range of MAX\_CSMA\_RETRIES is [0, 1, ..., 5]. A value of MAX\_CSMA\_RETRIES = 7 initiates an immediate frame transmission without performing CSMA-CA. This may especially be required for slotted acknowledgement operation. MAX\_CSMA\_RETRIES = 6 is reserved.

- Bit 0 - SLOTTED\_OPERATION

Using RX\_AACK mode in networks operating in beacon or slotted mode, refer to IEEE 802.15.4 2006, section 5.5.1, register bit SLOTTED\_OPERATION indicates that acknowledgement frames are to be sent on back-off slot boundaries (slotted acknowledgement). If this register bit is set the acknowledgement frame transmission has to be initiated by the microcontroller using the rising edge of pin 11 (SLP\_TR). This waiting state is signaled in subregister TRAC\_STATUS (register 0x02, TRX\_STATE) with value SUCCESS\_WAIT\_FOR\_ACK. Table 7-18. Register Bit Slotted Acknowledgement Operation

Register Bit	Value	State Description
SLOTTED_OPERATION	0	The radio transceiver operates in unslotted mode. An acknowledgment frame is automatically sent if requested.
	1	Refer to Section 7.2.3.6. The transmission of an acknowledgement frame has to be controlled by the microcontroller.

Register 0x2D (CSMA\_SEED\_0):


- Bit [7:0] - CSMA\_SEED\_0

This register contains the lower 8-bit of the CSMA\_SEED, bits [7:0]. The higher 3 bit are part of register bits CSMA\_SEED\_1 (register 0x2E, CSMA\_SEED\_1). CSMA\_SEED is the seed for the random number generation that determines the length of the back-off period in the CSMA-CA algorithm. It is recommended to initialize registers CSMA\_SEED by random values. This can be done using register bits RND\_VALUE (register 0x06, PHY\_RSSI), refer to Section 11.2 "Random Number Generator" on page 136.

Register 0x2E (CSMA\_SEED\_1):

The CSMA\_SEED\_1 register is a control register for RX\_AACK and contains a part of the CSMA\_SEED for the CSMA-CA algorithm. 

Bit 7 6 5 4 3 2 1 +0x2E AACK_FVN_MODE AACH_SET_PD AACK_DIS_ACK AACK_I_AM_C OORD CSMA_SEED_1 CSMA_SEED_1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 0 1 0 0 0 0 1

Note: The register bits CSMA\_SEED\_0/1 content initializes the TX\_ARET random backoff generator after leaving SLEEP state. To prevent a reinitialization with the same value it is recommended to reinitialize all register bits with random values before entering SLEEP state.

- Bit [7:6] - AACK\_FVN\_MODE

The frame control field of the MAC header (MHR) contains a frame version subfield. The setting of AACK\_FVN\_MODE specifies the frame filtering behavior of the AT86RF231. According to the content of these register bits the radio transceiver passes frames with a specific frame version number, number group, or independent of the frame version number. Thus the register bit AACK\_FVN\_MODE defines the maximum acceptable frame version. Received frames with a higher frame version number than configured do not pass the address filter and are not acknowledged. Table 7-19. Register Bit Slotted Acknowledgement Operation

Register Bit	Value	State Description
AACK_FVN_MODE	0	Acknowledge frames with version number 0
	1	Acknowledge frames with version number 0 or 1
	2	Acknowledge frames with version number 0 or 1 or 2
	3	Acknowledge independent of frame version number

The frame version field of the acknowledgment frame is set to 0x00 according to IEEE 802.15.4-2006, section 7.2.2.3.1, Acknowledgment frame MHR fields.

- Bit 5 - AACK\_SET\_PD

The content of AACK\_SET\_PD bit is copied into the frame pending subfield of the acknowledgment frame if the ACK is the answer to a data request MAC command frame. In addition, if register bits AACK\_FVN\_MODE (register 0x2E, CSMA\_SEED\_1) are configured to accept frames with a frame version other than 0 or 1, the content of register bit AACK\_SET\_PD is also copied into the frame pending subfield of the acknowledgment frame for any MAC command frame with a frame version of 2 or 3 that have the security enabled subfield set to 1. This is done in the assumption that a future version of the standard [1] might change the length or structure of the auxiliary security header, so it is not possible to safely detect whether the MAC command frame is actually a data request command or not.

- Bit 4 - AACK\_DIS\_ACK

If this bit is set no acknowledgment frames are transmitted in RX\_AACK Extended Operating Mode, even if requested.

- Bit 3 - AACK\_I\_AM\_COORD

This register bit has to be set if the node is a PAN coordinator. It is used for address filtering in RX\_AACK. If AACK\_I\_AM\_COORD = 1 and if only source addressing fields are included in a data or MAC command frame, the frame shall be accepted only if the device is the PAN coordinator and the source PAN identifier matches macPANId, for details refer to IEEE 802.15.4, section 7.5.6.2 (third-level filter rule 6).

- Bit [2:0] - CSMA\_SEED\_1

These register bits are the higher 3-bit of the CSMA\_SEED, bits [10:8]. The lower part is in register 0x2D (CSMA\_SEED\_0), see register CSMA\_SEED\_0 for details. Register 0x2F (CSMA\_BE): 

Bit 7 6 5 4 3 2 1 0 +0x2F MAX BE MIN BE CSMA BE Read/Write R/W R/W R/W R/W R/W R/W R/W Reset Value 0 1 0 1 0 0 1 1

- Bit [7:4] - MAX\_BE

Register bits MAX\_BE defines the maximum back-off exponent used in the CSMA-CA algorithm to generate a pseudo random number for back off the CCA. For details refer to IEEE 802.15.4-2006, Section 7.5.1.4. Valid values are [4'd8, 4'd7, ..., 4'd3].

- Bit [3:0] - MIN\_BE

Register bits MIN\_BE defines the minimum back-off exponent used in the CSMA-CA algorithm to generate a pseudo random number for back off the CCA. For details refer to IEEE 802.15.4-2006, Section 7.5.1.4. Valid values are [MAX\_BE, (MAX\_BE - 1), ..., 4'd0].

Note

\- If MIN\_BE = 0 and MAX\_BE = 0 the CCA back off period is always set to 0.

7.2.8 Register Description - Address Registers

Register 0x20 (SHORT\_ADDR\_0):

This register contains the lower 8 bit of the MAC short address for Frame Filter address recognition, bits [7:0]. 

B i t 7 6 5 4 3 2 1 0 +0x20 SHORT_ADDR_0[7:0] SHORT_ADDR_0 Read/Write R/W R/W R/W R/W R/W R/W R/W R e s e t V a l u e 1 1

Register 0x21 (SHORT\_ADDR\_1):

This register contains the upper 8 bit of the MAC short address for Frame Filter address recognition, bits [15:8]. 

B i t 7 6 5 4 3 2 1 0 +0x21 SHORT_ADDR_1[7:0] SHORT_ADDR_1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R e s e t Va l u e 1 1 1 1

Register 0x22 (PAN\_ID\_0):

This register contains the lower 8 bit of the MAC PAN ID for Frame Filter address recognition, bits [7:0]. 

B i t 7 6 5 4 3 2 1 0 +0x22 PAN_ID_0[7:0] PAN_ID_0 Read/Write R/W R/W R/W R/W R/W R/W R/W R e s e t V a l u e 1 1

Register 0x23 (PAN\_ID\_1):

This register contains the upper 8 bit of the MAC PAN ID for Frame Filter address recognition, bits [15:8]. 

B i t 7 6 5 4 3 2 1 0 +0x23 PAN_ID_1[7:0] PAN_ID_1 Read/Write R/W R/W R/W R/W R/W R/W R/W R e s e t V a l u e 1 1

Register 0x24 (IEEE\_ADDR\_0):

This register contains the lower 8 bit of the MAC IEEE address for Frame Filter address recognition, bits [7:0]. 

B i t 7 6 5 4 3 2 1 0 +0x24 IEEE ADDR_0[7:0] IEEE_ADDR_0 Read/Write R/W R/W R/W R/W R/W R/W R/W R e s e t V a l u e 0 0

Register 0x25 (IEEE\_ADDR\_1):

This register contains 8 bit of the MAC IEEE address for Frame Filter address recognition, bits [15:8]. 

B i t 7 6 5 4 3 2 1 0 +0x25 IEEE ADDR 1[7:0] IEEE ADDR 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R e s e t V a l u e 0 0

Register 0x26 (IEEE\_ADDR\_2):

This register contains 8 bit of the MAC IEEE address for Frame Filter address recognition, bits [23:16]. 

B i t 7 6 5 4 3 2 1 0 +0x26 IEEE_ADDR_2[7:0] IEEE_ADDR_2 Read/Write R/W R/W R/W R/W R/W R/W R/W R e s e t V a l u e 0 0

Register 0x27 (IEEE\_ADDR\_3):

This register contains 8 bit of the MAC IEEE address for Frame Filter address recognition, bits [31:24]. 

B i t 7 6 5 4 3 2 1 0 +0x27 IEEE_ADDR_3[7:0] IEEE_ADDR_3 Read/Write R/W R/W R/W R/W R/W R/W R/W R e s e t V a l u e 0 0

Register 0x28 (IEEE\_ADDR\_4):

This register contains 8 bit of the MAC IEEE address for Frame Filter address recognition, bits [39:32]. 

B i t 7 6 5 4 3 2 1 0 +0x28 IEEE ADDR 4[7:0] IEEE ADDR 4 Read/Write R/W R/W R/W R/W R/W R/W R/W R e s e t V a l u e 0 0

Register 0x29 (IEEE\_ADDR\_5):

This register contains 8 bit of the MAC IEEE address for Frame Filter address recognition, bits [47:40]. 

B i t 7 6 5 4 3 2 1 0 +0x29 IEEE ADDR 5[7:0] IEEE ADDR 5 Read/Write R/W R/W R/W R/W R/W R/W R/W R e s e t V a l u e 0 0

Register 0x2A (IEEE\_ADDR\_6):

This register contains 8 bit of the MAC IEEE address for Frame Filter address recognition, bits [55:48]. 

B i t 7 6 5 4 3 2 1 0 +0x2A IEEE_ADDR_6[7:0] IEEE_ADDR_6 Read/Write R/W R/W R/W R/W R/W R/W R/W R e s e t V a l u e 0 0

Register 0x2B (IEEE\_ADDR\_7):

This register contains the most significant 8 bits of the MAC IEEE Frame Filter address for address recognition, bits [63:56]. 

B i t 7 6 5 4 3 2 1 0 +0x2B IEEE_ADDR_7[7:0] IEEE_ADDR_7 Read/Write R/W R/W R/W R/W R/W R/W R/W R e s e t V a l u e 0 0

8. Functional Description

8.1 Introduction - IEEE 802.15.4 - 2006 Frame Format

Figure 8-1 on page 79 provides an overview of the physical layer (PHY) frame structure as defined by IEEE 802.15.4. Figure 8-2 on page 80 shows the frame structure of the medium access control (MAC) layer. Figure 8-1. IEEE 802.15.4 Frame Format - PHY-Layer Frame Structure (PPDU)

PHY Protocol Data Unit (PPDU)
Preamble Sequence	SFD	Frame Length	PHY Payload
5 octets Synchronization Header (SHR)		1 octet (PHR)	max. 127 octets PHY Service Data Unit (PSDU)
			MAC Protocol Data Unit (MPDU)

8.1.1 PHY Protocol Layer Data Unit (PPDU)

8.1.1.1 8.1.1.1 Synchronization Header (SHR)

The SHR consists of a four-octet preamble field (all zero), followed by a single byte start-of-frame delimiter (SFD) which has the predefined value 0xA7. During transmit, the SHR is automatically generated by the AT86RF231, thus the Frame Buffer shall contain PHR and PSDU only. The transmission of the SHR requires 160 s (10 symbols). As the SPI data rate is normally higher than the over-air data rate, this allows the microcontroller to initiate a transmission without having transferred the full frame data already. Instead it is possible to subsequently write the frame content. During frame reception, the SHR is used for synchronization purposes. The matching SFD determines the beginning of the PHR and the following PSDU payload data.

8.1.1.2 PHY Header (PHR)

The PHY header is a single octet following the SHR. The least significant 7 bits denote the frame length of the following PSDU, while the most significant bit of that octet is reserved, and shall be set to 0 for IEEE 802.15.4 compliant frames. On receive the PHR is returned as the first octet during Frame Buffer read access. Even though the standard only defines frame lengths ≤127 bytes, AT86RF231 is able to transmit and receive frame length values >127. For IEEE 802.15.4 compliant operation bit 7 has to be masked by SW. The reception of a valid PHR is signaled by an interrupt IRQ\_2 (RX\_START). On transmit the PHR is to be supplied by the microcontroller during Frame Buffer write access as the first octet.

8.1.1.3 PHY Payload (PHY Service Data Unit, PSDU)

The PSDU has a variable length between 0 and aMaxPHYPacketSize (127, maximum PSDU size in octets) whereas the last two octets are used for the Frame Check Sequence (FCS). The length of the PSDU is signaled by the frame length field (PHR), refer to Table 8-1 on page 80. The PSDU contains the MAC Protocol Layer Data Unit (MPDU). Received frames with a frame length field set to 0x00 (invalid PHR) are not signaled to the microcontroller. Table 8-1 on page 80 summarizes the type of payload versus the frame length value. Table 8-1. Frame Length Field - PHR

Frame Length Value Payload
0 - 4 Reserved
5 MPDU (Acknowledgement)
6 - 8 Reserved
9 - aMaxPHYPacketSize MPDU

8.1.2 MAC Protocol Layer Data Unit (MPDU)

Figure 8-2 on page 80 shows the frame structure of the MAC layer. Figure 8-2. IEEE 802.15.4 Frame Format - MAC-Layer Frame Structure (MPDU) 

8.1.2.1 MAC Header (MHR) Fields

The MAC header consists of the Frame Control Field (FCF), a sequence number, and the addressing fields (which are of variable length, and can even be empty in certain situations).

8.1.2.2 Frame Control Field (FCF)

The FCF consists of 16 bits, and occupies the first two octets of the MPDU or PSDU, respectively. Figure 8-3. IEEE 802.15.4-2006 Frame Control Field (FCF)

0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
Frame Type			Sec. Enabled	Frame Pending	ACK Request	Intra PAN	Reserved			Destination addressing mode		Frame Version		Source addressing mode
Frame Control Field 2 octets

- Bit [2:0]:

describes the frame type. Table 8-2 on page 81 summarizes frame types defined by IEEE 802.15.4, section 7.2.1.1.1. Table 8-2. Frame Control Field - Frame Type Subfield

Frame Control Field Bit Assignments Description
Frame Type Value b_2 b_1 b_0	Value
000 0 Beacon
001 1 Data
010 2 Acknowledge
011 3 MAC command
100 - 111 4 - 7 Reserved

This subfield is used for address filtering by the third level filter rules. Only frame types 0 - 3 pass the third level filter rules, refer to Section 7.2.3.5 "Frame Filtering" on page 61 Automatic address filtering by the AT86RF231 is enabled when using the RX\_AACK mode, refer to Section 7.2.3 "RX\_AACK\_ON - Receive with Automatic ACK" on page 51. However, a reserved frame (frame type value > 3) can be received if register bit AACK\_UPLD\_RES\_FT (register 0x17, XAH\_CTRL\_1) is set, for details refer to Section 7.2.3.3 "Configuration of non IEEE 802.15.4 Compliant Scenarios" on page 58. Address filtering is also provided in Basic Operating Mode, refer to Section 7.1 "Basic Operating Mode" on page 33.

- Bit 3 :

indicates whether security processing applies to this frame.

- Bit 4 :

is the "Frame Pending" subfield. This field can be set in an acknowledgment frame (ACK) in response to a data request MAC command frame. This bit indicates that the node, which transmitted the ACK, has more data to send to the node receiving the ACK. For acknowledgment frames automatically generated by the AT86RF231, this bit is set according to the content of register bit AACK\_SET\_PD in register 0x2E (CSMA\_SEED\_1) if the received frame was a data request MAC command frame.

- Bit 5 :

forms the "Acknowledgment Request" subfield. If this bit is set within a data or MAC command frame that is not broadcast, the recipient shall acknowledge the reception of the frame within the time specified by IEEE 802.15.4 (i.e. within 192 s for non beacon-enabled networks). The radio transceiver parses this bit during RX\_AACK mode and transmits an acknowledgment frame if necessary. In TX\_ARET mode this bit indicates if an acknowledgement frame is expected after transmitting a frame. If this is the case, the receiver waits for the acknowledgment frame, otherwise the TX\_ARET transaction is finished.

- Bit 6 :

the "Intra-PAN" subfield indicates that in a frame, where both, the destination and source addresses are present, the PAN-ID of the source address field is omitted. In RX\_AACK mode, this bit is evaluated by the address filter logic of the AT86RF231.

• Bit [1 1 : 1 0 ] :

the "Destination Addressing Mode" subfield describes the format of the destination address of the frame. The values of the address modes are summarized in Table 8-3 on page 82, according to IEEE 802.15.4. Table 8-3. Frame Control Field - Destination and Source Addressing Mode

Frame Control Field Bit Assignments Description
Addressing Mode b_11 b_10 b_15 b_14	Value
00 0 PAN identifier and address fields are not present
01 1 Reserved
10 2 Address field contains a 16-bit short address
11 3 Address field contains a 64-bit extended address

If the destination address mode is either 2 or 3 (i.e. if the destination address is present), it always consists of a 16-bit PAN ID first, followed by either the 16-bit or 64-bit address as described by the mode.

• B i t [ 1 3 : 1 2 ] :

the "Frame Version" subfield specifies the version number corresponding to the frame. These register bits are reserved in IEEE 802.15.4-2003. This subfield shall be set to 0 to indicate a frame compatible with IEEE 802.15.4-2003 and 1 to indicate an IEEE 802.15.4-2006 frame. All other subfield values shall be reserved for future use. RX\_AACK register bit AACK\_FVN\_MODE (register 0x2E, CSMA\_SEED\_1) controls the behavior of frame acknowledgements. This register determines if, depending on the Frame Version Number, a frame is acknowledged or not. This is necessary for backward compatibility to IEEE 802.15.4-2003 and for future use. Even if frame version numbers 2 and 3 are reserved, it can be handled by the radio transceiver, for details refer to Section 7.2.7 "Register Description - Control Registers" on page 68. See IEEE 802.15.4-2006, section 7.2.3 for details on frame compatibility. Table 8-4. Frame Control Field - Frame Version Subfield

Frame Control Field Bit Assignments Description
Frame Version b_13 b_12	Value
00 0 Frames are compatible with IEEE		802.15.4 2003
01 1 Frames are compatible with IEEE		802.15.4-2006
10 2 Reserved
11 3 Reserved

- Bit [15:14]:

the "Source Addressing Mode" subfield, with similar meaning as "Destination Addressing Mode", see Table 8-3 on page 82. The subfields of the FCF (Bits 0-2, 3, 6, 10-15) affect the address filter logic of the AT86RF231 while operating in RX\_AACK operation, see Section 7.2.3 "RX\_AACK\_ON - Receive with Automatic ACK" on page 51.

8.1.2.3 Frame Compatibility between IEEE 802.15.4-2003 and IEEE 802.15.4-2006

All unsecured frames according to IEEE 802.15.4-2006 are compatible with unsecured frames compliant with IEEE 802.15.4-2003 with two exceptions: a coordinator realignment command frame with the "Channel Page" field present (see IEEE 802.15.4-2006, section 7.3.8) and any frame with a MAC Payload field larger than aMaxMACSafePayloadSize octets. Compatibility for secured frames is shown in Table 8-5 on page 83, which identifies the security operating modes for IEEE 802.15.4-2006. Table 8-5. Frame Control Field - Security and Frame Version

Frame Control Field Bit Assignments		Description
Security Enabled b_3	Frame Version b_13 b_12
0 00 No security. Frames are compatible betweenIEEE 802.15.4-2003 and IEEE 802.15.4-2006.
0 01 No security. Frames are not compatible betweenIEEE 802.15.4-2003 and IEEE 802.15.4-2006.
1 00 Secured frame formatted according to IEEE 802.15.4-2003.This frame type is not supported in IEEE 802.15.4-2006.
1 01 Secured frame formatted according to IEEE 802.15.4-2006

8.1.2.4 Sequence Number

The one-octet sequence number following the FCF identifies a particular frame, so that duplicated frame transmissions can be detected. While operating in RX\_AACK mode, the content of this field is copied from the frame to be acknowledged into the acknowledgment frame.

8.1.2.5 Addressing Fields

The addressing fields of the MPDU are used by the AT86RF231 for address matching indication. The destination address (if present) is always first, followed by the source address (if present). Each address field consists of the Intra PAN ID and a device address. If both addresses are present, and the "Intra PAN-ID compression" subfield in the FCF is set to one, the source Intra PAN ID is omitted. Note that in addition to these general rules, IEEE 802.15.4 further restricts the valid address combinations for the individual possible MAC frame types. For example, the situation where both addresses are omitted (source addressing mode = 0 and destination addressing mode = 0) is only allowed for acknowledgment frames. The address filter in the AT86RF231 has been designed to apply to IEEE 802.15.4 compliant frames. It can be configured to handle other frame formats and exceptions.

8.1.2.6 Auxiliary Security Header Field

The Auxiliary Security Header specifies information required for security processing and has a variable length. This field determines how the frame is actually protected (security level) and which keying material from the MAC security PIB is used (see IEEE 802.15.4-2006, section 7.6.1). This field shall be present only if the Security Enabled subfield b3, see Section 8.1.2.3 "Frame Compatibility between IEEE 802.15.4-2003 and IEEE 802.15.4-2006" on page 83, is set to one. For details of its structure, see IEEE 802.15.4-2006, section 7.6.2. Auxiliary security header.

8.1.2.7 MAC Service Data Unit (MSDU)

This is the actual MAC payload. It is usually structured according to the individual frame type. A description can be found in IEEE 802.15.4-2006, section 5.5.3.2.

8.1.2.8 MAC Footer (MFR) Fields

The MAC footer consists of a two-octet Frame Checksum (FCS), for details refer to Section 8.2 "Frame Check Sequence (FCS)" on page 85.

8.2 Frame Check Sequence (FCS)

The Frame Check Sequence (FCS) is characterized by: - Indicate bit errors, based on a cyclic redundancy check (CRC) of length 16 bit - Uses International Telecommunication Union (ITU) CRC polynomial • Automatically evaluated during reception - Can be automatically generated during transmission

8.2.1 Overview

The FCS is intended for use at the MAC layer to detect corrupted frames at a first level of filtering. It is computed by applying an ITU CRC polynomial to all transferred bytes following the length field (MHR and MSDU fields). The frame check sequence has a length of 16 bit and is located in the last two bytes of a frame (MAC footer, see Figure 8-2 on page 80). The AT86RF231 applies an FCS check on each received frame. The FCS check result is stored in register bit RX\_CRC\_VALID in register 0x06 (PHY\_RSSI). On transmit the radio transceiver generates and appends the FCS bytes during the frame transmission. This behavior can be disabled by setting register bit TX\_AUTO\_CRC\_ON = 0 (register 0x04, TRX\_CTRL\_1).

8.2.2 CRC Calculation

The CRC polynomial used in IEEE 802.15.4 networks is defined by: $$ G _ {1 6} x (\quad) ^ {1 6} x x ^ {1 2} x ^ {5} 1 + + + = $$ The FCS shall be calculated for transmission using the following algorithm: Let $$ M x (\quad) _ {0} x ^ {k} \stackrel {{\text { b}}} {{=}} b ^ {1} + \bar {b} _ {1} x ^ {k} ^ {2} + \bar {b} _ {2} x ^ {k} ^ {3} + \dots \quad b _ {k} + 2 x - b _ {k} + 1 ^ {+} - $$ be the polynomial representing the sequence of bits for which the checksum is to be computed. Multiply M(x) by x^16 , giving the polynomial $$ N (x) = M (x) \cdot x ^ {1 6} $$ Divide N(x) modulo 2 by the generator polynomial, G_16(x) , to obtain the remainder polynomial, $$ R x (\neq_ {0} x ^ {1 5} r + r _ {1} x ^ {1 4} + \dots + r _ {1 4} x \# _ {1 5} $$ The FCS field is given by the coefficients of the remainder polynomial, R(x) .

Example:

Considering a 5 octet ACK frame. The MHR field consists of 0100 0000 0000 0000 0101 0110. The leftmost bit ( b_0 ) is transmitted first in time. The FCS is in this case 0010 0111 1001 1110. The leftmost bit ( r_0 ) is transmitted first in time.

8.2.3 Automatic FCS generation

The automatic FCS generation is performed with register bit TX\_AUTO\_CRC\_ON = 1 (reset value). This allows the AT86RF231 to compute the FCS autonomously. For a frame with a frame length specified as N (3 ≤ N ≤ 127), the FCS is calculated on the first N-2 octets in the Frame Buffer, and the resulting FCS field is transmitted in place of the last two octets from the Frame Buffer. If the radio transceivers automatic FCS generation is enabled, the Frame Buffer write access can be stopped right after MAC payload. There is no need to write FCS dummy bytes. In RX\_AACK mode, when a received frame needs to be acknowledged, the FCS of the ACK frame is always automatically generated by the AT86RF231, independent of the TX\_AUTO\_CRC\_ON setting.

Example:

A frame transmission of length five with TX\_AUTO\_CRC\_ON set, is started with a Frame Buffer write access of five bytes (the last two bytes can be omitted). The first three bytes are used for FCS generation; the last two bytes are replaced by the internally calculated FCS.

8.2.4 Automatic FCS check

An automatic FCS check is applied on each received frame with a frame length N □ 2. Register bit RX\_CRC\_VALID (register 0x06, PHY\_RSSI) is set if the FCS of a received frame is valid. The register bit is updated when issuing interrupt IRQ\_3 (TRX\_END) and remains valid until the next TRX\_END interrupt caused by a new frame reception. In RX\_AACK mode, if FCS of the received frame is not valid, the radio transceiver rejects the frame and the TRX\_END interrupt is not issued. In TX\_ARET mode, the FCS and the sequence number of an ACK is automatically checked. If one of these is not correct, the ACK is not accepted.

8.2.5 Register Description

Register 0x04 (TRX\_CTRL\_1):

The TRX\_CTRL\_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit 76543210

+0x04	PA_EXT_EN	IRQ 2_EXT_EN	TX_AUTO_CRC_ON	RX_BL_CTRL	SPI_CMD_MODE		IRQ_MASK_MODE	IRQ_POLARITY	TRX_CTRL_1
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset Value	0 0 1 0 0 0 0 0

\- Bit 7 - PA\_EXT\_EN Refer to Section 11.5 "RX/TX Indicator" on page 147. \- Bit 6 - IRQ\_2\_EXT\_EN Refer to Section 11.6 "RX Frame Time Stamping" on page 150. \- Bit 5 - TX\_AUTO\_CRC\_ON Register bit TX\_AUTO\_CRC\_ON controls the automatic FCS generation for TX operations. The automatic FCS algorithm is performed autonomously by the radio transceiver if register bit TX\_AUTO\_CRC\_ON = 1. \- Bit 4 - RX\_BL\_CTRL Refer to Section 11.7 "Frame Buffer Empty Indicator" on page 152. \- Bit [3:2] - SPI\_CMD\_MODE Refer to Section 6.3 "Radio Transceiver Status information" on page 24. \- Bit 1 - IRQ\_MASK\_MODE Refer to Section 6.6 "Interrupt Logic" on page 29. \- Bit 0 - IRQ\_POLARITY Refer to Section 6.6 "Interrupt Logic" on page 29.

Register 0x06 (PHY\_RSSI):

The PHY\_RSSI register is a multi purpose register that indicates FCS validity, provides random numbers and shows the actual RSSI value. 

- Bit 7 - RX\_CRC\_VALID

Reading this register bit indicates whether the last received frame has a valid FCS or not. The register bit is updated when issuing interrupt IRQ\_3 (TRX\_END) and remains valid until the next TRX\_END interrupt is issued, caused by a new frame reception. Table 8-6. RX Frame FCS Check

Register Bit Value State Description
RX_CRC_VALID 0	_	FCS is not valid
	1 FCS is valid

- Bit [6:5] - RND\_VALUE

Refer to register description in Section 11.2.2 "Register Description" on page 136.

- Bit [4:0] - RSSI

Refer to register description in Section 8.3.4 "Register Description" on page 90.

8.3 Received Signal Strength Indicator (RSSI)

The Received Signal Strength Indicator is characterized by: - Minimum RSSI level is -91 dBm (RSSI\_BASE\_VAL) • Dynamic range is 81 dB • Minimum RSSI value is 0 • Maximum RSSI value is 28

8.3.1 Overview

The RSSI is a 5-bit value indicating the receive power in the selected channel, in steps of 3 dB. No attempt is made to distinguish IEEE 802.15.4 signals from others, only the received signal strength is evaluated. The RSSI provides the basis for an ED measurement, see Section 8.4 "Energy Detection (ED)" on page 91.

8.3.2 Reading RSSI

In Basic Operating Mode the RSSI value is valid in any receive state, and is updated every t_TR25 = 2 s to register 0x06 (PHY\_RSSI). It is not recommended to read the RSSI value when using the Extended Operating Mode. The automatically generated ED value should be used alternatively, see Section 8.4 "Energy Detection (ED)" on page 91.

8.3.3 Data Interpretation

The RSSI value is a 5-bit value indicating the receive power, in steps of 3 dB and with a range of 0 - 28. An RSSI value of 0 indicates a receiver RF input power of P_RF < -91 dBm. For an RSSI value in the range of 1 to 28, the RF input power can be calculated as follows: $$ P _ {R F} = R S S I \_ B A S E \_ V A L + 3 * (R S S I - 1) [ d B m ] $$ Figure 8-4. Mapping between RSSI Value and Received Input Power 

8.3.4 Register Description

Register 0x06 (PHY\_RSSI): 

- Bit 7 - RX\_CRC\_VALID

Refer to register description in Section 8.2.5 "Register Description" on page 87.

- Bit [6:5] - RND\_VALUE

Refer to register description in section Section 11.2.2 "Register Description" on page 136.

- Bit [4:0] - RSSI

The result of the automated RSSI measurement is stored in register bits RSSI. The value is updated every 2 s in receive states. The read value is a number between 0 and 28 indicating the received signal strength as a linear curve on a logarithmic input power scale (dBm) with a resolution of 3 dB. An RSSI value of 0 indicates an RF input power of P_RF < -91 dBm (see parameter 12.7.16), a value of 28 a power of P_RF 10 dBm (see parameter 12.7.18).

8.4 Energy Detection (ED)

The Energy Detection (ED) module is characterized by: • 85 unique energy levels defined - 1 dB resolution

8.4.1 Overview

The receiver ED measurement is used by the network layer as part of a channel selection algorithm. It is an estimation of the received signal power within the bandwidth of an IEEE 802.15.4 channel. No attempt is made to identify or decode signals on the channel. The ED value is calculated by averaging RSSI values over eight symbols (128 s). For High Data Rate Modes the automated ED measurement duration is reduced to 32 s, refer to Section 11.3 “High Data Rate Modes” on page 137. For manually initiated ED measurements in these modes the measurement period is still 128 s as long as the receiver is in RX\_ON state.

8.4.2 Measurement Description

There are two ways to initiate an ED measurement: - Manually, by writing an arbitrary value to register 0x07 (PHY\_ED\_LEVEL), or - Automatically, after detection of a valid SHR of an incoming frame. For manually initiated ED measurements the radio transceiver needs to be in one of the states RX\_ON or BUSY\_RX state. The end of the ED measurement is indicated by an interrupt IRQ\_4 (CCA\_ED\_DONE). An automated ED measurement is started if an SHR is detected. The end of the automated measurement is not signaled by an interrupt. The measurement result is stored after t_TR26 = 140 s (128 s measurement duration and processing delay) in register 0x07 (PHY\_ED\_LEVEL). Thus by using Basic Operating Mode, a valid ED value from the currently received frame is accessible 108 s after IRQ\_2 (RX\_START) and remains valid until a new RX\_START interrupt is generated by the next incoming frame or until another ED measurement is initiated. By using the Extended Operating Mode, it is recommended to mask IRQ\_2 (RX\_START), thus the interrupt cannot be used as timing reference. A successful frame reception is signalized by interrupt IRQ\_3 (TRX\_END). The minimum time span between a TRX\_END interrupt and a following SFD detection is t_TR27 = 96 s due to the length of the SHR. Including the ED measurement time, the ED value needs to be read within 224 s after the TRX\_END interrupt; otherwise, it could be overwritten by the result of the next measurement cycle. This is important for time critical applications or if interrupt IRQ\_2 (RX\_START) is not used to indicate the reception of a frame. Note, it is not recommended to manually initiate an ED measurement when using the Extended Operating Mode. The values of the register 0x07 (PHY\_ED\_LEVEL) are: Table 8-7. Register Bit PHY\_ED\_LEVEL Interpretation

PHY_ED_LEVEL Description
0xFF	Reset value
0x00.... 0x54 ED measurement result of the last ED measurement

8.4.3 Data Interpretation

The PHY\_ED\_LEVEL is an 8-bit register. The ED value of the AT86RF231 has a valid range from 0x00 to 0x54 with a resolution of 1 dB. All other values do not occur; a value of 0xFF indicates the reset value. A value of PHY\_ED\_LEVEL = 0 indicates that the measured energy is less than -91 dBm (see parameter 12.7.16 RSSI\_BASE\_VAL, Section 12.7 "Receiver Characteristics" on page 160). Due to environmental conditions (temperature, voltage, semiconductor parameters, etc.) the calculated ED value has a maximum tolerance of ±5 dB, this is to be considered as constant offset over the measurement range. An ED value of 0 indicates an RF input power of P_RF ≤ -91 dBm. For an ED value in the range of 0 to 84, the RF input power can be calculated as follows: $$ P _ {R F} = - 9 1 + E D [ d B m ] $$ Figure 8-5. Mapping between Received Input Power and ED Value 

8.4.4 Interrupt Handling

Interrupt IRQ\_4 (CCA\_ED\_DONE) is issued at the end of a manually initiated ED measurement. Note that an ED request should only be initiated in receive states. Otherwise the radio transceiver generates an IRQ\_4 (CCA\_ED\_DONE); however no ED measurement was performed.

8.4.5 Register Description

Register 0x07 (PHY\_ED\_LEVEL):

The PHY\_ED\_LEVEL register contains the result of an ED measurement. 

B i t 7 6 5 4 3 2 1 0 +0x07 ED_LEVEL[7:0] PHY_ED_LEVEL R e a d / W r i t e R R R R e s e t V a l u e 1 1 1

- Bit [7:0] - ED\_LEVEL

The minimum ED value (ED\_LEVEL = 0) indicates receiver power less than or equal to RSSI\_BASE\_VAL. The range is 84 dB with a resolution of 1 dB and an absolute accuracy of ±5 dB. A manual ED measurement can be initiated by a write access to the register. A value 0xFF signals that a measurement has never been started yet (reset value). The measurement duration is 8 symbol periods (128 s) for a data rate of 250 kb/s. For High Data Rate Modes the automated measurement duration is reduced to 32 s, refer to Section 11.3 “High Data Rate Modes” on page 137. For manually initiated ED measurements in these modes the measurement period is still 128 s as long as the receiver is in RX\_ON state. A value other than 0xFF indicates the result of the last ED measurement.

8.5 Clear Channel Assessment (CCA)

The main features of the Clear Channel Assessment (CCA) module are: - All 4 modes are available as defined by IEEE 802.15.4-2006 in section 6.9.9 - Adjustable threshold for energy detection algorithm

8.5.1 Overview

A CCA measurement is used to detect a clear channel. Four modes are specified by IEEE 802.15.4 - 2006: Table 8-8. CCA Mode Overview

CCA Mode Description
1	Energy above threshold.CCA shall report a busy medium upon detecting any energy above the ED threshold.
2 Carrier sense only.CCA shall report a busy medium only upon the detection of a signal with the modulation and spreading characteristics of an IEEE 802.15.4 compliant signal. The signal strength may be above or below the ED threshold.
0, 3 Carrier sense with energy above threshold.CCA shall report a busy medium using a logical combination of– Detection of a signal with the modulation and spreading characteristics of this standard and– Energy above the ED threshold.Where the logical operator may be configured as either OR (mode 0) or AND (mode 3).

8.5.2 Configuration and Request

The CCA modes are configurable via register 0x08 (PHY\_CC\_CCA). Using the Basic Operating Mode, a CCA request can be initiated manually by setting CCA\_REQUEST = 1 (register 0x08, PHY\_CC\_CCA), if the AT86RF231 is in any RX state. The current channel status (CCA\_STATUS) and the CCA completion status (CCA\_DONE) are accessible in register 0x01 (TRX\_STATUS). The CCA evaluation is done over eight symbol periods and the result is accessible t_TR28 = 140 s (128 s measurement duration and processing delay) after the request. The end of a manually initiated CCA measurement is indicated by an interrupt IRQ\_4 (CCA\_ED\_DONE). The sub-register CCA\_ED\_THRES of register 0x09 (CCA\_THRES) defines the received power threshold of the "Energy above threshold" algorithm. The threshold is calculated by RSSI\_BASE\_VAL + 2 \* CCA\_ED\_THRES [dBm]. Any received power above this level is interpreted as a busy channel. Note, it is not recommended to manually initiate a CCA measurement when using the Extended Operating Mode.

8.5.3 Data Interpretation

The current channel status (CCA\_STATUS) and the CCA completion status (CCA\_DONE) are accessible in register 0x01 (TRX\_STATUS). Note, register bits CCA\_DONE and CCA\_STATUS are cleared in response to a CCA\_REQUEST. The completion of a measurement cycle is indicated by CCA\_DONE = 1. If the radio transceiver detected no signal (idle channel) during the measurement cycle, the CCA\_STATUS bit is set to 1. When using the "energy above threshold" algorithm, any received power above CCA\_ED\_THRES level is interpreted as a busy channel. The "carrier sense" algorithm reports a busy channel when detecting an IEEE 802.15.4 signal above the RSSI\_BASE\_VAL (see parameter 12.7.16). The radio transceiver is also able to detect signals below this value, but the detection probability decreases with the signal power. It is almost zero at the radio transceivers sensitivity level (see parameter 12.7.1).

8.5.4 Interrupt Handling

Interrupt IRQ\_4 (CCA\_ED\_DONE) is issued at the end of a manually initiated CCA measurement.

Notes

- A CCA request should only be initiated in Basic Operating Mode receive states. Otherwise the radio transceiver generates an IRQ\_4 (CCA\_ED\_DONE) and sets the register bit CCA\_DONE = 1, even though no CCA measurement was performed. - Requesting a CCA measurement in BUSY\_RX state and during an ED measurement, an IRQ\_4 (CCA\_ED\_DONE) could be issued immediately after the request. If in this case register bit CCA\_DONE = 0, an additional interrupt CCA\_ED\_DONE is issued after finishing the CCA measurement and register bit CCA\_DONE is set to 1.

8.5.5 Measurement Time

The response time for a manually initiated CCA measurement depends on the receiver state. In RX\_ON state the CCA measurement is done over eight symbol periods and the result is accessible 140 s after the request (see above). In BUSY\_RX state the CCA measurement duration depends on the CCA Mode and the CCA request relative to the reception of an SHR. The end of the CCA measurement is indicated by an IRQ\_4 (CCA\_ED\_DONE). The variation of a CCA measurement period in BUSY\_RX state is described in Table 8-9 on page 95. Table 8-9. CCA Measurement Period and Access in BUSY\_RX state

CCA Mode	Request within ED measurement (1)	Request after ED measurement
1	Energy above threshold.
	CCA result is available after finishing automated ED measurement period.	CCA result is immediately available after request.
2 Carrier	sense only.
	CCA result is immediately available after request.

Table 8-9. CCA Measurement Period and Access in BUSY\_RX state

3 Carrier	sense with Energy above threshold (AND).
	CCA result is available after finishing automated ED measurement period.	CCA result is immediately available after request.
0 Carrier	sense with Energy above threshold (OR).
	CCA result is available after finishing automated ED measurement period	CCA result is immediately available after request.

Note: 1. After receiving the SHR an automated ED measurement is started with a length of 8 symbol periods (PSDU rate 250 kb/s), refer to Section 8.4 "Energy Detection (ED)" on page 91. This automated ED measurement must be finished to provide a result for the CCA measurement. Only one automated ED measurement per frame is performed. It is recommended to perform CCA measurements in RX\_ON state only. To avoid switching accidentally to BUSY\_RX state the SHR detection can be disabled by setting register bit RX\_PDT\_DIS (register 0x15, RX\_SYN), refer to Section 9.1 "Receiver (RX)" on page 101. The receiver remains in RX\_ON state to perform a CCA measurement until the register bit RX\_PDT\_DIS is set back to continue the frame reception. In this case the CCA measurement duration is 8 symbol periods.

8.5.6 Register Description

Register 0x01 (TRX\_STATUS):

Two register bits of register 0x01 (TRX\_STATUS) signal the status of the CCA measurement. Bit 76543210

+0x01	CCA_DONE	CCA_STATUS	Reserved	TRX_STATUS					TRX_STATUS
Read/Write	R	R	R	R	R	R	R	R
Reset Value	0 0 0 0 0 0 0

- Bit 7 - CCA\_DONE

This register indicates if a CCA request is completed. This is also indicated by an interrupt IRQ\_4 (CCA\_ED\_DONE). Note, register bit CCA\_DONE is cleared in response to a CCA\_REQUEST. Table 8-10. CCA Algorithm Status

Register Bit	Value	State Description
CCA_DONE	0	CCA calculation not finished
	1	CCA calculation finished

- Bit 6 - CCA\_STATUS

After a CCA request is completed the result of the CCA measurement is available in register bit CCA\_STATUS. Note, register bit CCA\_STATUS is cleared in response to a CCA\_REQUEST. Table 8-11. CCA Status Result

Register Bit	Value	State Description
CCA_STATUS	0	Channel indicated as busy
	1	Channel indicated as idle

- Bit 5 - Reserved

- Bit [4:0] - TRX\_STATUS

Refer to Section 7.1.5 “Register Description” on page 44 and Section 7.2.7 “Register Description - Control Registers” on page 68.

Register 0x08 (PHY\_CC\_CCA):

This register is provided to initiate and control a CCA measurement. 

Bit 7 6 5 4 3 2 1 0 +0x08 CCA_REQUEST CCA_MODE CHANNEL PHY_CC_CCA Read/Write W R/W R/W R/W R/W R/W R/W R/W Reset Value 0 0 1 0 1 0 1 1

- Bit 7 - CCA\_REQUEST

A manual CCA measurement is initiated with setting CCA\_REQUEST = 1. The end of the CCA measurement is indicated by interrupt IRQ\_4 (CCA\_ED\_DONE). Register bits CCA\_DONE and CCA\_STATUS (register 0x01, TRX\_STATUS) are updated after a CCA\_REQUEST. The register bit is automatically cleared after requesting a CCA measurement with CCA\_REQUEST = 1.

- Bit [6:5] - CCA\_MODE

The CCA mode can be selected using register bits CCA\_MODE. Table 8-12. CCA Status Result

Register Bit Value State Description

CCA_MODE 0 Mode 3a, Carrier sense OR energy above threshold

1 Mode 1, Energy above threshold

2 Mode 2, Carrier sense only

3 Mode 3b, Carrier sense AND energy above threshold

Note that IEEE 802.15.4-2006 CCA Mode 3 defines the logical combination of CCA Mode 1 and 2 with the logical operators AND or OR. This can be selected with: \- CCA\_MODE = 0 for logical operation OR, and \- CCA\_MODE = 3 for logical operation AND.

- Bit [4:0] - CHANNEL

Refer to Section 9.7 "Frequency Synthesizer (PLL)" on page 121.

Register 0x09 (CCA\_THRES):

This register sets the ED threshold level for CCA. 

Bit 7 6 5 4 3 +0x09 Reserved CCA_ED_THRES Read/Write R/W R/W R/W R/W R/W R/W R/W Reset Value 1 1 0 0 0 1 1 1

- Bit [7:5] - Reserved

- Bit [4:0] - CCA\_ED\_THRES

The CCA Mode 1 request indicates a busy channel if the measured received power is above RSSI\_BASE\_VAL + 2 \* CCA\_ED\_THRES [dBm]. CCA Modes 0 and 3 are logical related to this result.

8.6 Link Quality Indication (LQI)

According to IEEE 802.15.4, the LQI measurement is a characterization of the strength and/or quality of a received packet. The measurement may be implemented using receiver ED, a signal-to-noise ratio estimation, or a combination of these methods. The use of the LQI result by the network or application layers is not specified in this standard. LQI values shall be an integer ranging from 0x00 to 0xFF. The minimum and maximum LQI values (0x00 and 0xFF) should be associated with the lowest and highest quality compliant signals, respectively, and LQI values in between should be uniformly distributed between these two limits.

8.6.1 Overview

The LQI measurement of the AT86RF231 is implemented as a measure of the link quality which can be described with the packet error rate (PER) for this link. An LQI value can be associated with an expected packet error rate. The PER is the ratio of erroneous received frames to the total number of received frames. A PER of zero indicates no frame error, whereas at a PER of one no frame was received correctly. The radio transceiver uses correlation results of multiple symbols within a frame to determine the LQI value. This is done for each received frame. The minimum frame length for a valid LQI value is two octets PSDU. LQI values are integers ranging from 0 to 255. As an example, Figure 8-6 on page 99 shows the conditional packet error when receiving a certain LQI value. Figure 8-6. Conditional Packet Error Rate versus LQI  The values are taken from received frames of PSDU length of 20 octets on transmission channels with reasonable low multipath delay spreads. If the transmission channel characteristic has higher multipath delay spread than assumed in the example, the PER is slightly higher for a cer- tain LQI value. Since the packet error rate is a statistical value, the PER shown in Section 8-6 "Conditional Packet Error Rate versus LQI" on page 99 is based on a huge number of transactions. A reliable estimation of the packet error rate cannot be based on a single or a small number of LQI values.

8.6.2 Request an LQI Measurement

The LQI byte can be obtained after a frame has been received by the radio transceiver. One additional byte is automatically attached to the received frame containing the LQI value. This information can also be read via Frame Buffer read access, see Section 6.2.2 "Frame Buffer Access Mode" on page 20. The LQI byte can be read after IRQ\_3 (TRX\_END) interrupt.

8.6.3 Data Interpretation

According to IEEE 802.15.4 a low LQI value is associated with low signal strength and/or high signal distortions. Signal distortions are mainly caused by interference signals and/or multipath propagation. High LQI values indicate a sufficient high signal power and low signal distortions. Note, the received signal power as indicated by received signal strength indication (RSSI) value or energy detection (ED) value of the AT86RF231 do not characterize the signal quality and the ability to decode a signal. As an example, a received signal with an input power of about 6 dB above the receiver sensitivity likely results in a LQI value close to 255 for radio channels with very low signal distortions. For higher signal power the LQI value becomes independent of the actual signal strength. This is because the packet error rate for these scenarios tends towards zero and further increased signal strength, i.e. increasing the transmission power does not decrease the error rate any further. In this case RSSI or ED can be used to evaluate the signal strength and the link margin. ZigBee networks often require the identification of the "best" routing between two nodes. Both, the LQI and the RSSI/ED can be used for this, dependent on the optimization criteria. If a low packet error rate (corresponding to high throughput) is the optimization criteria then the LQI value should be taken into consideration. If a low transmission power or the link margin is the optimization criteria then the RSSI/ED value is also helpful. Combinations of LQI, RSSI and ED are possible for routing decisions. As a rule of thumb RSSI and ED values are useful to differentiate between links with high LQI values. Transmission links with low LQI values should be discarded for routing decisions even if the RSSI/ED values are high. This is because RSSI/ED does not say anything about the possibility to decode a signal. It is only an information about the received signal strength whereas the source can be an interferer.

9. Module Description

9.1 Receiver (RX)

9.1.1 Overview

The AT86RF231 receiver is split into an analog radio front end and a digital base band processor (RX BBP), see Figure 9-1 on page 101. Figure 9-1. Receiver Block Diagram 

graph LR
    RFP --> LNA_DPR/PF_Limiter_ADC
    RFN --> LNA_DPR/PF_Limiter_ADC
    LNA_DPR/PF_Limiter_ADC --> LO
    LO --> Add1["×"]
    Add1 --> Add2["×"]
    Add2 --> Add3["×"]
    Add3 --> Add4["Block"]
    Add4 --> Add5["Block"]
    Add5 --> Add6["Block"]
    Add6 --> Add7["Block"]
    Add7 --> Add8["Block"]
    Add8 --> Add9["Block"]
    Add9 --> Add10["Block"]
    Add10 --> Add11["Block"]
    Add11 --> Add12["Block"]
    Add12 --> Add13["Block"]
    Add13 --> Add14["Block"]
    Add14 --> Add15["Block"]
    Add15 --> Add16["Block"]
    Add16 --> Add17["Block"]
    Add17 --> Add18["Block"]
    Add18 --> Add19["Block"]
    Add19 --> Add20["Block"]
    Add20 --> Add21["Block"]
    Add21 --> Add22["Block"]
    Add22 --> Add23["Block"]
    Add23 --> Add24["Block"]
    Add24 --> Add25["Block"]
    Add25 --> Add26["Block"]
    Add26 --> Add27["Block"]
    Add27 --> Add28["Block"]
    Add28 --> Add29["Block"]
    Add29 --> Add30["Block"]
    Add30 --> Add31["Block"]
    Add31 --> Add32["Block"]
    Add32 --> Add33["Block"]
    Add33 --> Add34["Block"]
    Add34 --> Add35["Block"]
    Add35 --> Add36["Block"]
    Add36 --> Add37["Block"]
    Add37 --> Add38["Block"]
    Add38 --> Add39["Block"]
    Add39 --> Add40["Block"]
    Add40 --> Add41["Block"]
    Add41 --> Add42["Block"]
    Add42 --> Add43["Block"]
    Add43 --> Add44["Block"]
    Add44 --> Add45["Block"]
    Add45 --> Add46["Block"]
    Add46 --> Add47["Block"]
    Add47 --> Add48["Block"]
    Add48 --> Add49["Block"]
    Add49 --> Add50["Block"]
    Add50 --> Add51["Block"]
    Add51 --> Add52["Block"]
    Add52 --> Add53["Block"]
    Add53 --> Add54["Block"]
    Add54 --> Add55["Block"]
    Add55 --> Add56["Block"]
    Add56 --> Add57["Block"]
    Add57 --> Add58["Block"]
    Add58 --> Add59["Block"]
    Add59 --> Add60["Block"]
    Add60 --> Add61["Block"]
    Add61 --> Add62["Block"]
    Add62 --> Add63["Block"]
    Add63 --> Add64["Block"]
    Add64 --> Add65["Block"]
    Add65 --> Add66["Block"]
    Add66 --> Add67["Block"]
    Add67 --> Add68["Block"]
    Add68 --> Add69["Block"]
    Add69 --> Add70["Block"]
    Add70 --> Add71["Block"]
    Add71 --> Add72["Block"]
    Add72 --> Add73["Block"]
    Add73 --> Add74["Block"]
    Add74 --> Add75["Block"]
    Add75 --> PI_X_bar_1
    PI_X_bar_1 --> SPI_I_F
    PI_X_bar_1 --> μ_C_I_F

The differential RF signal is amplified by a low noise amplifier (LNA), filtered (PPF) and down converted to an intermediate frequency by a mixer. Channel selectivity is performed using an integrated band pass filter (BPF). A limiting amplifier (Limiter) provides sufficient gain to overcome the DC offset of the succeeding analog-to-digital converter (ADC) and generates a digital RSSI signal. The ADC output signal is sampled and processed further by the digital base band receiver (RX BBP). The RX BBP performs additional signal filtering and signal synchronization. The frequency offset of each frame is calculated by the synchronization unit and is used during the remaining receive process to correct the offset. The receiver is designed to handle frequency and symbol rate deviations up to ±120 ppm, caused by combined receiver and transmitter deviations. For details refer to Section 12.5 “General RF Specifications” on page 158 parameter 12.5.8. Finally the signal is demodulated and the data are stored in the Frame Buffer. In Basic Operating Mode, refer to Section 7.1 "Basic Operating Mode" on page 33, the reception of a frame is indicated by an interrupt IRQ\_2 (RX\_START). Accordingly its end is signalized by an interrupt IRQ\_3 (TRX\_END). Based on the quality of the received signal a link quality indicator (LQI) is calculated and appended to the frame, refer to Section 8.6 "Link Quality Indication (LQI)" on page 99. Additional signal processing is applied to the frame data to provide further status information like ED value (register 0x07, ED\_LEVEL) and FCS correctness (register 0x06, PHY\_RSSI). Beyond these features the Extended Operating Mode of the AT86RF231 supports address filtering and pending data indication. For details refer to Section 7.2 "Extended Operating Mode" on page 47.

9.1.2 Frame Receive Procedure

The frame receive procedure including the radio transceiver setup for reception and reading PSDU data from the Frame Buffer is described in Section 10.1 "Frame Receive Procedure" on page 126.

9.1.3 Configuration

In Basic Operating Mode the receiver is enabled by writing command RX\_ON to register bits TRX\_CMD (register 0x02, TRX\_STATE) in states TRX\_OFF or PLL\_ON. Similarly in Extended Operating Mode, the receiver is enabled for RX\_AACK operation from states TRX\_OFF or PLL\_ON by writing the command RX\_AACK\_ON. There is no additional configuration required to receive IEEE 802.15.4 compliant frames when using the Basic Operating Mode. However, the frame reception in the Extended Operating Mode requires further register configurations, for details refer to Section 7.2 "Extended Operating Mode" on page 47. The AT86RF231 receiver has an outstanding sensitivity performance of -101 dBm. At certain environmental conditions or for High Data Rate Modes, refer to Section 11.3 "High Data Rate Modes" on page 137, it may be useful to manually decrease this sensitivity. This is achieved by adjusting the synchronization header detector threshold using register bits RX\_PDT\_LEVEL (register 0x15, RX\_SYN). Received signals with an RSSI value below the threshold do not activate the demodulation process. Furthermore, it may be useful to protect a received frame against overwriting by subsequent received frames. A Dynamic Frame Buffer Protection is enabled with register bit RX\_SAFE\_MODE (register 0x0C, TRX\_CTRL\_2) set, see Section 11.8 "Dynamic Frame Buffer Protection" on page 154. The receiver remains in RX\_ON or RX\_AACK\_ON state until the whole frame is read by the microcontroller, indicated by /SEL = H during the SPI Frame Receive Mode. The Frame Buffer content is only protected if the FCS is valid. A Static Frame Buffer Protection is enabled with register bit RX\_PDT\_DIS (register 0x15, RX\_SYN) set. The receiver remains in RX\_ON or RX\_AACK\_ON state and no further SHR is detected until the register bit RX\_PDT\_DIS is set back.

9.1.4 Register Description

Register 0x15 (RX\_SYN):

This register controls the sensitivity threshold of the receiver. 

- Bit 7 - RX\_PDT\_DIS

RX\_PDT\_DIS = 1 prevents the reception of a frame even if the radio transceiver is in receive modes. An ongoing frame reception is not affected. This operation mode is independent of the setting of register bits RX\_PDT\_LEVEL.

- Bit [6:4] - Reserved

- Bit [3:0] - RX\_PDT\_LEVEL

These register bits desensitize the receiver such that frames with an RSSI level below the RX\_PDT\_LEVEL threshold level (if RX\_PDT\_LEVEL > 0) are not received. The threshold level can be calculated according to the following formula: $$ R X \_ T H R E S = R S S I \_ B A S E \_ V A L + 3 * (R X \_ P D T \_ L E V E L - 1), f o r R X \_ P D T \_ L E V E L > 0 $$ Examples for certain register settings are given in Table 9-1 on page 103 Table 9-1. Receiver Desensitization Threshold Level - RX\_PDT\_LEVEL

Value [Register]	RX Input Threshold Level	Value [dBm]
0x0	≤ RSSI_BASE_VAL (reset value)	RSSI value not considered
0x1	> RSSI_BASE_VAL + 0 * 3	> -90
...
0xE	> RSSI_BASE_VAL + 13 * 3	> -51
0xF	> RSSI_BASE_VAL + 14 * 3	> -48

If register bits RX\_PDT\_LEVEL > 0 the current consumption of the receiver in states RX\_ON and RX\_AACK\_ON is reduced by 500 A, refer to Section 12.8 “Current Consumption Specifications” on page 161 parameter 12.8.4. If register bits RX\_PDT\_LEVEL = 0 (reset value) all frames with a valid SHR and PHR are received, independently of their signal strength.

9.2 Transmitter (TX)

9.2.1 Overview

The AT86RF231 transmitter consists of a digital base band processor (TX BBP) and an analog radio front end, see Figure 9-2 on page 104. Figure 9-2. Transmitter Block Diagram 

graph LR
    A["RFN"] --> B["Buffer"]
    C["RFP"] --> B
    D["DIG3/4"] --> E["Ext. RF front-end and Output Power Control"]
    E --> F["PLL - TX Modulation PA"]
    F --> G["TX Data"]
    G --> H["Control, Registers"]
    H --> I["SPI"]
    I --> J["Frame Buffer"]
    J --> K["TX BBP"]
    K --> L["Analog Domain Digital Domain"]
    M["SPI I/F"] --> L
    N["μC I/F"] --> H

The TX BBP reads the frame data from the Frame Buffer and performs the bit-to-symbol and symbol-to-chip mapping as specified by IEEE 802.15.4 in section 6.5.2. The O-QPSK modulation signal is generated and fed into the analog radio front end. The fractional-N frequency synthesizer (PLL) converts the baseband transmit signal to the RF signal, which is amplified by the power amplifier (PA). The PA output is internally connected to bidirectional differential antenna pins (RFP, RFN), so that no external antenna switch is needed.

9.2.2 Frame Transmit Procedure

The frame transmit procedure including writing PSDU data in the Frame Buffer and initiating a transmission is described in Section 10.2 "Frame Transmit Procedure" on page 127, Frame Transmit Procedure.

9.2.3 Configuration

The maximum output power of the transmitter is typically +3 dBm. The output power can be configured via register bits TX\_PWR (register 0x05, PHY\_TX\_PWR). The output power of the transmitter can be controlled over a range of 20 dB. A transmission can be started from PLL\_ON or TX\_ARET\_ON state by a rising edge of pin SLP\_TR or by writing TX\_START command to register bits TRX\_CMD (register 0x02, TRX\_STATE).

9.2.4 TX Power Ramping

To optimize the output power spectral density (PSD), the PA buffer and PA are enabled sequentially. This is illustrated by a timing example using default settings, shown in Figure 9-3 on page 105. In this example the transmission is initiated with the rising edge of pin 11 (SLP\_TR). The radio transceiver state changes from PLL\_ON to BUSY\_TX. The modulation starts 16~ s after SLP\_TR. Figure 9-3. TX Power Ramping 

0 6 2 8 4 1 0 12 14 16 18 Length [µs] TRX_STATE PLL_ON BUSY_TX SLP_TR PA buffer PA_BUF_LT PA PA_LT Modulation 1 1 0 1 1 0 0 1 1

When using an external RF front-end (refer to Section 11.5 "RX/TX Indicator" on page 147) it may be required to adjust the startup time of the external PA relative to the internal building blocks to optimize the overall PSD. This can be achieved using register bits PA\_BUF\_LT and PA\_LT.

9.2.5 Register Description

Register 0x05 (PHY\_TX\_PWR):

This register controls the output power and the ramping of the transmitter. 

Bit 7 6 5 4 3 2 1 0 +0x05 PA_BUF_LT PA_LT TX_PWR PHY_TX_PWR Read/Write R/W R/W R/W R/W R/W R/W R/W Reset Value 1 1 0 0 0 0 0

- Bit [7:6] - PA\_BUF\_LT

These register bits control the enable lead time of the internal PA buffer relative to the enable time of the internal PA. This time is further used to derive a control signal for an external RF front-end to switch between receive and transmit, for details refer to Section 11.5. Table 9-2. PA Buffer Enable Time Relative to the PA

Register Bits	Value	PA Buffer Lead Time [μs]
PA_BUF_LT	0	0
	1	2
	2	4
	3	6

- Bit [5:4] - PA\_LT

These register bits control the enable lead time of the internal PA relative to the beginning of the transmitted frame. Table 9-3. PA Enable Time Relative to the Start of the Frame (SHR)

Register Bits Value PA Lead Time [μs]
PA_LT 0	-	2
	1	4
	2	6
	3	8

- Bit [3:0] - TX\_PWR

These register bits determine the TX output power of the AT86RF231. Table 9-4. AT86RF231 TX Output Power Setting

Register Bits Value TX Output Power [dBm]
TX_PWR 0x0	—	3.0
	0x1 2.8
	0x2 2.3
	0x3 1.8
	0x4 1.3
	0x5 0.7
	0x6 0.0
	0x7 -1
	0x8 -2
	0x9 -3
	0xA -4
	0xB -5
	0xC -7
	0xD -9
	0xE	-12
	0xF	-17

9.3 Frame Buffer

The AT86RF231 contains a 128 byte dual port SRAM. One port is connected to the SPI interface, the other to the internal transmitter and receiver modules. For data communication, both ports are independent and simultaneously accessible. The Frame Buffer uses the address space 0x00 to 0x7F for RX and TX operation of the radio transceiver and can keep one IEEE 802.15.4 RX or one TX frame of maximum length at a time. Frame Buffer access modes are described in Section 6.6.2 "Register Description" on page 30. Frame Buffer access conflicts are indicated by an under run interrupt IRQ\_6 (TRX\_UR). Note that this interrupt also occurs on the attempt to write frames longer than 127 octets to the Frame Buffer. In that case the content of the Frame Buffer cannot be guaranteed. Frame Buffer access is only possible if the digital voltage regulator is turned on. This is valid in all device states except in SLEEP state. An access in P\_ON state is possible if pin 17 (CLKM) provides the 1 MHz master clock.

9.3.1 Data Management

Data in Frame Buffer (received data or data to be transmitted) remains valid as long as: - No new frame or other data are written into the buffer over SPI - No new frame is received (in any BUSY\_RX state) - No state change into SLEEP state is made - No RESET took place By default there is no protection of the Frame Buffer against overwriting. Therefore, if a frame is received during Frame Buffer read access of a previously received frame, interrupt IRQ\_6 (TRX\_UR) is issued and the stored data might be overwritten. Even so, the old frame data can be read, if the SPI data rate is higher than the effective over air data rate. For a data rate of 250 kb/s a minimum SPI clock rate of 1 MHz is recommended. Finally the microcontroller should check the transferred frame data integrity by an FCS check. To protect the Frame Buffer content against being overwritten by newly incoming frames the radio transceiver state should be changed to PLL\_ON state after reception. This can be achieved by writing immediately the command PLL\_ON to register bits TRX\_CMD (register 0x02, TRX\_STATE) after receiving the frame, indicated by IRQ\_3 (TRX\_END). Alternatively Dynamic Frame Buffer Protection can be used to protect received frames against overwriting, for details refer to Section 11.8 "Dynamic Frame Buffer Protection" on page 154. Both procedures do not protect the Frame Buffer from overwriting by the microcontroller. In Extended Operating Mode during TX\_ARET operation, see Section 7.2.4 "TX\_ARET\_ON - Transmit with Automatic Retry and CSMA-CA Retry" on page 64, the radio transceiver switches to receive, if an acknowledgement of a previously transmitted frame was requested. During this period received frames are evaluated, but not stored in the Frame Buffer. This allows the radio transceiver to wait for an acknowledgement frame and retry the frame transmission without writing them again. A radio transceiver state change, except a transition to SLEEP state or a reset, does not affect the Frame Buffer contents. If the radio transceiver is forced into SLEEP, the Frame Buffer is powered off and the stored data gets lost.

9.3.2 User accessible Frame Content

The AT86RF231 supports an IEEE 802.15.4 compliant frame format as shown in Figure 9-4 on page 108. Figure 9-4. AT86RF231 Frame Structure 

0 Length [octets] 4 5 6 n + 3 n + 5 n + 6 Frame Preamble Sequence SFD PHR (1) Payload LQI FCS (2) Duration 4 octets / 128 µs 1 n octets / n • 32 µs (n <= 128) 1 Access SHR not accessible PHY generated TX: Frame Buffer content RX: Frame Buffer content

Notes: 1. Stored into Frame Buffer for TX operation 2. Stored into Frame Buffer during frame reception. A frame comprises two sections, the radio transceiver internally generated SHR field and the user accessible part stored in the Frame Buffer. The SHR contains the preamble and the SFD field. The variable frame section contains the PHR and the PSDU including the FCS, see Section 8.2 "Frame Check Sequence (FCS)" on page 85. The Frame Buffer content differs depending on the direction of the communication (receive or transmit). To access the data follow the procedures described in Section 6.2.2 “Frame Buffer Access Mode” on page 20. During frame reception, the payload and the link quality indicator (LQI) value of a successfully received frame are stored in the Frame Buffer. The radio transceiver appends the LQI value to the frame data after the last received octet. The frame length information is not stored in the Frame Buffer. When using the Frame Buffer access mode to read the Frame Buffer content, the frame length information is placed before the payload. If the SRAM read access is used to read an RX frame, the frame length field (PHR) cannot be accessed. The SHR (except the SFD used to generate the SHR) can generally not be read by the microcontroller. For frame transmission, the PHR and the PSDU needs to be stored in the Frame Buffer. The PHR byte is the first byte in the Frame Buffer and must be calculated based on the PHR and the PSDU. The maximum frame size supported by the radio transceiver is 128 bytes. If the TX\_AUTO\_CRC\_ON bit is set in register 0x05 (PHY\_TX\_PWR), the FCS field of the PSDU is replaced by the automatically calculated FCS during frame transmission. That's why there is no need to write the FCS field when using the automatic FCS generation. To manipulate individual bytes of the Frame Buffer a SRAM write access can be used instead. For non IEEE 802.15.4 compliant frames, the minimum frame length supported by the radio transceiver is one byte (Frame Length Field + 1 byte of data).

9.3.3 Interrupt Handling

Access conflicts may occur when reading and writing data simultaneously at the two independent ports of the Frame Buffer, TX/RX BBP and SPI. Both of these ports have their own address counter that points to the Frame Buffer's current address. Access violations occurs during concurrent Frame Buffer read or write accesses, when the SPI port's address counter value becomes higher than or equal to that of TX/RX BBP port. While receiving a frame, primarily the data needs to be stored in the Frame Buffer before reading it. This can be ensured by accessing the Frame Buffer 32 s after IRQ\_2 (RX\_START) at the earliest. When reading the frame data continuously the SPI data rate shall be lower than 250 kb/s to ensure no under run interrupt occurs. To avoid access conflicts and to simplify the Frame Buffer read access Frame Buffer Empty indication may be used, for details refer to Section 11.7 "Frame Buffer Empty Indicator" on page 152. While transmitting an access violation occurs during a Frame Buffer write access, when the SPI port's address counter value becomes less than or equal to that of TX BBP port. Both these access violations may cause data corruption and are indicated by IRQ\_6 (TRX\_UR) interrupt when using the Frame Buffer access mode. Access violations are not indicated when using the SRAM access mode.

Notes

- Interrupt IRQ\_6 (TRX\_UR) is valid 64 μs after IRQ\_2 (RX\_START). The occurrence of the interrupt can be disregarded when reading the first byte of the Frame Buffer between 32 μs and 64 μs after the RX\_START interrupt. - If a Frame Buffer read access is not finished until a new frame is received, a TRX\_UR interrupt occurs. Nevertheless the old frame data can be read, if the SPI data rate is higher than the effective PHY data rate. A minimum SPI clock rate of 1 MHz is recommended in this case. Finally, the microcontroller should check the integrity of the transferred frame data by calculating the FCS. - When writing data to the Frame Buffer during frame transmission, the SPI data rate shall be higher than the PHY data rate to ensure no under run interrupt. The first byte of the PSDU data must be available in the Frame Buffer before SFD transmission is complete, which takes 176~ s (16 s PA ramp up + 160 s SHR) from the rising edge of SLP\_TR pin (see Figure 7-2 on page 39).

9.4 Voltage Regulators (AVREG, DVREG)

The main features of the Voltage Regulator blocks are: - Bandgap stabilized 1.8V supply for analog and digital domain - Low dropout (LDO) voltage regulator - Configurable for usage of external voltage regulator

9.4.1 Overview

The internal voltage regulators supply a stabilized voltage to the AT86RF231. The AVREG provides the regulated 1.8V supply voltage for the analog section and the DVREG supplies the 1.8V supply voltage for the digital section. A simplified schematic of the internal voltage regulator is shown in Figure 9-5 on page 110. Figure 9-5. Simplified Schematic of AVREG/DVREG 

Bandgap voltage reference 1.25V (D)EVDD AVDD, DVDD

The voltage regulators require bypass capacitors for stable operation. The value of the bypass capacitors determine the settling time of the voltage regulators. The bypass capacitors shall be placed as close as possible to the pins and shall be connected to ground with the shortest possible traces.

9.4.2 Configuration

The voltage regulators can be configured by the register 0x10 (VREG\_CTRL). It is recommended to use the internal regulators, but it is also possible to supply the low voltage domains by an external voltage supply. For this configuration, the internal regulators need to be switched off by setting the register bits to the values AVREG\_EXT = 1 and DVREG\_EXT = 1. A regulated external supply voltage of 1.8V needs to be connected to the pins 13, 14 (DVDD) and pin 29 (AVDD). When turning on the external supply, ensure a sufficiently long stabilization time before interacting with the AT86RF231.

9.4.3 Data Interpretation

The status bits AVDD\_OK = 1 and DVDD\_OK = 1 of register 0x10 (VREG\_CTRL) indicate an enabled and stable internal supply voltage. Reading value 0 indicates a disabled or internal supply voltage not settled to the final value.

9.4.4 Register Description

Register 0x10 (VREG\_CTRL):

This register controls the use of the voltage regulators and indicates the status of these.

Bit 7	6		5		4		3		2		1
+0x10	AVREG_EXT	AVDD_OK	Reserved		DVREG_EXT	DVDD_OK	Reserved				VREG_CTRL
Read/Write	R/W	R	R/W	R/W	R/W	R	R/W	R/W	R/W
Reset Value	0	0		0		0		0		0

- Bit 7 - AVREG\_EXT

If set this register bit disables the internal analog voltage regulator to apply an external regulated 1.8V supply for the analog building blocks. Table 9-5. Regulated Voltage Supply Control for Analog Building Blocks

Register Bit	Value	Description
AVREG_EXT	0	Internal voltage regulator enabled, analog section
	1	Internal voltage regulator disabled, use external regulated 1.8V supply voltage for the analog section

• Bit 6 - AVDD\_OK

This register bit indicates if the internal 1.8V regulated voltage supply AVDD has settled. The bit is set to logic high, if AVREG\_EXT = 1. Table 9-6. Regulated Voltage Supply Control for Analog Building Blocks

Register Bit	Value Description
AVDD_OK	0	Analog voltage regulator disabled or supply voltage not stable
	1	Analog supply voltage has settled

- Bit [5:4] - Reserved

- Bit 3 - DVREG\_EXT

If set this register bit disables the internal digital voltage regulator to apply an external regulated 1.8V supply for the digital building blocks. Table 9-7. Regulated Voltage Supply Control for Digital Building Blocks

Register Bit	Value Description
DVREG_EXT	0	Internal voltage regulator enabled, digital section
	1	Internal voltage regulator disabled, use external regulated 1.8V supply voltage for the digital section

- Bit 2 - DVDD\_OK

This register bit indicates if the internal 1.8V regulated voltage supply DVDD has settled. The bit is set to logic high, if DVREG\_EXT = 1. Table 9-8. Regulated Voltage Supply Control for Digital Building Blocks

Register Bit Value Description
DVDD_OK 0	_	Digital voltage regulator disabled or supply voltage not stable
	1 Digital supply voltage has settled

Note

\- While the reset value of this bit is 0, any practical access to the register is only possible when DVREG is active. So this bit is normally always read out as 1. \- Bit [1:0] - Reserved

9.5 Battery Monitor (BATMON)

The main features of the battery monitor are: - Configurable voltage threshold range: 1.7V to 3.675V - Generates an interrupt when supply voltage drops below a threshold

9.5.1 Overview

The battery monitor (BATMON) detects and indicates a low supply voltage of the external supply voltage at pin 28 (EVDD). This is done by comparing the voltage on the external supply pin 28 (EVDD) with a configurable internal threshold voltage. A simplified schematic of the BATMON with the most important input and output signals is shown in Figure 9-6 on page 113. Figure 9-6. Simplified Schematic of BATMON 

graph LR
    A["BATMON_HR"] --> B["DAC"]
    C["BATMON_VTH"] --> B
    B --> D["Threshold Voltage"]
    D --> E["+"]
    E --> F["BATMON_OK"]
    G["1"] --> H["clear"]
    H --> I["D"]
    H --> J["Q"]
    I --> K["BATMON_IRQ"]
    J --> K
    L["For input-to-output mapping see control register 0x11 (BATMON)"]

9.5.2 Configuration

The BATMON can be configured using the register 0x11 (BATMON). Register subfield BATMON\_VTH sets the threshold voltage. It is configurable with a resolution of 75 mV in the upper voltage range (BATMON\_HR = 1) and with a resolution of 50 mV in the lower voltage range (BATMON\_HR = 0), for details refer to register 0x11 (BATMON).

9.5.3 Data Interpretation

The signal bit BATMON\_OK of register 0x11 (BATMON) monitors the current value of the battery voltage: - If BATMON\_OK = 0, the battery voltage is lower than the threshold voltage - If BATMON\_OK = 1, the battery voltage is higher than the threshold voltage After setting a new threshold, the value BATMON\_OK should be read out to verify the current supply voltage value. Note, the battery monitor is inactive during P\_ON and SLEEP states, see status register 0x01 (TRX\_STATUS).

9.5.4 Interrupt Handling

A supply voltage drop below the configured threshold value is indicated by an interrupt IRQ\_7 (BAT\_LOW), see Section 6.6 "Interrupt Logic" on page 29. Note that the interrupt is issued only if BATMON\_OK changes from 1 to 0. No interrupt is generated when: - The battery voltage is under the default 1.8V threshold at power up (BATMON\_OK was never 1), or - A new threshold is set, which is still above the current supply voltage (BATMON\_OK remains 0). When the battery voltage is close to the programmed threshold voltage, noise or temporary voltage drops may generate unwanted interrupts. To avoid this: - Disable the IRQ\_7 (BAT\_LOW) in register 0x0E (IRQ\_MASK) and treat the battery as empty, or - Set a lower threshold value.

9.5.5 Register Description

Register 0x11 (BATMON):

This register configures the battery monitor to compare the supply voltage at pin 28 (EVDD) to the threshold BATMON\_VTH. Additionally the supply voltage status at pin 28 (EVDD) is accessible by reading register bit BATMON\_OK according to the actual BATMON settings. Bit 76543210

+0x11	Reserved		BATMON_OK	BATMON_HR	BATMON_VTH				BATMON
Read/Write	R	R	R	R/W	R/W	R/W	R/W	R/W
Reset Value	0 0 0 0 0 1 0

\- Bit [7:6] - Reserved \- Bit 5 - BATMON\_OK The register bit BATMON\_OK indicates the level of the external supply voltage with respect to the programmed threshold BATMON\_VTH. Table 9-9. Battery Monitor Status

Register Bit	Value	Description
BATMON_OK	0	The battery voltage is below the threshold.
	1	The battery voltage is above the threshold.

\- Bit 4 - BATMON\_HR BATMON\_HR sets the range and resolution of the battery monitor. Table 9-10. Battery Monitor Range Selection

Register Bit	Value	Description
BATMON_HR	0	Enables the low range, see BATMON_VTH
	1	Enables the high range, see BATMON_VTH

- Bit [3:0] - BATMON\_VTH

The threshold values for the battery monitor are set by register bits BATMON\_VTH: Table 9-11. Battery Monitor Threshold Voltage

ValueBATMON_VTH[3:0]	Voltage [V]BATMON_HR = 1	Voltage [V]BATMON_HR = 0
0x0 2.550 1.70
0x1 2.625 1.75
0x2 2.700 1.80		—
0x3 2.775 1.85
0x4 2.850 1.90
0x5 2.925 1.95
0x6 3.000 2.00
0x7 3.075 2.05
0x8 3.150 2.10
0x9 3.225 2.15
0xA 3.300 2.20
0xB 3.375 2.25
0xC 3.450 2.30
0xD 3.525 2.35
0xE 3.600 2.40
0xF 3.675 2.45

9.6 Crystal Oscillator (XOSC)

The main crystal oscillator features are: • 16 MHz amplitude controlled crystal oscillator - 330 s typical settling time after leaving SLEEP state - Configurable trimming capacitance array - Configurable clock output (CLKM)

9.6.1 Overview

The crystal oscillator generates the reference frequency for the AT86RF231. All other internally generated frequencies of the radio transceiver are derived from this unique frequency. Therefore, the overall system performance is mainly determined by the accuracy of crystal reference frequency. The external components of the crystal oscillator should be selected carefully and the related board layout should be done with caution (see Section 5. "Application Circuits" on page 12). The register 0x12 (XOSC\_CTRL) provides access to the control signals of the oscillator. Two operating modes are supported. It is recommended to use the integrated oscillator setup as described in Figure 9-7 on page 116; nevertheless a reference frequency can be fed to the internal circuitry by using an external clock reference as shown in Figure 9-8 on page 117.

9.6.2 Integrated Oscillator Setup

Using the internal oscillator, the oscillation frequency depends on the load capacitance between the crystal pins XTAL1 and XTAL2. The total load capacitance C_L must be equal to the specified load capacitance of the crystal itself. It consists of the external capacitors CX and parasitic capacitances connected to the XTAL nodes. Figure 9-7 on page 116 shows all parasitic capacitances, such as PCB stray capacitances and the pin input capacitance, summarized to C_PAR . Figure 9-7. Simplified XOSC Schematic with External Components 

VDD EVDD CPAR CX CX 16MHz XTAL2XTAL1 AT86RF231 CTRIM XTAL_TRIM[3:0] CTRIM XTAL_TRIM[3:0] EVDD

Additional internal trimming capacitors C_TRIM are available. Any value in the range from 0 pF to 4.5 pF with a 0.3 pF resolution is selectable using XTAL\_TRIM of register 0x12 (XOSC\_CTRL). To calculate the total load capacitance, the following formula can be used: $$ C _ {L} = 0. 5 ^ {*} \left(C X + C _ {T R I M} + C _ {P A R}\right). $$ The trimming capacitors provide the possibility of reducing frequency deviations caused by production process variations or by external components tolerances. Note that the oscillation frequency can only be reduced by increasing the trimming capacitance. The frequency deviation caused by one step of C_TRIM decreases with increasing crystal load capacitor values. An amplitude control circuit is included to ensure stable operation under different operating conditions and for different crystal types. Enabling the crystal oscillator in P\_ON state and after leaving SLEEP state causes a slightly higher current during the amplitude build-up phase to guarantee a short start-up time. At stable operation, the current is reduced to the amount necessary for a robust operation. This also keeps the drive level of the crystal low. Generally, crystals with a higher load capacitance are less sensitive to parasitic pulling effects caused by external component variations or by variations of board and circuit parasitics. On the other hand, a larger crystal load capacitance results in a longer start-up time and a higher steady state current consumption.

9.6.3 External Reference Frequency Setup

When using an external reference frequency, the signal must be connected to pin 26 (XTAL1) as indicated in Figure 9-8 on page 117 and the register bits XTAL\_MODE (register 0x12, XOSC\_CTRL) need to be set to the external oscillator mode. The oscillation peak-to-peak amplitude shall be between 100 mV and 500 mV, the optimum range is between 400 mV and 500 mV. Pin 25 (XTAL2) should not be wired. Figure 9-8. Setup for Using an External Frequency Reference 

16 MHz XTAL1 XTAL2 PCB AT86RF231

9.6.4 Master Clock Signal Output (CLKM)

The generated reference clock signal can be fed to a microcontroller using pin 17 (CLKM). The internal 16 MHz raw clock can be divided by an internal prescaler. Thus, clock frequencies of 16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 250 kHz, or 62.5 kHz can be supplied by pin CLKM. The CLKM frequency, update scheme, and pin driver strength is configurable using register 0x03 (TRX\_CTRL\_0). There are two possibilities how a CLKM frequency change gets effective. If CLKM\_SHA\_SEL = 0 and/or CLKM\_CTRL = 0, changing the register bits CLKM\_CTRL immediately affects the CLKM clock rate. Otherwise (CLKM\_SHA\_SEL = 1 and CLKM\_CTRL > 0 before changing the register bits CLKM\_CTRL) the new clock rate is supplied when leaving the SLEEP state the next time. To reduce power consumption and spurious emissions, it is recommended to turn off the CLKM clock when not in use or to reduce its driver strength to a minimum, refer to Section 1.3 "Digital Pins" on page 7.

Note:

- During reset procedure, see Section 7.1.2.8 "RESET State" on page 37, register bits CLKM\_CTRL are shadowed. Although the clock setting of CLKM remains after reset, a read access to register bits CLKM\_CTRL delivers the reset value 1. For that reason it is recommended to write the previous configuration (before reset) to register bits CLKM\_CTRL (after reset) to align the radio transceiver behavior and register configuration. Otherwise the CLKM clock rate is set back to the reset value (1 MHz) after the next SLEEP cycle. - For example, if the CLKM clock rate is configured to 16 MHz the CLKM clock rate remains at 16 MHz after a reset, however the register bits CLKM\_CTRL are set back to 1. Since CLKM\_SHA\_SEL reset value is 1, the CLKM clock rate changes to 1 MHz after the next SLEEP cycle if the CLKM\_CTRL setting is not updated after reset.

9.6.5 Register Description

Register 0x03 (TRX\_CTRL\_0): 

Bit 7 6 5 4 3 2 1 +0x03 PAD_IO PAD_IO_CLKM CLKM_SHA_SIL CLKM_CTRL TRX_CTRL_0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 1 1 0 0 1

The TRX\_CTRL\_0 register controls the drive current of the digital output pads and the CLKM clock rate. It is recommended to use the lowest value for the drive current to reduce the current consumption and the emission of signal harmonics. \- Bit [7:6] - PAD\_IO Refer to Section 1.3 "Digital Pins" on page 7. \- Bit [5:6] - PAD\_IO\_CLKM These register bits set the output driver current of pin CLKM. It is recommended to reduce the current capability to PAD\_IO\_CLKM = 0 (2 mA) if possible. This reduces power consumption and spurious emissions. Table 9-12. CLKM Driver Strength

Register Bit	Value	Description
PAD_IO_CLKM	0	2 mA
	1	4 mA
	2	6 mA
	3	8 mA

\- Bit 3 - CLKM\_SHA\_SEL Register bit CLKM\_SHA\_SEL defines if a new clock rate, defined by CLKM\_CTRL, is set immediately or after the next SLEEP cycle. Table 9-13. CLKM Clock Rate Update Scheme

Register Bit	Value	Description
CLKM_SHA_SEL	0	CLKM clock rate change appears immediately
	1	CLKM clock rate change appears after SLEEP cycle

\- Bit [2:0] - CLKM\_CTRL These register bits set clock rate of pin 17 (CLKM). Table 9-14. Clock Rate Setting at pin CLKM

Register Bit Value Description
CLKM_CTRL 0 No clock at	pin 17 (CLKM), pin set to logic low
	1 1 MHz
	2 2 M H z
	3 4 M H z
	4 8 M H z
	5 1 6 M H z
	6 2 5 0 k H z
	7 62.5 kHz (IEEE 802.15.4 symbol rate)

Register 0x12 (XOSC\_CTRL):

The register XOSC\_CTRL controls the operation of the crystal oscillator.  \- Bit [7:4] - XTAL\_MODE These register bits set the operating mode of the crystal oscillator. For normal operation the default value is set to XTAL\_MODE = 0xF after reset. Using an external clock source it is recommended to set XTAL\_MODE = 0x4. Table 9-15. Crystal Oscillator Operating Mode

Register Bit	Value	Description
XTAL_MODE	0x4	Internal crystal oscillator disabled, use external reference frequency
	0xF	Internal crystal oscillator enabledXOSC voltage regulator enabled

- Bit [3:0] - XTAL\_TRIM

The register bits XTAL\_TRIM control two internal capacitance arrays connected to pins XTAL1 and XTAL2. A capacitance value in the range from 0 pF to 4.5 pF is selectable with a resolution of 0.3 pF. Table 9-16. Crystal Oscillator Trimming Capacitors

Register Bit Value	Description
XTAL_TRIM 0x0	____	0.0 pF, trimming capacitors disconnected
	0x1 0.3 pF trimming capacitor switched on
	...
	0xF 4.5 pF trimming capacitor switched on

9.7 Frequency Synthesizer (PLL)

The main PLL features are: - Generate RX/TX frequencies for all IEEE 802.15.4 - 2.4 GHz channels - Autonomous calibration loops for stable operation within the operating range - Two PLL-interrupts for status indication - Fast PLL settling to support frequency hopping

9.7.1 Overview

The PLL generates the RF frequencies for the AT86RF231. During receive operation the frequency synthesizer works as a local oscillator on the radio transceiver receive frequency, during transmit operation the voltage-controlled oscillator (VCO) is directly modulated to generate the RF transmit signal. The frequency synthesizer is implemented as a fractional-N PLL. Two calibration loops ensure correct PLL functionality within the specified operating limits.

9.7.2 RF Channel Selection

The PLL is designed to support 16 channels in the 2.4 GHz ISM band with a channel spacing of 5 MHz according to IEEE 802.15.4. The center frequency of these channels is defined as follows: $$ F _ {c} = 2 4 0 5 + 5 (k - 1 1) \text { in } [ \mathrm{MHz} ], \text { for } k = 1 1, 1 2,..., 2 6 $$ where k is the channel number. The channel k is selected by register bits CHANNEL (register 0x08, PHY\_CC\_CA).

9.7.3 Frequency Agility

When the PLL is enabled during state transition from TRX\_OFF to PLL\_ON, the settling time is typically t_TR4 = 110 s , including settling of the analog voltage regulator (AVREG) and PLL self calibration, refer to Table 7-2 on page 43 and Figure 13-13 on page 168. A lock of the PLL is indicated with an interrupt IRQ\_0 (PLL\_LOCK). Switching between 2.4 GHz ISM band channels in PLL\_ON or RX\_ON states is typically done within t_TR20 = 11 s . This makes the radio transceiver highly suitable for frequency hopping applications. When starting the transmit procedure the PLL frequency is changed to the transmit frequency within a period of t_TR23 = 16 s before starting the transmission. After the transmission the PLL settles back to the receive frequency within a period of t_TR24 = 32 s . This frequency step does not generate an interrupt IRQ\_0 (PLL\_LOCK) or IRQ\_1 (PLL\_UNLOCK) within these periods.

9.7.4 Calibration Loops

Due to variation of temperature, supply voltage and part-to-part variations of the radio transceiver the VCO characteristics may vary. To ensure a stable operation, two automated control loops are implemented, center frequency (CF) tuning and delay cell (DCU) calibration. Both calibration loops are initiated automatically when the PLL is enabled during state transition from TRX\_OFF to PLL\_ON state. Additionally, center frequency calibration is initiated when the PLL changes to a different channel center frequency. If the PLL operates for a long time on the same channel, e.g. more than 5 min, or the operating temperature changes significantly, it is recommended to initiate the calibration loops manually. Both calibration loops can be initiated manually by setting PLL\_CF\_START = 1 (register 0x1A, PLL\_CF) and register bit PLL\_DCU\_START = 1 (register 0x1B, PLL\_DCU). To start the calibration the device must be in PLL\_ON or RX\_ON state. The completion of the center frequency tuning is indicated by a PLL\_LOCK interrupt. Both calibration loops may be run simultaneously.

9.7.5 Interrupt Handling

Two different interrupts indicate the PLL status (refer to register 0x0F). IRQ\_0 (PLL\_LOCK) indicates that the PLL has locked. IRQ\_1 (PLL\_UNLOCK) interrupt indicates an unexpected unlock condition. A PLL\_LOCK interrupt clears any preceding PLL\_UNLOCK interrupt automatically and vice versa. A PLL\_LOCK interrupt is supposed to occur in the following situations: - State change from TRX\_OFF to PLL\_ON / RX\_ON / TX\_ARET\_ON / RX\_AACK\_ON - Channel change in states PLL\_ON / RX\_ON / TX\_ARET\_ON / RX\_AACK\_ON Any other occurrences of PLL interrupts indicate erroneous behavior and require checking of the actual device status. The state transition from BUSY\_TX to PLL\_ON after successful transmission does not generate an IRQ\_0 (PLL\_LOCK) within the settling period.

9.7.6 Register Description

Register 0x08 (PHY\_CC\_CCA): This register sets the IEEE 802.15.4 - 2.4 GHz channel number Bit 76543210

+0x08 CCA REQUEST CCA_MODE CHANNEL PHY_CC_CCA
Read/Write	W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset Value	0 0 1 0 1 0 1 1

\- Bit 7 - CCA\_REQUEST Refer to Section 8.5 "Clear Channel Assessment (CCA)" on page 94. \- Bit [6:5] - CCA\_MODE Refer to Section 8.5 "Clear Channel Assessment (CCA)" on page 94. \- Bit [4:0] - CHANNEL The register bits CHANNEL define the RX/TX channel. The channel assignment is according to IEEE 802.15.4. Table 9-17. Channel Assignment for IEEE 802.15.4 - 2.4 GHz Band

Register Bit Value Channel Number k Center Frequency [MHz]
CHANNEL 0x0B	____	11 2405
	0x0C 12 2410
	0x0D 13 2415
	0x0E 14 2420
	0x0F 15 2425
	0x10 16 2430
	0x11 17 2435
	0x12 18 2440
	0x13 19 2445
	0x14 20 2450
	0x15 21 2455
	0x16 22 2460
	0x17 23 2465
	0x18 24 2470
	0x19 25 2475
	0x1A 26 2480

Register 0x1A (PLL\_CF):

This register controls the operation of the center frequency calibration loop. 

- Bit 7 - PLL\_CF\_START

PLL\_CF\_START = 1 initiates the center frequency calibration. The calibration cycle has finished after t_TR21 = 35 s (typ.). The register bit is cleared immediately after finishing the calibration.

- Bit [6:0] - Reserved

Register 0x1B (PLL\_DCU):

This register controls the operation of the delay cell calibration loop. 

- Bit 7 - PLL\_DCU\_START

PLL\_DCU\_START = 1 initiates the delay cell calibration. The calibration cycle has finished after at most t_TR22 = 6 s , the register bit is set to 0. The register bit is cleared immediately after finishing the calibration. \- Bit [6:0] - Reserved

9.8 Automatic Filter Tuning (FTN)

9.8.1 Overview

The FTN is incorporated to compensate device tolerances for temperature, supply voltage variations as well as part-to-part variations of the radio transceiver. The filter-tuning result is used to correct the analog baseband filter transfer function and the PLL loop-filter time constant, refer to Section 4. "General Circuit Description" on page 10. An FTN calibration cycle is initiated automatically when entering the TRX\_OFF state from the SLEEP, RESET or P\_ON states. Although receiver and transmitter are very robust against these variations, it is recommended to initiate the FTN manually if the radio transceiver does not use the SLEEP state. If necessary, a calibration cycle is to be initiated in states TRX\_OFF, PLL\_ON or any receive state. This applies in particular for the High Data Rate Modes with a much higher sensitivity against BPF transfer function variations. The recommended calibration interval is 5 min or less.

9.8.2 Register Description

Register 0x18 (FTN\_CTRL):

This register controls the operation of the filter tuning network calibration loop. 

Bit 7 6 5 4 3 2 1 0 +0x18 FTN_START Reserved FTN_CTRL Read/Write R/W R/W R/W R/W R/W R/W R/W Reset Value 0 1 0 1 1 0 0 0

\- Bit 7 - FTN\_START FTN\_START = 1 initiates the filter tuning network calibration. When the calibration cycle has finished after at most 25 s the register bit is automatically reset to 0. \- Bit [6:0] - Reserved

10. Radio Transceiver Usage

This section describes basic procedures to receive and transmit frames using the AT86RF231. For a detailed programming description refer to reference [6].

10.1 Frame Receive Procedure

A frame reception comprises of two actions: The PHY listens for, receives and demodulates the frame to the Frame Buffer and signalizes the reception to the microcontroller. After or while that the microcontroller read the available frame data from the Frame Buffer via the SPI interface. While in state RX\_ON or RX\_AACK\_ON the radio transceiver searches for incoming frames on the selected channel. Assuming the appropriate interrupts are enabled, a detection of an IEEE 802.15.4 compliant frame is indicated by interrupt IRQ\_2 (RX\_START) first. The frame reception is completed when issuing interrupt IRQ\_3 (TRX\_END). Different Frame Buffer read access scenarios are recommended for: • Non-time critical applications read access starts after IRQ\_3 (TRX\_END) • Time-critical applications read access starts after IRQ\_2 (RX\_START) Waiting for IRQ\_3 (TRX\_END) interrupt before starting a Frame Buffer read access is recommended for operations considered to be none time critical. Figure 10-1 on page 126 illustrates the frame receive procedure using IRQ\_3 (TRX\_END). Figure 10-1. Transactions between AT86RF231 and Microcontroller during Receive 

graph LR
    A["IRQ issued (IRQ_2)"] --> B["Read IRQ status, pin 24 (IRQ) deasserted"]
    B --> C["IRQ issued (IRQ_3)"]
    C --> D["Read IRQ status, pin 24 (IRQ) deasserted"]
    D --> E["Read frame data (Frame Buffer access)"]
    style A fill:#f9f,stroke:#333
    style B fill:#f9f,stroke:#333
    style C fill:#f9f,stroke:#333
    style D fill:#f9f,stroke:#333
    style E fill:#f9f,stroke:#333

Critical protocol timing could require starting the Frame Buffer read access after interrupt IRQ\_2 (RX\_START). The first byte of the frame data can be read 32 s after the IRQ\_2 (RX\_START) interrupt. The microcontroller must ensure to read slower than the frame is received. Otherwise a Frame Buffer under run occurs, IRQ\_6 (TRX\_UR) is issued, and the frame data may be not valid. To avoid this, the Frame Buffer read access can be controlled by using a Frame Buffer Empty indicator, refer to Section 11.7 "Frame Buffer Empty Indicator" on page 152.

10.2 Frame Transmit Procedure

A frame transmission comprises of two actions, a Frame Buffer write access and the transmission of the Frame Buffer content. Both actions can be run in parallel if required by critical protocol timing. Figure 10-2 on page 127 illustrates the frame transmit procedure, when writing and transmitting the frame consecutively. After a Frame Buffer write access, the frame transmission is initiated by asserting pin 11 (SLP\_TR) or writing command TX\_START to register 0x02 (TRX\_STATE), while the radio transceiver is in state PLL\_ON or TX\_ARET\_ON. The completion of the transaction is indicated by interrupt IRQ\_3 (TRX\_END). Figure 10-2. Transaction between AT86RF231 and Microcontroller during Transmit 

graph TD
    A["AT86RF231"] --> B["Write frame data (Frame Buffer access)"]
    B --> C["Write TRX_CMD = TX_START, or assert pin 11 (SLP_TR)"]
    C --> D["IRQ_3 (TRX_END) issued"]
    D --> E["Read IRQ_STATUS register, pin 24 (IRQ) deasserted"]
    E --> F["Microcontroller"]

Alternatively a frame transmission can be started first, followed by the Frame Buffer write access (PSDU data); refer to Figure 10-3 on page 127. This is applicable for time critical applications. Initiating a transmission, either by asserting pin 11 (SLP\_TR) or command TX\_START to register bits TRX\_CMD (register 0x02, TRX\_STATE), the radio transceiver starts transmitting the SHR, which is internally generated. This first phase requires 16 s for PLL settling and 160 s for SHR transmission. The PHR must be available in the Frame Buffer before this time elapses. Furthermore the SPI data rate must be higher than the PHY data rate selected by register bits OQPSK\_DATA\_RATE (register 0x0C, TRX\_CTRL\_2) to ensure that no Frame Buffer under run occurs, indicated by IRQ\_6 (TRX\_UR), refer to Section 11.3 “High Data Rate Modes” on page 137. Figure 10-3. Time Optimized Frame Transmit Procedure 

graph TD
    A["Write TRX_CMD = TX_START, or assert pin 11 (SLP_TR)"] --> B["Write frame data (Frame Buffer access)"]
    B --> C["IRQ_3 (TRX_END) issued"]
    C --> D["Read IRQ_STATUS register, pin 24 (IRQ) deasserted"]
    D --> E["Microcontroller"]

11. AT86RF231 Extended Feature Set

11.1 Security Module (AES)

The security module (AES) is characterized by: - Hardware accelerated encryption and decryption - Compatible with AES-128 standard (128-bit key and data block size) - ECB (encryption/decryption) mode and CBC (encryption) mode support - Stand-alone operation, independent of other blocks

11.1.1 Overview

The security module is based on an AES-128 core according to FIPS197 standard, refer to [5] . The security module works independent of other building blocks of the AT86RF231, encryption and decryption can be performed in parallel to a frame transmission or reception. Controlling the security block is implemented as an SRAM access to address space 0x82 to 0x94. A Fast SRAM access mode allows simultaneously writing new data and reading data from previously processed data within the same SPI transfer. This access procedure is used to reduce the turnaround time for ECB mode, see Section 11.1.5 "Data Transfer - Fast SRAM Access" on page 132. In addition, the security module contains another 128-bit register to store the initial key used for security operations. This initial key is not modified by the security module.

11.1.2 Security Module Preparation

The use of the security module requires a configuration of the security engine before starting a security operation. The following steps are required: Table 11-1. AES Engine Configuration Steps

Step	Description Description	Section
1	Key Setup Write encryption or decryption key to SRAM Section 11.1.3
2	AES Mode Select AES	mode: ECB or CBCSelect encryption or decryption	Section 11.1.4.1Section 11.1.4.2
3	Write Data	Write plaintext or cipher text to SRAM	Section 11.1.5
4	Start Operation Start AES operation
5	Read Data	Read cipher text or plaintext from SRAM	Section 11.1.5

Before starting any security operation a key must be written to the security engine, refer to Section 11.1.3 "Security Key Setup" on page 129. The key set up requires the configuration of the AES engine KEY mode using register bits AES\_MODE (SRAM address 0x83, AES\_CTRL). The following step selects the AES mode, either electronic code book (ECB) or cipher block chaining (CBC). These modes are explained more in detail in sections Section 11.1.4 "Security Operation Modes" on page 129. Further, encryption or decryption must be selected with register bit AES\_DIR (SRAM address 0x83, AES\_CTRL). As next the 128-bit plain text or ciphertext data has to be provided to the AES hardware engine. The data uses the SRAM address range 0x84 - 0x93. The encryption or decryption is initiated with register bit AES\_REQUEST = 1 (SRAM address 0x83, AES\_CTRL or the mirrored version with SRAM address 0x94, AES\_CTRL\_MIRROR). The AES module control registers are only accessible using SRAM read and write accesses on address space 0x82 to 0x94. A configuration of the AES mode, providing the data and the start of the operation can be combined within one SRAM access.

Notes

- No additional register access is required to operate the security block. - Using AES in TRX\_OFF state requires an activated clock at pin 17 (CLKM), i.e. register bits CLKM\_CTRL!= 0. For further details refer to Section 9.6.4 "Master Clock Signal Output (CLKM)" on page 117. - Access to the security block is not possible while the radio transceiver is in state SLEEP. - All configurations of the security module, the SRAM content and keys are reset during SLEEP or RESET states.

11.1.3 Security Key Setup

The setup of the key is prepared by setting register bits AES\_MODE = 0x1 (SRAM address 0x83, AES\_CTRL). Afterwards the 128 bit key must be written to SRAM addresses 0x84 through 0x93 (registers AES\_KEY). It is recommended to combine the setting of control register 0x83 (AES\_CTRL) and the 128 bit key transfer using only one SRAM access starting from address 0x83. The address space for the 128-bit key and 128-bit data is identical from programming point of view. However, both use different pages which are selected by register bit AES\_MODE before storing the data. A read access to registers AES\_KEY (0x84 - 0x93) returns the last round key of the preceding security operation. After an ECB encryption operation, this is the key that is required for the corresponding ECB decryption operation. However, the initial AES key, written to the security module in advance of an AES run, see step 1 in Table 11-1 on page 128, is not modified during an AES operation. This initial key is used for the next AES run even it cannot be read from AES\_KEY.

Note

\- ECB decryption is not required for IEEE 802.15.4 or ZigBee security processing. The AT86RF231 provides this functionality as an additional feature.

11.1.4 Security Operation Modes

11.1.4.1 Electronic Code Book (ECB)

ECB is the basic operating mode of the security module. After setting up the initial AES key, register bits AES\_MODE = 0 (SRAM address 0x83, AES\_CTRL) sets up ECB mode. Register bit AES\_DIR (SRAM address 0x83, AES\_CTRL) selects the direction, either encryption or decryption. The data to be processed has to be written to SRAM addresses 0x84 through 0x93 (registers AES\_STATE). An example for a programming sequence is shown in Figure 11-1 on page 130. This example assumes a suitable key has been loaded before. A security operation can be started within one SRAM access by appending the start command AES\_REQUEST = 1 (register 0x94, AES\_CTRL\_MIRROR) to the SPI sequence. Register AES\_CTRL\_MIRROR is a mirrored version of register 0x83 (AES\_CTRL). Figure 11-1. ECB Programming SPI Sequence - Encryption 

byte 1 (address)byte 0 (cmd.) byte 2 (AES cmd) byte 3 (data) 0 1 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 data 0[7:0]


byte 18 (data) byte 19 (AES cmd) data_15[7:0] 1 0 0 0 0 0 0 AES startECB, encrypt

Summarizing, the following steps are required to perform a security operation using only one SPI access: 1. Configure SPI Access a) SRAM Write, refer to Section 6.2.3 2. Configure AES Operation b) Start Address 0x83 3. Write 128-bit data block Address 0x83: select ECB mode, direction 4. Start AES Operation Addresses 0x84 - 0x93: either plain or ciphertext Addresses 0x94: start AES operation, ECB mode This sequence is recommended because the security operation is configured and started within one SPI transaction. The ECB encryption operation is illustrated in Figure 11-2 on page 130. Figure 11-3 on page 130 shows the ECB decryption mode, which is supported in a similar way. Figure 11-2. ECB Mode - Encryption 

graph TD
    A["Plaintext"] --> B["Block Cipher Encryption"]
    C["Encryption Key"] --> B
    B --> D["Ciphertext"]


graph TD
    A["Plaintext"] --> B["Block Cipher Encryption"]
    C["Encryption Key"] --> B
    B --> D["Ciphertext"]

Figure 11-3. ECB Mode - Decryption 

graph TD
    A["Ciphertext"] --> B["Block Cipher Decryption"]
    C["Decryption Key"] --> B
    B --> D["Plaintext"]


graph TD
    A["Ciphertext"] --> B["Block Cipher Decryption"]
    B --> C["Plaintext"]
    D["Decryption Key"] --> B

When decrypting, due to the nature of AES algorithm, the initial key to be used is not the same as the one used for encryption, but rather the last round key instead. This last round key is the content of the key address space stored after running one full encryption cycle, and must be saved for decryption. If the decryption key has not been saved, it has to be recomputed by first running a dummy encryption (of an arbitrary plaintext) using the original encryption key, then fetching the resulting round key from the key memory, and writing it back into the key memory as the decryption key. ECB decryption is not used by either IEEE 802.15.4 or ZigBee frame security. Both of these standards do not directly encrypt the payload, but rather a nonce instead, and protect the payload by applying an XOR operation between the resulting (AES-) cipher text and the original payload. As the nonce is the same for encryption and decryption only ECB encryption is required. Decryption is performed by XORing the received cipher text with its own encryption result respectively, which results in the original plaintext payload upon success.

11.1.4.2 Cipher Block Chaining (CBC)

In CBC mode, the result of a previous AES operation is XORed with the new incoming vector, forming the new plaintext to encrypt, see Figure 11-4 on page 131. This mode is used for the computation of a cryptographic checksum (message integrity code, MIC). Figure 11-4. CBC Mode - Encryption 

graph TD
    A["Plaintext Initialization Vector (IV)"] --> B["Block Cipher Encryption"]
    B --> C["Ciphertext"]
    C --> D["EC8 mode"]
    B --> E["Encryption Key"]
    E --> F["Block Cipher Encryption"]
    F --> G["Ciphertext"]
    G --> H["CBC mode"]
    I["Plaintext"] --> J["Block Cipher Encryption"]
    J --> K["Ciphertext"]
    K --> L["EC8 mode"]
    J --> M["Encryption Key"]
    M --> N["Block Cipher Encryption"]
    N --> O["Ciphertext"]
    O --> P["EC8 mode"]
    style A fill:#f9f,stroke:#333
    style I fill:#ccf,stroke:#333
    style J fill:#cfc,stroke:#333
    style K fill:#fcc,stroke:#333
    style L fill:#ffc,stroke:#333

After preparing the AES key, and defining the AES operation direction using SRAM register bit AES\_DIR, the data has to be provided to the AES engine and the CBC operation can be started. The first CBC run has to be configured as ECB to process the initial data (plaintext XORed with an initialization vector provided by the microcontroller). All succeeding AES runs are to be configured as CBC by setting register bits AES\_MODE = 0x2 (register 0x83, AES\_CTRL). Register bit AES\_DIR (register 0x83, AES\_CTRL) must be set to AES\_DIR = 0 to enable AES encryption. The data to be processed has to be transferred to the SRAM starting with address 0x84 to 0x93 (register AES\_STATE). Setting register bit AES\_REQUEST = 1 (register 0x94, AES\_CTRL\_MIRROR) as described in Section 11.1.4 "Security Operation Modes" on page 129 starts the first encryption within one SRAM access. This causes the next 128 bits of plaintext data to be XORed with the previous cipher text data, see Figure 11-4 on page 131. According to IEEE 802.15.4 the input for the very first CBC operation has to be prepared by a XORing a plaintext with an initialization vector (IV). The value of the initialization vector is 0. However, for non-compliant usage any other initialization vector can be used. This operation has to be prepared by the microcontroller. Note that IEEE 802.15.4-2006 standard MIC algorithm requires CBC mode encryption only, as it implements a one-way hash function.

11.1.5 Data Transfer - Fast SRAM Access

The ECB and CBC modules including the AES core are clocked with 16 MHz. One AES operation takes 24 s to execute, refer to parameter 12.4.15 in Section 12.4 “Digital Interface Timing Characteristics” on page 157. That means that the processing of the data is usually faster than the transfer of the data via the SPI interface. To reduce the overall processing time the AT86RF231 provides a Fast SRAM access for the address space 0x82 to 0x94. Figure 11-5. Packet Structure - Fast SRAM Access Mode 

AES run #0 AES run #n AES access #0 AES access #1 AES access #n+1 MOSI cmd add cfg P0 P1 ... P14 P15 start mid stat xx xx xx xx ... xx xx xx MISO Address 0x83 ... 0x94 mid stat xx xx xx C0 ... C13 C14 C15 mid stat xx xx xx C0 ... C13 C14 C15 0x83 ... 0x94 byte 0 (cmd) byte 1 (addr.) byte 2 (cfg) byte 3 byte 4 byte 18 byte 19 (start) SRAM writeMOSaddress 0x83 P0[7:0] P1[7:0] ... P15[7:0] (1) PHY_STATUS ISO XX XX XX C0[7:0] ... C14[7:0] C15[7:0] Address 0x83 0x84 0x85 0x93 0x94

Note: Byte 19 is the mirrored version of register AES\_CTRL on SRAM address 0x94, see register description AES\_CTRL\_MIRROR for details. In contrast to a standard SRAM access, refer to Section 6.2.3 "SRAM Access Mode" on page 22, the Fast SRAM access allows writing and reading of data simultaneously during one SPI access for consecutive AES operations (AES run). For each byte P0 transferred to pin 22 (MOSI) for example in "AES access #1", see Figure 11-5 on page 132 (lower part), the previous content of the respective AES register C0 is clocked out at pin 20 (MISO) with an offset of one byte. In the example shown in Figure 11-5 on page 132 the initial plaintext P0 - P15 is written to the SRAM within "AES access #0". The last command on address 0x94 (AES\_CTRL\_MIRROR) starts the AES operation ("AES run #0"). In the next "AES access #1" new plaintext data P0 - P15 is written to the SRAM for the second AES run, in parallel the ciphertext C0 - C15 from the first AES run is clocked out at pin MISO. To read the ciphertext from the last "AES run #(n)" one dummy "AES access #(n+1)" is needed. Note that the SRAM write access always overwrites the previous processing result. The Fast SRAM access automatically applies to all write operations to SRAM addresses 0x82 to 0x94.

11.1.6 Start of Security Operation and Status

A security operation is started within one SRAM access by appending the start command AES\_REQUEST = 1 (register 0x94, AES\_CTRL\_MIRROR) to the SPI sequence. Register AES\_CTRL\_MIRROR is a mirrored version of register 0x83 (AES\_CTRL). The status of the security processing is indicated by register 0x82 (AES\_STATUS). After 24 s AES processing time register bit AES\_DONE changes to 1 (register 0x82, AES\_STATUS) indicating that the security operation has finished, see parameter 12.4.15 in Section 12.4 “Digital Interface Timing Characteristics” on page 157.

11.1.7 SRAM Register Summary

The following registers are required to control the security module: Table 11-2. SRAM Security Module Address Space Overview

SRAM-Addr. Register Name Description
0x80 - 0x81 Reserved, not available
0x82 AES_STATUS AES Status
0x83 AES_	CTRL Security Module	Control, AES Mode
0x84 - 0x93	AES_KEYAES_STATE	Depends on AES_MODE setting:AES_MODE = 1:- Contains AES_KEY (key)AES_MODE = 0 | 2:- Contains AES_STATE (128-bit data block)
0x94 AES_	CTRL_MIRROR	Mirror of register 0x83 (AES_CTRL)
0x95 - 0xFF Reserved, not available

These registers are only accessible using SRAM write and read accesses, for details refer to Section 6.2.3 "SRAM Access Mode" on page 22. Note, that the SRAM register are reset when entering the SLEEP state.

11.1.8 AES SRAM Configuration Register

Register 0x82 (AES\_STATUS): This read-only register signals the status of the security module and operation. 

• Bit 7 - AES\_ER

This SRAM register bit indicates an error of the AES module. An error may occur for instance after an access to SRAM register 0x83 (AES\_CTRL) while an AES operation is running or after reading less than 128 bits from SRAM register space 0x84 - 0x93 (AES\_STATE). Table 11-3. AES Core Operation Status

Register Bit Value Description
AES_ER 0	_	No error of the AES module
	1 AES module error

- Bit [6:1] -Reserved - Bit 0 - AES\_DONE Table 11-4. AES Core Operation Status

Register Bit Value Description
AES_DONE 0	_	AES Module is not finished
	1 AES module has finished

Register 0x83 (AES\_CTRL):

This register controls the operation of the security module. Do not access this register during AES operation to read the AES core status. A read or write access during AES operation stops the actual processing. To read the AES status use register bit AES\_DONE (register 0x82, AES\_STATUS).

Bit 7 6 5 4 3	2	1	0
+0x83	AES_REQUEST	AES_MODE			AES_DIR	Reserved			AES_CTRL
Read/Write	W	R/W	R/W	R/W	R/W	R	R	R
Reset Value	0	0	0	0	0	0	0	0

- Bit 7 - AES\_REQUEST

A write access with AES\_REQUEST = 1 initiates the AES operation. Table 11-5. AES Core Status

Register Bit	Value	Description
AES_REQUEST	0	Security module, AES core idle
	1 Write access: Start security module

- Bit [6:4] - AES\_MODE

This register bit sets the AES operation mode. Table 11-6. AES Mode

Register Bit	Value	Description
AES_MODE	0	ECB mode, refer to Section 11.1.4.1
	1 KEY	mode, refer to Section 11.1.3
	2 CBC	mode, refer to Section 11.1.4.2
	3 - 7	Reserved

- Bits 3 - AES\_DIR

This register bit sets the AES operation direction, either encryption or decryption. Table 11-7. AES Direction

Register Bit Value	Description
AES_DIR 0	_	AES encryption (ECB, CBC)
	1 AES decryption

- Bit [2:0] - Reserved

Register 0x94 (AES\_CTRL\_MIRROR):

Register 0x94 is a mirrored version of register 0x83 (AES\_CTRL), for details refer to register 0x83 (AES\_CTRL). 

Bit 7 6 5 4 3 2 1 0 +0x83 AES_REQUEST AES_MODE AES_DIR Reserved AES_CTRL Read/Write W R/W R/W R/W R R R Reset Value 0 0 0 0 0 0 0 0

This register could be used to start a security operation within a single SRAM access by appending it to the data stream and setting register bit AES\_REQUEST = 1.

11.2 Random Number Generator

11.2.1 Overview

The AT86RF231 incorporates a 2-bit truly random number generator by observation of noise. This random number can be used to: - Generate random seeds for CSMA-CA algorithm see Section 7.2 - Generate random values for AES key generation see Section 11.1 The random number is updated every t_TR29 = 1 s in Basic Operation Mode receive states. The values are stored in register bits RND\_VALUE (register 0x06, PHY\_RSSI).

11.2.2 Register Description

Register 0x06 (PHY\_RSSI):

Register 0x06 (PHY\_RSSI) is a multi purpose register to indicate FCS validity, to provide random numbers and an RSSI value. 

B i t 7 6 5 4 3 2 1 +0x06 RX_CRC_VALID RND_VALUE RSSI PHY_RSSI Read/Write R R R R R R Reset Value 0 0 0 0 0 0 0

- Bit 7 - RX\_CRC\_VALID

Refer to register description in Section 8.2.5 "Register Description" on page 87.

- Bit [6:5] - RND\_VALUE

The 2-bit random value can be retrieved by reading register bits RND\_VALUE. Note that the radio transceiver shall be in Basic Operating Mode receive state. The values are updated each t_TR29 = 1 s .

- Bit [4:0] - RSSI

Refer to register description in Section 8.3.4 "Register Description" on page 90. Note: Ensure that register bit RX\_PDT\_DIS (register 0x15, RX\_SYN) is set to 0 at least 1 s before reading a random value.

11.3 High Data Rate Modes

The main features are: • High Data Rate Transmission up to 2 Mb/s. - Support of Basic and Extended Operating Mode - Support of other features of the Extended Feature Set - Reduced ACK timing (optional)

11.3.1 Overview

The AT86RF231 also supports alternative data rates, higher than 250 kb/s for applications beyond IEEE 802.15.4 compliant networks. The selection of a data rate does not affect the remaining functionality. Thus it is possible to run all features and operating modes of the radio transceiver in various combinations. The data rate can be selected by writing to register bits OQPSK\_DATA\_RATE (register 0x0C, TRX\_CTRL\_2). The High Data Rate Modes occupy the same RF channel bandwidth as the IEEE 802.15.4-2.4 GHz 250 kb/s standard mode. Due to the decreased spreading factor, the sensitivity of the receiver is reduced accordingly. Table 11-8 on page 137 shows typical values of the sensitivity for different data rates. Table 11-8. High Data Rate Sensitivity

High Data Rate Sensitivity Comment

250 kb/s -101 dBm PER ≤ 1%, PSDU length of 20 octets

500 kb/s -97 dBm PER ≤ 1%, PSDU length of 20 octets

1000 kb/s -95 dBm PER ≤ 1%, PSDU length of 20 octets

2000 kb/s -89 dBm PER ≤ 1%, PSDU length of 20 octets

By default there is no header based signaling of the data rate within a transmitted frame. Thus nodes using a data rate other than the default IEEE 802.15.4 data rate of 250 kb/s are to be configured in advance and consistently. Alternatively the configurable start of frame delimiter (SFD) could be used as an indicator of the PHY data rate, see Section 11.9 "Configurable Start-Of-Frame Delimiter" on page 155.

11.3.2 High Data Rate Packet Structure

In order to allow appropriate frame synchronization, higher data rate modulation is restricted to the payload octets only. The SHR and the PHR field are transmitted with the IEEE 802.15.4 compliant data rate of 250 kb/s, refer to Section 8.1.1 "PHY Protocol Layer Data Unit (PPDU)" on page 79. A comparison of the general packet structure for different data rates with an example PSDU length of 80 octets is shown in Figure 11-6 on page 138. Figure 11-6. High Data Rate Frame Structure  Due to the overhead caused by the SHR, PHR as well as the FCS, the effective data rate is lower than the selected data rate. This is also affected by the length of the PSDU. A graphical representation of the effective PSDU data rate is shown in Figure 11-7 on page 138. Figure 11-7. Effective Data Rate "B" for High Data Rate Mode  The effective throughput is further affected by the MAC overhead, the acknowledgment scheme as well as the MCU processing capability. Consequently, High Data Rate transmission and reception is useful for large PSDU lengths due to the higher effective data rate, or to reduce the power consumption of the system. When using High Data Rate Modes the active on-air time is significantly reduced.

11.3.3 High Data Rate Frame Buffer Access

The Frame Buffer access to read or write frames for High Data Rate transmission is similar to the procedure described in Section 6.2.2 "Frame Buffer Access Mode" on page 20. However, during Frame Buffer read access the last byte transferred after the PSDU data is the ED value rather than the LQI value. Figure 11-8 on page 139 illustrates the packet structure of a High Data Rate Frame Buffer read access. Figure 11-8. Packet Structure - High Data Rate Frame Buffer Read Access 

byte 1 (command byte) byte 2 (data byte) byte 3 (data byte) 0 reset:xx[5:0]0MOSI XX ... XX XX PHY_STATUSMISO PHR[7:0] PSDU[7:0] ... PSDU[7:0] ED[7:0]

11.3.4 High Data Rate Energy Detection

According to IEEE 802.15.4 the ED measurement duration is 8 symbol periods. For frames operated at higher data rates the automated ED measurement duration is reduced to 32 s to take the reduced frame length into account, refer to Section 8.4 “Energy Detection (ED)” on page 91. During Frame Buffer read access the ED value is appended to the PSDU data, refer to Section 11.3.3 "High Data Rate Frame Buffer Access" on page 138.

11.3.5 High Data Rate Mode Options

Receiver Sensitivity Control

The different data rates between PPDU header (SHR and PHR) and PHY payload (PSDU) cause a different sensitivity between header and payload. This can be adjusted by defining sensitivity threshold levels of the receiver. With a sensitivity threshold level set (register bits RX\_PDT\_LEVEL > 0), the receiver does not receive frames with an RSSI level below that threshold. Under these operating conditions the receiver current consumption is reduced by about 500 A, refer to Section 12.8 “Current Consumption Specifications” on page 161 parameter 12.8.4. Enabling receiver sensitivity control with at least RX\_PDT\_LEVEL = 1 is recommended for the 2 Mb/s rate with a PSDU sensitivity of -89 dBm. In the case of receiving with the default setting of RX\_PDT\_LEVEL, a high data rate frame may be detected even if the PSDU sensitivity is above the received signal strength. In this case the frame is rejected. A description of the settings to control the sensitivity threshold with register 0x15 (RX\_SYN) can be found in Section 9.1.4 "Register Description" on page 103.

Reduced Acknowledgment Timing

On higher data rates the IEEE 802.15.4 compliant acknowledgment frame response time of 192 s significantly reduces the effective data rate of the network. To minimize this influence in Extended Operating Mode RX\_AACK, refer to Section 7.2.3 "RX\_AACK\_ON - Receive with Automatic ACK" on page 51, the acknowledgment frame response time can be reduced to 32 s. Figure 11-9 on page 140 illustrates an example for a reception and acknowledgement of a frame with a data rate of 2000 kb/s and a PSDU length of 80 symbols. The PSDU length of the acknowledgment frame is 5 octets according to IEEE 802.15.4. Figure 11-9. High Data Rate AACK Timing  If register bit AACK\_ACK\_TIME (register 0x17, XAH\_CTRL\_1) is set the acknowledgment time is reduced from 192 s to 32 s.

11.3.6 Register Description

Register 0x0C (TRX\_CTRL\_2):

The TRX\_CTRL\_2 register controls the data rate setting 

Bit 7 6 5 4 3 2 1 +0x0C RX_SAFE_MODE Reserved OQPSK_DATA_RATE TRX_CTRL_2 Read/Write R/W R R R R R R/W R/W Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

\- Bit 7 - RX\_SAFE\_MODE Refer to Section 11.8.2 "Register Description" on page 154. \- Bit [6:2] - Reserved \- Bit [1:0] - OQPSK\_DATA\_RATE A write access to these register bits sets the OQPSK PSDU data rate used by the radio transceiver. The reset value OQPSK\_DATA\_RATE = 0 is the PSDU data rate according to IEEE 802.15.4. Table 11-9. OQPSK Data Rate

Register Bits	Value	OQPSK Data Rate	Comment
OQPSK_DATA_RATE 0	-	250 kb/s	IEEE 802.15.4 compliant
	1	500 kb/s
	2	1000 kb/s
	3	2000 kb/s

Register 0x17 (XAH\_CTRL\_1):

The XAH\_CTRL\_1 register is a multi-purpose control register for various RX\_AACK settings. Bit 76543210

+0x17	Reserved		AACK_FLTR_RES_FT	AACK_UPLD_RES_FT	Reserved	AACK_ACK_TIME	AACK_PROM_MODE	Reserved	XAH_CTRL_1
Read/Write	R/W	R	R/W	R/W	R	R/W	R/W	R
Reset Value	0 0 1 0 0 0 0 0

- Bit [7:6] - Reserved - Bit 5 - AACK\_FLTR\_RES\_FT Refer to 7.2.7 "Register Description - Control Registers" on page 68. \- Bit 4 - AACK\_UPLD\_RES\_FT Refer to Section 7.2.7 "Register Description - Control Registers" on page 68. \- Bit 3 - Reserved \- Bit 2 - AACK\_ACK\_TIME According to IEEE 802.15.4, section 7.5.6.4.2 the transmission of an acknowledgment frame shall commence 12 symbol periods (aTurnaroundTime) after the reception of the last symbol of a data or MAC command frame. This is fulfilled with the reset value of the register bit [2] (AACK\_ACK\_TIME). If AACK\_ACK\_TIME = 1 an acknowledgment frame is sent 32 s after the reception of the last symbol of a data or MAC command frame. This may be applied to proprietary networks including networks using the High Data Rate Modes to improve the overall data throughput. \- Bit 1 - AACK\_PROM\_MODE Refer to Section 7.2.7 "Register Description - Control Registers" on page 68. \- Bit 0 - Reserved

11.4 Antenna Diversity

The Antenna Diversity implementation is characterized by: - Improves signal path robustness between nodes - AT86RF231 self-contained antenna diversity algorithm - Direct register based antenna selection

11.4.1 Overview

Due to multipath propagation effects between network nodes, the receive signal strength may vary and affect the link quality, even for small changes of the antenna location. These fading effects can result in an increased error floor or loss of the connection between devices. To improve the reliability of an RF connection between network nodes Antenna Diversity can be applied to reduce effects of multipath propagation and fading. Antenna Diversity uses two antennas to select the most reliable RF signal path. This is done by the radio transceiver during preamble field search without the need for microcontroller interaction. To ensure highly independent receive signals on both antennas, the antennas should be carefully separated from each other. If a preamble field is detected on one antenna, this antenna is selected for reception. Otherwise the search is continued on the other antenna and vice versa. Antenna Diversity can be used in Basic and Extended Operating Modes and can also be combined with other features and operating modes like High Data Rate Mode and RX/TX Indication.

11.4.2 Antenna Diversity Application Example

A block diagram for an application using an antenna switch is shown in Figure 11-10 on page 142. Figure 11-10. Antenna Diversity - Block Diagram 

graph TD
    ANT0["ANT0"] --> RF_Switch["RF-Switch"]
    ANT1["ANT1"] --> RF_Switch
    RF_Switch --> Balun["Balun"]
    Balun --> 1["1 DIG3"]
    Balun --> 2["2 DIG4"]
    Balun --> 3["3 AVSS"]
    Balun --> 4["4 RFP"]
    Balun --> 5["5 RFN"]
    Balun --> 6["6 AVSS"]
    1 --> AT86RF231["AT86RF231"]
    2 --> AT86RF231
    3 --> AT86RF231
    4 --> AT86RF231
    5 --> AT86RF231
    6 --> AT86RF231
    7["..."] --> DIG1["9 DIG1"]
    7 --> DIG2["10 DIG2"]

Generally, the Antenna Diversity algorithm is enabled with register bit ANT\_DIV\_EN (register 0x0D, ANT\_DIV) set. In this case the control of an antenna diversity switch must be enabled by register bit ANT\_EXT\_SW\_EN (register 0x0D, ANT\_DIV). The internal connection to digital ground of the control pins pin 9 (DIG1) and pin 10 (DIG2) is disabled (refer to section 4.2), and they feed the antenna switch signal and its inverse to the differential inputs of the RF Switch (SW1). Upon reception of a frame the AT86RF231 selects one antenna during preamble field detection. The selected antenna is then indicated by register bit ANT\_SEL (register 0x0D, ANT\_DIV). After the frame reception is completed, the antenna selection continues searching for new frames on both antennas. However, the register bit ANT\_SEL maintains its previous value (from the last received frame) until a new SHR has been found, and the selection algorithm locked into one antenna again. At this time the register bit ANT\_SEL is updated again. For transmission the antenna defined by register bits ANT\_CTRL (register 0x0D, ANT\_DIV) is selected. If for example the same antenna is to be used for transmission as being selected for reception, the antenna must be set using register bits ANT\_CTRL, based on the value read from register bit ANT\_SEL. It is recommended to read register bit ANT\_SEL after IRQ\_2 (RX\_START). The autonomous search and selection allows the use of Antenna Diversity during reception even if the microcontroller does currently not control the radio transceiver, for instance in Extended Operating Mode. A microcontroller defined selection of a certain antenna can be done by disabling the automated Antenna Diversity algorithm (ANT\_DIV\_EN = 0) and selecting one antenna using register bit ANT\_CTRL. If the AT86RF231 is not in a receive or transmit state, it is recommended to disable register bit ANT\_EXT\_SW\_EN to reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP state. If register bit ANT\_EXT\_SW\_EN = 0, output pins DIG1/DIG2 are pulled-down to digital ground.

11.4.3 Antenna Diversity Sensitivity Control

Due to a different receive algorithm used by the Antenna Diversity algorithm, the correlator threshold of the receiver has to be adjusted. It is recommended to set register bits PDT\_THRES (register 0x0A, RX\_CTRL) to 3.

11.4.4 Register Description

Register 0x0A (RX\_CTRL): The RX\_CTRL controls the sensitivity of the Antenna Diversity Mode 

Bit 7 6 5 4 3 2 1 0 +0x0A Reserved PDT_THRES RX_CTRL Read/Write R/W R/W R/W R/W R/W R/W R/W Reset Value 1 0 1 1 0 1 1 1

- Bit [7:4] - Reserved

- Bit [3:0] - PDT\_THRES

These register bits control the sensitivity of the receiver correlation unit. If the Antenna Diversity algorithm is enabled (ANT\_DIV\_EN = 1), the value shall be set to PDT\_THRES = 3, otherwise it shall be set back to the reset value. This is not automatically done by the hardware. Table 11-10. Receiver Sensitivity Control

Register Bit Value	Description
PDT_THRES 0x7	—	Reset value, to be used if Antenna Diversity algorithm is disabled
	0x3	Recommended correlator threshold for Antenna Diversity operation
	Other	Reserved

Register 0x0D (ANT\_DIV):

The ANT\_DIV register controls Antenna Diversity.

Bit 7 6 5 4 3	2	1	0
+0x0D	ANT_SEL	Reserved			ANT_DIV_EN	ANT_EXT_SW_EN	ANT_CTRL	ANT_DIV
Read/Write	R	R	R	R	R/W	R/W	R/W	R/W
Reset Value	0	0	0	0	0	0	1	1

- Bit 7 - ANT\_SEL

This register bit signals the currently selected antenna path. The selection may be based either on the last antenna diversity cycle (ANT\_DIV\_EN = 1) or on the content of register bits ANT\_CTRL, for details refer to Section 11.4.2 "Antenna Diversity Application Example" on page 142. Table 11-11. Antenna Diversity - Antenna Status

Register Bit Value	Description
ANT_SEL	0	Antenna 0
	1	Antenna 1

- Bit [6:4] - Reserved

- Bit 3 - ANT\_DIV\_EN

If register bit ANT\_DIV\_EN is set, the Antenna Diversity algorithm is enabled. On reception of a frame the algorithm selects an antenna autonomously during SHR search. This selection is kept until: • A new SHR search starts • Leaving receive states - Manually programmed register bits ANT\_CTRL Table 11-12. Antenna Diversity Control

Register Bit Value Description
ANT_DIV_EN 0	_	Antenna Diversity algorithm disabled
	1 Antenna Diversity algorithm enabled

Note: If ANT\_DIV\_EN = 1 register bit ANT\_EXT\_SW\_EN shall be set to 1, too. This is not automatically done by the hardware.

- Bit 2 - ANT EXT SW EN

If enabled, pin 9 (DIG1) and pin 10 (DIG2) become output pins and provide a differential control signal for an Antenna Diversity switch. The selection of a specific antenna is done either by the automated Antenna Diversity algorithm (ANT\_DIV\_EN = 1), or according to register bits ANT\_CTRL if Antenna Diversity algorithm is disabled. Do not enable Antenna Diversity RF switch control (ANT\_EXT\_SW\_EN = 1) and RX Frame Time Stamping (IRQ\_2\_EXT\_EN = 1) at the same time, see Section 11.6 "RX Frame Time Stamping" on page 150. If the register bit is set the control pins DIG1/DIG2 are activated in all radio transceiver states as long as register bit ANT\_EXT\_SW\_EN is set. If the AT86RF231 is not in a receive or transmit state, it is recommended to disable register bit ANT\_EXT\_SW\_EN to reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP state. If register bit ANT\_EXT\_SW\_EN = 0, output pins DIG1 and DIG2 are pulled-down to digital ground. Table 11-13. Antenna Diversity RF Switch Enable

Register Bit Value Description
ANT_EXT_SW_EN 0	_	Antenna Diversity RF Switch Control disabled
	1 Antenna Diversity RF Switch Control enabled

Note: If ANT\_EXT\_SW\_EN = 0, register bit ANT\_DIV\_EN shall be set to 0 and register bits ANT\_CTRL to 3. This is not automatically done by the hardware.

- Bit [1:0] - ANT\_CTRL

These register bits provide a static control of an Antenna Diversity switch. Setting ANT\_DIV\_EN = 0 (Antenna Diversity disabled), this register setting defines the selected antenna. Although it is possible to change register bits ANT\_CTRL in state TRX\_OFF, this change will be effective at pins DIG1 and DIG2 in state PLL\_ON as well as all receive and transmit states. Table 11-14. Antenna Diversity Switch Control

Register Bit Value Description

Table 11-14. Antenna Diversity Switch Control

ANT_CTRL 0 Reserved
1 Antenna 1DIG1 = LDIG2 = H
2 Antenna 0DIG1 = HDIG2 = L
3 Default value for ANT_EXT_SW_EN = 0.Mandatory setting for applications not using Antenna Diversity.

Note: Register values 1 and 2 are valid for ANT\_EXT\_SW\_EN = 1.

11.5 RX/TX Indicator

The main features are: - RX/TX Indicator to control an external RF Front-End - Microcontroller independent RF Front-End Control - Provide TX Timing Information

11.5.1 Overview

While IEEE 802.15.4 is a low cost, low power standard, solutions supporting higher transmit output power are occasionally desirable. To simplify the control of an optional external RF front-end, a differential control pin pair can indicate that the AT86RF231 is currently in transmit mode. The control of an external RF front-end is done via digital control pins DIG3/DIG4. The function of this pin pair is enabled with register bit PA\_EXT\_EN (register 0x04, TRX\_CTRL\_1). While the transmitter is turned off pin 1 (DIG3) is set to low level and pin 2 (DIG4) to high level. If the radio transceiver starts to transmit, the two pins change the polarity. This differential pin pair can be used to control PA, LNA, and RF switches. If the AT86RF231 is not in a receive or transmit state, it is recommended to disable register bit PA\_EXT\_EN (register 0x04, TRX\_CTRL\_1) to reduce the power consumption or avoid leakage current of external RF switches and other building blocks, especially during SLEEP state. If register bits PA\_EXT\_EN = 0, output pins DIG3/DIG4 are pulled-down to analog ground.

11.5.2 External RF-Front End Control

Using an external RF front-end including a power amplifier (PA) it may be required to adjust the setup time of the external PA relative to the internal building blocks to optimize the overall power spectral density (PSD) mask. Figure 11-11. TX Power Ramping Control for RF Front-Ends 

0 6 2 8 4 1 0 12 14 16 18 Length [µs] TRX_STATE PLL_ON BUSY_TX SLP_TR PA buffer PA_BUF_LT PA Modulation PA_LT DIG3 DIG4

The start-up sequence of the individual building blocks of the internal transmitter is shown in Figure 11-11 on page 147, where transmission is actually initiated by the rising edge of pin 11 (SLP\_TR). The radio transceiver state changes from PLL\_ON to BUSY\_TX and the PLL settles to the transmit frequency within 16 s. The modulation starts 16 s after the rising edge of SLP\_TR. During this time, the PA buffer and the internal PA are enabled. The control of an external PA is done via differential pin pair DIG3/DIG4. DIG3 = H / DIG4 = L indicates that the transmission starts and can be used to enable an external PA. The timing of pins DIG3/DIG4 can be adjusted relative to the start of the frame and the activation of the internal PA buffer. This is controlled using register bits PA\_BUF\_LT and PA\_LT. For details refer to Section 9.2.4 "TX Power Ramping" on page 104.

11.5.3 Register Description

Register 0x04 (TRX\_CTRL\_1):

The TRX\_CTRL\_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit 76543210

+0x04	PA_EXT_EN	IRQ_2_EXT_EN	TX_AUTO_CRC_ON	RX_BL_CTRL	SPI_CMD_MODE	IRQ_MASK_MODE	IRQ_POLARITY	TRX_CTRL_1
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset Value	0 0 1 0		0	0 0

- Bit 7 - PA\_EXT\_EN

This register bit enables pin 1 (DIG3) and pin 2 (DIG4) to indicate the transmit state of the radio transceiver. Table 11-15. RF Front-End Control Pins

PA_EXT_EN	State	Pin	Value	Description
0	n/a	DIG3	L	External RF front-end control disabled
		DIG4	L
1(1)	TX_BUSY	DIG3	H	External RF front-end control enabled
		DIG4	L
	Other	DIG3	L
		DIG4	H

Note: 1. It is recommended to set PA\_EXT\_EN = 1 only in receive or transmit states to reduce the power consumption or avoid leakage current of external RF switches or other building blocks, especially during SLEEP state.

- Bit 6 - IRQ\_2\_EXT\_EN

Refer to Section 11.6 "RX Frame Time Stamping" on page 150.

- Bit 5 - TX\_AUTO\_CRC\_ON

Refer to Section 8.2 "Frame Check Sequence (FCS)" on page 85.

- Bit 4 - RX\_BL\_CTRL

Refer to Section 11.7 "Frame Buffer Empty Indicator" on page 152.

- Bit [3:2] - SPI\_CMD\_MODE

Refer to Section 6.3 "Radio Transceiver Status information" on page 24. \- Bit 1 - IRQ\_MASK\_MODE Refer to Section 6.6 "Interrupt Logic" on page 29. \- Bit 0 - IRQ\_POLARITY Refer to Section 6.6 "Interrupt Logic" on page 29.

11.6 RX Frame Time Stamping

11.6.1 Overview

To determine the exact timing of an incoming frame, e.g. for beaconing networks, the reception of this frame can be signaled to the microcontroller via pin 10 (DIG2). The pin turns from L to H after a detection of a valid PHR. When enabled, DIG2 is set to DIG2 = H at the same time as IRQ\_2 (RX\_START), even if IRQ\_2 is disabled. The pin remains high for the length of the frame receive procedure, see Figure 11-3 on page 130. Figure 11-12. Timing of RX\_START and DIG2 for RX Frame Time Stamping 

0 128 160 192 192 + m * 32 Time [µs] Number of Octets Frame Content 4 1 1 m < 128 Preamble SFD PHR PSDU (250 kb/s) TRX_STATE RX_ON RX_ON BUSY_RX DIG2 (RX Frame Time Stamp) IRQ Interrupt latency t_IRQ t_IRQ TRX_END

Note: Timing figures refer to 12.4 "Digital Interface Timing Characteristics" on page 157. This function is enabled with register bit IRQ\_2\_EXT\_EN (register 0x04) set. Pin 10 (DIG2) could be connected to a timer capture unit of the microcontroller. If this pin is not used for RX Frame Time Stamping it can be configured for Antenna Diversity. Otherwise this pin is pulled-down to digital ground.

11.6.2 Register Description

Register 0x04 (TRX\_CTRL\_1):

Register 0x04 (TRX\_CTRL\_1) is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit 76543210

+0x04	PA_EXT_EN	IRQ_2_EXT_EN	TX_AUTO_CRC_ON	RX_BL_CTRL	SPI_CMD_MODE	IRQ_MASK_MODE	IRQ_POLARITY	TRX_CTRL_1
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset Value	0 0 1 0		0	0 0

- Bit 7 - PA\_EXT\_EN

Refer to Section 11.5 "RX/TX Indicator" on page 147.

- Bit 6 - IRQ\_2\_EXT\_EN

If this register bit is set the RX Frame Time Stamping Mode is enabled. An incoming frame with a valid PHR is signaled via pin 10 (DIG2). The pin remains at high level until the end of the frame receive procedure, see Figure 11-12 on page 150. Do not enable RX Frame Time Stamping (IRQ\_2\_EXT\_EN = 1) and Antenna Diversity (ANT\_EXT\_SW\_EN = 1) at the same time, see Section 11.4 "Antenna Diversity" on page 142.

- Bit 5 - TX\_AUTO\_CRC\_ON

Refer to Section 8.2 "Frame Check Sequence (FCS)" on page 85.

- Bit 4 - RX\_BL\_CTRL

Refer to Section 11.7 "Frame Buffer Empty Indicator" on page 152.

- Bit [3:2] - SPI\_CMD\_MODE

Refer to Section 6.3 "Radio Transceiver Status information" on page 24.

- Bit 1 - IRQ\_MASK\_MODE

Refer to Section 6.6 "Interrupt Logic" on page 29.

- Bit 0 - IRQ\_POLARITY

Refer to Section 6.6 "Interrupt Logic" on page 29.

11.7 Frame Buffer Empty Indicator

11.7.1 Overview

For time critical applications that want to start reading the frame data as early as possible, the Frame Buffer status can be indicated to the microcontroller through a dedicated pin. This pin indicates to the microcontroller if an access to the Frame Buffer is not possible since valid PSDU data are missing. Pin 24 (IRQ) can be configured as a Frame Buffer Empty Indicator during a Frame Buffer read access. This mode is enabled by register bit RX\_BL\_CTRL (register 0x04, TRX\_CTRL\_1). The IRQ pin turns into Frame Buffer Empty Indicator after the Frame Buffer read access command, see note (1) in Figure 11-13 on page 152, has been transferred on the SPI bus until the Frame Buffer read procedure has finished indicated by /SEL = H, see note (4). Figure 11-13. Timing Diagram of Frame Buffer Empty Indicator 

/SEL SCLK MOSI Command XX Command XX XX XX XX XX XX XX MISO PHY_STATUS IRQ_STATUS PHY_STATUS PHR[7:0] PSDU[7:0] PSDU[7:0] PSDU[7:0] LQ[7:0] PHY_STATUS IRQ_STATUS IRQ IRQ_2 (RX_START) Frame Buffer Empty Indicator t13 (1) (4)(3)(2)Notes IRQ_3 (TRX_END)

The microcontroller has to observe the IRQ pin during the Frame Buffer read procedure. A Frame Buffer read access can proceed as long as pin IRQ = L, see note (2). Pin IRQ = H indicates that the Frame Buffer is currently not ready for another SPI cycle, note (3), and thus the Frame Buffer read procedure has to wait for valid data accordingly. The access indicator pin 24 (IRQ) shows a valid access signal (either access is allowed or denied) not before t_13 = 750 nsec after the rising edge of last SCLK clock of the Frame Buffer read command byte. After finishing the SPI frame receive procedure, and the SPI has been released by /SEL = H, note (4), pending interrupts are indicated immediately by pin IRQ. During all other SPI accesses, except during a SPI frame receive procedure with RX\_BL\_CTRL = 1, pin IRQ only indicates interrupts. If a receive error occurs during the Frame Buffer read access the Frame Buffer Empty Indicator locks on 'empty' (pin IRQ = H) too. To prevent possible deadlocks, the microcontroller should impose a timeout counter that checks whether the Frame Buffer Empty Indicator remains logic high for more than 64 s. Presuming a PHY data rate of 250 kb/s a new byte must have been arrived at the Frame Buffer during that period. If not, the Frame Buffer read access should be aborted.

11.7.2 Register Description

Register 0x04 (TRX\_CTRL\_1):

The TRX\_CTRL\_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit 76543210

+0x04	PA_EXT_EN	IRQ_2_EXT_EN	TX_AUTO_CRC_ON	RX_BL_CTRL	SPI_CMD_MODE	IRQ_MASK_MODE	IRQ_POLARITY	TRX_CTRL_1
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset Value	0 0 1 0		0	0 0

- Bit 7 - PA\_EXT\_EN

Refer to Section 11.5 "RX/TX Indicator" on page 147.

- Bit 6 - IRQ\_2\_EXT\_EN

Refer to Section 11.6 "RX Frame Time Stamping" on page 150.

- Bit 5 - TX\_AUTO\_CRC\_ON

Refer to Section 8.2 "Frame Check Sequence (FCS)" on page 85.

- Bit 4 - RX\_BL\_CTRL

If this register bit is set the Frame Buffer Empty Indicator is enabled. After sending a Frame Buffer read command, refer to Section 6.2 "SPI Protocol" on page 19, pin 24 (IRQ) indicates to the microcontroller that an access to the Frame Buffer is not possible since valid PSDU data are missing. Pin IRQ does not indicate any interrupts during this time. Table 11-16. Frame Buffer Empty Indicator

Register Bit	Value	Description
RX_BL_CTRL	0	Frame Buffer Empty Indicator disabled
	1	Frame Buffer Empty Indicator enabled

- Bit [3:2] - SPI\_CMD\_MODE

Refer to Section 6.3 "Radio Transceiver Status information" on page 24.

- Bit 1 - IRQ\_MASK\_MODE

Refer to Section 6.6 "Interrupt Logic" on page 29.

- Bit 0 - IRQ\_POLARITY

Refer to Section 6.6 "Interrupt Logic" on page 29.

11.8 Dynamic Frame Buffer Protection

11.8.1 Overview

The AT86RF231 continues the reception of incoming frames as long as it is in any receive state. When a frame was successfully received and stored into the Frame Buffer, the following frame will overwrite the Frame Buffer content again. To relax the timing requirements for a Frame Buffer read access the Dynamic Frame Buffer Protection prevents that a new valid frame passes to the Frame Buffer until a Frame Buffer read access has ended (indicated by /SEL = H, refer to Section 6.2 "SPI Protocol" on page 19). A received frame is automatically protected against overwriting: - in Basic Operating Mode, if its FCS is valid - in Extended Operating Mode, if an IRQ\_3 (TRX\_END) is generated The Dynamic Frame Buffer Protection is enabled, if register bit RX\_SAFE\_MODE (register 0x0C, TRX\_CTRL\_2) is set and the transceiver state is RX\_ON or RX\_AACK\_ON. Note that Dynamic Frame Buffer Protection only prevents write accesses from the air interface - not from the SPI interface. A Frame Buffer or SRAM write access may still modify the Frame Buffer content.

11.8.2 Register Description

Register 0x0C (TRX\_CTRL\_2):

The TRX\_CTRL\_2 register is a multi purpose register to control various settings of the radio transceiver. 

Bit 7 6 5 4 3 2 1 0 +0x0C RX_SAFE_MODE Reserved OQPSK_DATA_RATE TRX_CTRL_2 Read/Write R/W R R R R R R/W R/W Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

- Bit 7 - RX\_SAFE\_MODE

If this bit is set Dynamic Frame Buffer Protection is enabled: Table 11-17. Dynamic Frame Buffer Protection Mode

Register Bit	Value	Description
RX\_SAFE\_MODE^(1)	0	Disable Dynamic Frame Buffer Protection
	1	Enable Dynamic Frame Buffer Protection

Note: 1. Dynamic Frame Buffer Protection is released with the rising edge of pin23 (/SEL) of a Frame Buffer read access, see Section 6.2.2 "Frame Buffer Access Mode" on page 20, or radio transceiver state changing from RX\_ON or RX\_AACK\_ON to another state. This operation mode is independent of the setting of register bits RX\_PDT\_LEVEL, refer to Section 9.1.3 "Configuration" on page 102. \- Bit [6:2] - Reserved \- Bit [1:0] - OQPSK\_DATA\_RATE Refer to Section 11.3 "High Data Rate Modes" on page 137.

11.9 Configurable Start-Of-Frame Delimiter

11.9.1 Overview

The SFD is a field indicating the end of the SHR and the start of the packet data. The length of the SFD is 1 octet (2 symbols). This octet is used for byte synchronization only and is not included in the Frame Buffer. The value of the SFD could be changed if it is needed to operate non IEEE 802.15.4 compliant networks. An IEEE 802.15.4 compliant network node does not synchronize to frames with a different SFD value. Due to the way the SHR is formed, it is not recommended to set the low-order 4 bits to 0. The LSB of the SFD is transmitted first, i.e. right after the last bit of the preamble sequence.

11.9.2 Register Description

Register 0x0B (SFD\_VALUE):

This register contains the one octet start-of-frame delimiter (SFD) to synchronize to a received frame. 

B i t 7 6 5 4 3 2 1 0 +0x0B SFD_VALUE[7:0] SFD_VALUE Read/Write R/W R/W R/W R/W R/W R/W R/W R e s e t V a l u e 1 0 1

- Bit [7:0] - SFD\_VALUE

For compliant IEEE 802.15.4 networks set SFD\_VALUE = 0xA7, as specified by [1] and [2]. This is the default value of the register. To establish non IEEE 802.15.4 compliant networks the SFD value can be changed to any other value. If enabled an IRQ\_2 (RX\_START) is issued only if the received SFD matches the register content of register SFD\_VALUE and a valid PHR is received.

12. Electrical Characteristics

12.1 Absolute Maximum Ratings

Note: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 12-1. Absolute Maximum Ratings

No. Symbol Parameter Condition Min. Typ. Max Units
12.1.1	T_STOR	Storage temperature		-50		150	°C
12.1.2	T_LEAD	Lead temperature	T = 10s,(soldering profile compliant with IPC/JEDEC J STD 020B)			260	°C
12.1.3	V_ESD	ESD robustness	Compl. to [3],Compl. to [4]	50001500			VV
12.1.4	P_RF	Input RF level				+10	dBm
12.1.5	V_DIG	Voltage on all pins(except pins 4, 5, 13, 14, 29)		-0.3		V_DD+0.3 V
12.1.6	V_ANA	Voltage on pins 4, 5, 13, 14, 29		-0.3		2.0	V

12.2 Recommended Operating Range

Table 12-2. Recommended Operating Range

No. Symbol Parameter Condition Min. Typ. Max Units
12.2.1	T_OP	Operating temperature range		-40		+85	°C
12.2.2	V_DD	Supply voltage	Voltage on pins 15, 28(1)	1.8	3.0	3.6	V
12.2.3	V_DD1.8	Supply voltage	External voltage supply on pins 13, 14, 29(2)	1.7	1.8	1.9	V

Notes: 1. Even if an implementation uses the external 1.8V voltage supply V _DD1.8 it is required to connect V _DD . 2. Register 0x10 (VREG\_CTRL) needs to be programmed to disable internal voltage regulators and supply blocks by an external 1.8V supply, refer to "Voltage Regulators (AVREG, DVREG)" on page 110.

12.3 Digital Pin Characteristics

.Test Conditions: T_OP = 25^ (unless otherwise stated) Table 12-3. Digital Pin Characteristics

No. Symbol Parameter Condition Min. Typ. Max Units
12.3.1 V	IH	High level input voltage^(1)		V_DD - 0.4 V
12.3.2 V	IL	Low level input voltage^(1)				0.4	V
12.3.3 V	OH	High level output voltage^(1)	For all output driver strengths defined in TRX_CTRL_0	V_DD - 0.4 V
12.3.4 V	OL	Low level output voltage^(1)	For all output driver strengths defined in TRX_CTRL_0			0.4	V

Note: 1. The capacitive load should not be larger than 50 pF for all I/Os when using the default driver strength settings, refer to Section 1.3.1 "Driver Strength Settings" on page 7. Generally, large load capacitances increase the overall current consumption.

12.4 Digital Interface Timing Characteristics

Test Conditions: T_OP = 25^ , V_DD = 3.0V , C_L = 50 pF (unless otherwise stated). Table 12-4. Digital Interface Timing Characteristics

No.	Symbol	Parameter	Condition	Min.	Typ.	Max	Units
12.4.1 f	sync	SCLK frequency	synchronous operation			8	MHz
12.4.2	f_async	SCLK frequency	asynchronous operation			7.5	MHz
12.4.3	t_1	/SEL low to MISO active				180	ns
12.4.4	t_2	SCLK to MISO out	data hold time	10			ns
12.4.5	t_3	MOSI setup time		10			ns
12.4.6	t_4	MOSI hold time		10			ns
12.4.7	t_5	LSB last byte to MSB next byte		250^(2)			ns
12.4.8	t_6	/SEL high to MISO tri state				10	ns
12.4.9	t_7	SLP_TR pulse width	TX start trigger	62.5		Note (1)	ns
12.4.10	t_8	SPI idle time (SEL rising to falling edge)	SPI read/write, standard SRAM and Frame Buffer access modes, Idle time between consecutive SPI accesses	250			ns
12.4.11	t_8	SPI idle time (SEL rising to falling edge)	SPI Fast SRAM read/write access mode, refer to Section 11.1.5, Idle time between consecutive SPI accesses	500			ns
12.4.12	t_9	Last SCLK to /SEL high			250		ns
12.4.13	t_10	Reset pulse width	10 clock cycles at 16 MHz	625			ns
12.4.14	t_11	SPI access latency after reset	10 clock cycles at 16 MHz	625			ns
12.4.15	t_12	AES core cycle time			24		μs
12.4.15 t	13	BFBP IRQ latency 750 ns
12.4.17 t	IRQ	Interrupt event latency Relative to the event to be indicated 9 μs
12.4.18 f	CLKM	Clock frequency at pin 17 (CLKM) Configurable in register 0x03 (TRX_CTRL_0)			0		MHz
					1		MHz
					2		MHz
					4		MHz
					8		MHz
					16		MHz
					250		kHz
					62.5		kHz

Notes: 1. Maximum pulse width less than (TX frame length + 16 s) 2. For Fast SRAM read/write accesses on address space 0x82 - 0x94 the time t _5 (Min.) increases to 450 ns.

12.5 General RF Specifications

Test Conditions (unless otherwise stated): $$ V _ {D D} = 3. 0 V, f _ {R F} = 2. 4 5 \mathrm{GHz}, T _ {O P} = 2 5 ^ {\circ} \mathrm{C}, \text { Measurement setup see Figure 5 - 1 on page 12. } $$ Table 12-5. General RF Specifications

No.	Symbol	Parameter	Condition	Min.	Typ.	Max	Units
12.5.1	f_RF	Frequency range	As specified in [1], [2]	2405		2480	MHz
12.5.2	f_CH	Channel spacing	As specified in [1], [2]		5		MHz
12.5.3	f_HDR	Header bit rate (SHR, PHR)	As specified in [1], [2]		250		kb/s
12.5.4	f_PSDU	PSDU bit rate	As specified in [1], [2]OQPSK_DATA_RATE = 1OQPSK_DATA_RATE = 2OQPSK_DATA_RATE = 3		25050010002000		kb/skb/skb/skb/s
12.5.5	f_CHIP	Chip rate	As specified in [1], [2]		2000		kchip/s
12.5.6	f_CLK	Crystal oscillator frequency	Reference oscillator		16		MHz
12.5.7	t_XTAL	Reference oscillator settling time	Leaving SLEEP state to clock available at pin 17 (CLKM)		330	1000	μs
12.5.8		Symbol rate deviationReference frequency accuracy for correct functionality	PSDU bit rate 250 kb/sPSDU bit rate 500 kb/sPSDU bit rate 1000 kb/sPSDU bit rate 2000 kb/s	-60(1)-40-40-30		+60+40+40+30	ppmppmppm
12.5.9	B_20dB	20 dB bandwidth			2.8		MHz

Note: 1. A reference frequency accuracy of ±40 ppm is required by [1], [2].

12.6 Transmitter Characteristics

Test Conditions (unless otherwise stated): $$ V _ {D D} = 3. 0 V, f _ {R F} = 2. 4 5 \mathrm{GHz}, T _ {O P} = 2 5 ^ {\circ} \mathrm{C}, \text { Measurement setup see Figure 5 - 1 on page 12. } $$ Table 12-6. Transmitter Characteristics

No. Symbol Parameter Condition Min. Typ. Max Units
12.6.1 P	TX	TX Output power Maximum configurable TX outputpower valueRegister bit TX_PWR = 0	0	+	3	+
12.6.2 P	RANGE	Output power range 16 steps, configurable inregister 0x05 (PHY_TX_PWR)		20		dB
12.6.3 P	ACC	Output power tolerance				±3	dB
12.6.4		TX Return loss	100Ω differential impedance, P_TX = +3 dBm		10		dB
12.6.5		EVM			8		%rms
12.6.6 P	HARM	Harmonics 2^nd harmonic 3^rd harmonic		-45	-45		dBmdBm
12.6.7 P	SPUR	Spurious Emissions30 - ≤ 1000 MHz>1 - 12.75 GHz1.8 - 1.9 GHz5.15 - 5.3 GHz	Complies withEN 300 328/440,FCC-CFR-47 part 15,ARIB STD-66, RSS-210		-36-30-47-47		dBmdBmdBmdBm

12.7 Receiver Characteristics

Test Conditions (unless otherwise stated): V_DD = 3.0V , f_RF = 2.45 GHz , T_OP = 25^ , PSDU bit rate = 250 kb/s, Measurement setup see Figure 5-1 on page 12. Table 12-7. Receiver Characteristics

No. Symbol Parameter Condition Min. Typ. Max Units
12.7.1 P	SENS	Receiver sensitivity250 kb/s500 kb/s1000 kb/s2000 kb/s	AWGN channel, PER ≤ 1%,PSDU length 20 octetsHigh Data Rate Modes:PSDU length 20 octets		-101-97-95-89		dBmdBmdBmdBm
		Antenna Diversity	250 kb/s, PSDU 20 octets		-99		dBm
12.7.2	RL	Return loss	100Ω differential impedance		10		dB
12.7.3	NF	Noise figure			6		dB
12.7.4 P	RXMX	Maximum RX input level	PER ≤ 1%, PSDU length of 20 octets		10		dBm
12.7.5 P	ACRN	Adjacent channel rejection: f = -5 MHz	PER ≤ 1%, PSDU length of 20 octets, P_RF = -82 dBm		32		dB
12.7.6 P	ACRP	Adjacent channel rejection: f = +5 MHz	PER ≤ 1%, PSDU length of 20 octets, P_RF = -82 dBm		35		dB
12.7.7 P	AACR1	Alternate channel rejection: f = |10 MHz|	PER ≤ 1%, PSDU length of 20 octets, P_RF = -82 dBm		48		dB
12.7.8 P	AACR2	2^nd Alternate channel rejection: f = |15 MHz|	PER ≤ 1%, PSDU length of 20 octets, P_RF = -82 dBm		54		dB
12.7.9 P	SPUR	Spurious emissions:LO leakage30 - ≤1000 MHz>1 - 12.75 GHz			-70		dBmdBmdBm
12.7.10 f	RXTXOFFS	TX/RX carrier frequency offset S	sensitivity loss < 2 dB	-300 (1)		+300	kHz
12.7.11 IIP3	3	^rd - order intercept point	At maximum gainOffset freq. interf. 1 = 5 MHzOffset freq. interf. 2 = 10 MHz		-10		dBm
12.7.12 IIP2	2	^nd - order intercept point	At maximum gainOffset freq. interf. 1 = 60 MHzOffset freq. interf. 2 = 62 MHz		31		dBm
12.7.13		RSSI tolerance	Tolerance within gain step			±5	dB
12.7.14		RSSI dynamic range			81		dB
12.7.15		RSSI resolution			3		dB
12.7.16		RSSI sensitivity	Defined as RSSI_BASE_VAL		-91		dBm
12.7.17		Minimum RSSI value	P_RF ≤ RSSI\_BASE\_VAL		0
12.7.18		Maximum RSSI value	P_RF > RSSI\_BASE\_VAL + 81 dB		28

Note: 1. Offset equals ±120 ppm.

12.8 Current Consumption Specifications

Test Conditions (unless otherwise stated): $$ V _ {D D} = 3. 0 V, f _ {R F} = 2. 4 5 \mathrm{GHz}, T _ {O P} = 2 5 ^ {\circ} \mathrm{C}, \text { Measurement setup see Figure 5 - 1 on page 12. } $$ Table 12-8. Current Consumption Specifications (1)

No. Symbol Parameter Condition Min. Typ. Max Units
12.8.1 I	BUSY_TX	Supply current transmit state P	_TX = 3 dBm P_TX = 0 dBm P_TX = -17 dBm		1411.67.4		mA mA mA
12.8.2 I	RX_ON	Supply current RX_ON state	RX_ON state - high input level		10.3		mA
12.8.3 I	RX_ON	Supply current RX_ON state	RX_ON state - high sensitivity		12.3		mA
12.8.4 I	PLL_ON_P	Supply current RX_ON state	RX_ON state, with register setting RX PDT_LEVEL > 0^(2)		11.8		mA
12.8.5 I	PLL_ON	Supply current PLL_ON state	PLL_ON state		5.6		mA
12.8.6 I	TRX_OFF	Supply current TRX_OFF state	TRX_OFF state		0.4		mA
12.8.7 I	SLEEP	Supply current SLEEP state	SLEEP state			0.02	μA

Note: 1. Current consumption for all operating modes is reduced at lower V DD 2. Refer to Section 9.1 "Receiver (RX)" on page 101

12.9 Crystal Parameter Requirements

Table 12-9. Crystal Parameter Requirements

No. Symbol Parameter		Condition	Min. Typ. Max	Units
12.9.1 f	0	Crystal frequency		16		MHz
12.9.2 C	L	Load capacitance		8	14	pF
12.9.3 C	0	Static capacitance			7	pF
12.9.4 R	1	Series resistance			100 Ω

13. Typical Characteristics

13.1 Active Supply Current

The following charts showing each a typical behavior of the AT86RF231. These figures are not tested during manufacturing. All power consumption measurements are performed with pin 17 (CLKM) disabled, unless otherwise stated. The measurement setup used for the measurements is shown in Figure 5-1 on page 12. Power consumption for the microcontroller required to program the radio transceiver is not included in the measurement results. The power consumption in SLEEP state mode is independent from CLKM master clock rate selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, and ambient temperature. The dominating factors are operating voltage and ambient temperature. If possible the measurement results are not affected by current drawn from I/O pins. Register, SRAM or Frame Buffer read or write accesses are not performed during current consumption measurements.

13.1.1 P\_ON and TRX\_OFF states

Figure 13-1. Current Consumption in P\_ON State  Figure 13-2. Current Consumption in TRX\_OFF State 

13.1.2 PLL\_ON state

Figure 13-3. Current Consumption in PLL\_ON State 

13.1.3 RX\_ON state

Figure 13-4. Current Consumption in RX\_ON State - High Sensitivity  Figure 13-5. Current Consumption in RX\_ON State - High Input Level  Figure 13-6. Current Consumption in RX\_ON State - Reduced Sensitivity 

13.1.4 TX\_BUSY state

Figure 13-7. Current Consumption in TX\_BUSY State - Minimum Output Power  Figure 13-8. Current Consumption in TX\_BUSY State - Output Power 0 dBm  Figure 13-9. Current Consumption in TX\_BUSY State - Maximum Output Power 

13.1.5 SLEEP

Figure 13-10. Current Consumption in SLEEP 

13.2 State Transition Timing

Figure 13-11. Transition Time from EVDD to P\_ON (CLKM available)  Figure 13-12. Transition Time from SLEEP to TRX\_OFF (IRQ\_4 (AWAKE\_END))  Figure 13-13. Transition Time from TRX\_OFF to PLL\_ON 

14. Register Summary

The AT86RF231 provides a register space of 64 8-bit registers, used to configure, control and monitor the radio transceiver. Note: All registers not mentioned within the following table are reserved for internal use and must not be overwritten. When writing to a register, any reserved bits shall be overwritten only with their reset value.

Addr Name	Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Page
0x00----	-	-
0x01	TRX_STATUS	CCA_DONE	CCA_STATUS	-	TRX_STATUS[4]	TRX_STATUS[3]	TRX_STATUS[2]	TRX_STATUS[1]	44,89,97
0x02	TRX_STATE	TRAC_STATUS[2]	TRAC_STATUS[1]	TRAC_STATUS[0]	TRX_CMD[4]	TRX_CMD[5]	TRX_CMD[2]	TRX_CMD[1]	33,44,89
0x03	TFX_CTRL_0	PAD_IO[1]	PAD_IO[0]	PAD_IO_CLKM[1]	PAD_IO_CLKM[0]	CLKM_SHA_SEL	CLKM_CTRL[2]	CLKM_CTRL[1]	6,115
0x04	TFX_CTRL_1	PA_EXT_EN	IRQ_2_EXT_EN	TX_AUTO_CRC_ON	RX_IL_CTRL	SPI_CMD_MODE[1]	SPI_CMD_MODE[0]	IRO_MASK_MODE	IRQ_POLARITY
0x05	PHY_TX_PWR	PA_BUF_L[1]	PA_BUF_L[0]	PA_L[1]	PA_L[0]	TX_PWR[3]	TX_PWR[2]	TX_PWR[1]	105
0x06	PHY_MSSI	RX_CRC_VALID	RND_VALUE[1]	RND_VALUE[0]	RSS[4]	RSS[3]	RSS[2]	RSS[1]	93,135
0x07	PHY_ED_LEVEL	ED_LEVEL[7]	ED_LEVEL[8]	ED_LEVEL[5]	ED_LEVEL[4]	ED_LEVEL[3]	ED_LEVEL[2]	ED_LEVEL[1]	93
0x08	PHY_CC_CCA	CCA_REQUEST	CCA_MODE[1]	CCA_MODE[0]	CHANNEL[4]	CHANNEL[3]	CHANNEL[2]	CHANNEL[1]	97
0x09	CCA_THRES	-	-	-	-	CCA_ED_THRES[3]	CCA_ED_THRES[2]	CCA_ED_THRES[1]	97
0x0A	RX_CTRL	-	-	-	-	POT_THRES[3]	POT_THRES[2]	POT_THRES[1]	140
0x0B	SFD VALUE	SFD VALUE[7]	SFD VALUE[6]	SFD VALUE[5]	SFD VALUE[4]	SFD VALUE[3]	SFD VALUE[2]	SFD VALUE[1]	153
0x0C	TRX_CTRL_2	RX_SAFE_MODE	-	-	-	-	-	DOPSK_DATA_RATE[1]	154
0x0D	ANT_DIV	ANT_SBL	-	-	-	ANT_DIV_EN	ANT_EXT_SW_EN	ANT_CTRL[1]	143
0x0E	IRQ_MASK	MASK_BAT_LOW	MASK_TRX_UR	MASK_AMI	MASK_CCA_ED_DOVE	MASK_TRX_END	MASK_TRX_START	MASK_PLL_UNLOCK	30
0x0F	IRQ_STATUS	BAT_LOW	TRX_UR	AMI	CCA_ED_DONE	TRX_END	RX_START	PLL_UNLOCK	30
0x10	VREG_CTRL	AVREG_EXT	AVDO_OK	-	-	DVREG_EXT	DVDO_OK	-	111
0x11	BATMON	-	-	BATMON_OK	BATMON_HI	BATMON_VTH[3]	BATMON_VTH[2]	BATMON_VTH[1]	113
0x12	XOSC_CTRL	XTAL_MODE[3]	XTAL_MODE[2]	XTAL_MODE[1]	XTAL_MODE[0]	XTAL_TRIM[3]	XTAL_TRIM[2]	XTAL_TRIM[1]	115
0x13----	-
0x14----	-
0x15	RX_SYN	RX_PDT_DIS	-	-	-	RX_PDT_LEVEL[3]	RX_PDT_LEVEL[2]	RX_PDT_LEVEL[1]	103
0x16----	-
0x17	XAH_CTRL_1	-	-	AACK_FLTR_RES_FT	AACK_UPLD_RES_FT	-	AACK_ACK_TIME	AACK_PROM_MODE	93,140
0x18	FTN_CTRL	FTN_START	-	-	-	-	-	-	125
0x19----	-
0x1A	PLL_OF	PLL_OF_START	-	-	-	-	-	-	122
0x1B	PLL_DCU	PLL_DCU_START	-	-	-	-	-	-	122
0x1C	PART_NUM	PART_NUM[7]	PART_NUM[6]	PART_NUM[5]	PART_NUM[4]	PART_NUM[3]	PART_NUM[2]	PART_NUM[1]	25
0x1D	VERSION_NUM	VERSION_NUM[7]	VERSION_NUM[6]	VERSION_NUM[5]	VERSION_NUM[4]	VERSION_NUM[3]	VERSION_NUM[2]	VERSION_NUM[1]	25
0x1E	MAN_ID_0	MAN_ID_0[7]	MAN_ID_0[6]	MAN_ID_0[5]	MAN_ID_0[4]	MAN_ID_0[3]	MAN_ID_0[2]	MAN_ID_0[1]	25
0x1F	MAN_ID_1	MAN_ID_1[7]	MAN_ID_1[6]	MAN_ID_1[5]	MAN_ID_1[4]	MAN_ID_1[3]	MAN_ID_1[2]	MAN_ID_1[1]	25
0x20	SHORT_ADDR_0	SHORT_ADDR_0[7]	SHORT_ADDR_0[6]	SHORT_ADDR_0[5]	SHORT_ADDR_0[4]	SHORT_ADDR_0[3]	SHORT_ADDR_0[2]	SHORT_ADDR_0[1]	78
0x21	SHORT_ADDR_1	SHORT_ADDR_1[7]	SHORT_ADDR_1[6]	SHORT_ADDR_1[5]	SHORT_ADDR_1[4]	SHORT_ADDR_1[3]	SHORT_ADDR_1[2]	SHORT_ADDR_1[1]	78
0x22	PAN_ID_0	PAN_ID_0[7]	PAN_ID_0[6]	PAN_ID_0[5]	PAN_ID_0[4]	PAN_ID_0[3]	PAN_ID_0[2]	PAN_ID_0[1]	76
0x23	PAN_ID_1	PAN_ID_1[7]	PAN_ID_1[6]	PAN_ID_1[5]	PAN_ID_1[4]	PAN_ID_1[3]	PAN_ID_1[2]	PAN_ID_1[1]	76
0x24	IEEE_ADDR_0	IEEE_ADDR_0[7]	IEEE_ADDR_0[6]	IEEE_ADDR_0[5]	IEEE_ADDR_0[4]	IEEE_ADDR_0[3]	IEEE_ADDR_0[2]	IEEE_ADDR_0[1]	76
0x25	IEEE_ADDR_1	IEEE_ADDR_1[7]	IEEE_ADDR_1[6]	IEEE_ADDR_1[5]	IEEE_ADDR_1[4]	IEEE_ADDR_1[3]	IEEE_ADDR_1[2]	IEEE_ADDR_1[1]	76
0x26	IEEE_ADDR_2	IEEE_ADDR_2[7]	IEEE_ADDR_2[6]	IEEE_ADDR_2[5]	IEEE_ADDR_2[4]	IEEE_ADDR_2[3]	IEEE_ADDR_2[2]	IEEE_ADDR_2[1]	76
0x27	IEEE_ADDR_3	IEEE_ADDR_3[7]	IEEE_ADDR_3[6]	IEEE_ADDR_3[5]	IEEE_ADDR_3[4]	IEEE_ADDR_3[3]	IEEE_ADDR_3[2]	IEEE_ADDR_3[1]	76
0x28	IEEE_ADDR_4	IEEE_ADDR_4[7]	IEEE_ADDR_4[6]	IEEE_ADDR_4[5]	IEEE_ADDR_4[4]	IEEE_ADDR_4[3]	IEEE_ADDR_4[2]	IEEE_ADDR_4[1]	76
0x29	IEEE_ADDR_5	IEEE_ADDR_5[7]	IEEE_ADDR_5[6]	IEEE_ADDR_5[5]	IEEE_ADDR_5[4]	IEEE_ADDR_5[3]	IEEE_ADDR_5[2]	IEEE_ADDR_5[1]	76
0x2A	IEEE_ADDR_6	IEEE_ADDR_6[7]	IEEE_ADDR_6[6]	IEEE_ADDR_6[5]	IEEE_ADDR_6[4]	IEEE_ADDR_6[3]	IEEE_ADDR_6[2]	IEEE_ADDR_6[1]	76
0x2B	IEEE_ADDR_7	IEEE_ADDR_7[7]	IEEE_ADDR_7[6]	IEEE_ADDR_7[5]	IEEE_ADDR_7[4]	IEEE_ADDR_7[3]	IEEE_ADDR_7[2]	IEEE_ADDR_7[1]	76
0x2C	XAH_CTRL_3	MAX_FRAME_RETRES[3]	MAX_FRAME_RETRES[2]	MAX_FRAME_RETRES[1]	MAX_FRAME_RETRES[0]	MAX_CSMA_RETRES[2]	MAX_CSMA_RETRES[1]	MAX_CSMA_RETRES[0]	SLOTTED_OPERATION

0x2D	CSMA_SEED_0	CSMA_SEED_0[7]	CSMA_SEED_0[8]	CSMA_SEED_0[9]	CSMA_SEED_0[4]	CSMA_SEED_0[3]	CSMA_SEED_0[2]	CSMA_SEED_0[1]	CSMA_SEED_0[0]	68
0x2E	CSMA_SEED_1	AACK_FVN_MODE[1]	AACK_FVN_MODE[0]	AACK_SET_PD	AACK_DIS_ACK	AACK_J_AM_COORD	CSMA_SEED_1[8]	CSMA_SEED_1[1]	CSMA_SEED_1[0]	68
0x2F	CSMA_BE	MAX_BC[3]	MAX_BC[2]	MAX_BC[1]	MAX_BC[0]	MIN_BC[3]	MIN_BC[2]	MIN_BC[1]	MIN_BC[0]	68
...	-	-	-	-	-	-	-	-	-

The reset values of the AT86RF231 registers in state P\_ON ^(1, 2, 3) are shown in Table 14-1 on page 170. Note: All reset values in Table 14-1 on page 170 are only valid after a power on reset. After a reset procedure (/RST = L) as described in Section 7.1.4.5 "Reset Procedure" on page 41 the reset values of selected registers (e.g. registers 0x01, 0x10, 0x11, 0x30) can differ from that in Table 14-1 on page 170. Table 14-1. Register Summary - Reset Values

Address	Reset Value
0x00	0x00
0x01	0x00
0x02	0x00
0x03	0x19
0x04	0x20
0x05	0xC0
0x06	0x00
0x07	0xFF
0x08	0x2B
0x09	0xC7
0x0A	0xB7
0x0B	0xA7
0x0C	0x00
0x0D	0x03
0x0E	0x00
0x0F	0x00

Address	Reset Value
0x10	0x00^(1)
0x11	0x02^(2)
0x12	0xF0
0x13	0x00
0x14	0x00
0x15	0x00
0x16	0x00
0x17	0x00
0x18	0x58
0x19	0x55
0x1A	0x57
0x1B	0x20
0x1C	0x03
0x1D	0x02
0x1E	0x1F
0x1F	0x00

Address	Reset Value
0x20	0xFF
0x21	0xFF
0x22	0xFF
0x23	0xFF
0x24	0x00
0x25	0x00
0x26	0x00
0x27	0x00
0x28	0x00
0x29	0x00
0x2A	0x00
0x2B	0x00
0x2C	0x38
0x2D	0xEA
0x2E	0x42
0x2F	0x53

Address	Reset Value
0x30	0x00^(3)
0x31	0x00
0x32	0x00
0x34	0x00
0x34	0x00
0x35	0x00
0x36	0x00
0x37	0x00
0x38	0x00
0x39	0x40
0x3A	0x00
0x3B	0x00
0x3C	0x00
0x3D	0x00
0x3E	0x00
0x3F	0x00

Notes: 1. While the reset value of register 0x10 is 0x00, any practical access to the register is only possible when DVREG is active. So this register is normally always read out as 0x04. For details refer to Section 9.4 "Voltage Regulators (AVREG, DVREG)" on page 110. 2. While the reset value of register 0x11 is 0x02, any practical access to the register is only possible when BATMON is activated. So this register is normally always read out as 0x22 in P\_ON state. For details refer to Section 9.5 "Battery Monitor (BATMON)" on page 113. 3. While the reset value of register 0x30 is 0x00, any practical access to the register is only possible when the radio transceiver is accessible. So the register is normally read out as: a) 0x11 after a reset in P\_ON state b) 0x07 after a reset in any other state

15. Abbreviations

AACK - Automatic acknowledgement ACK - Acknowledgement ADC - Analog-to-digital converter AD - Antenna diversity AGC - Automated gain control AES - Advanced encryption standard ARET - Automatic retransmission AVREG - Voltage regulator for analog building blocks AWGN - Additive White Gaussian Noise BATMON - Battery monitor BBP - Base band processor BPF - Band pass filter CBC - Cipher block chaining CRC - Cyclic redundancy check CCA - Clear channel assessment CSMA-CA - Carrier sense multiple access/Collision avoidance CW - Continuous wave DFBP - Dynamic Frame Buffer Protection DVREG - Voltage regulator for digital building blocks ECB - Electronic code book ED - Energy detection ESD - Electrostatic discharge EVM - Error vector magnitude FCF - Frame control field FCS - Frame check sequence FIFO - First in first out FTN - Filter tuning network GPIO - General purpose input output ISM - Industrial, scientific, and medical LDO - Low-drop output LNA - Low-noise amplifier LO - Local oscillator LQI - Link quality indicator LSB - Least significant bit MAC - Medium access control MFR - MAC footer MHR - MAC header MISO - SPI Interface: Master input slave output MOSI - SPI Interface: Master output slave input MSB - Most significant bit MSDU - MAC service data unit MPDU - MAC protocol data unit MSK - Minimum shift keying O-QPSK - Offset - quadrature phase shift keying PA - Power amplifier PAN - Personal area network PCB - Printed circuit board PER - Packet error rate PHR - PHY header PHY - Physical layer PLL - Phase locked loop POR - Power-on reset PPF - Poly-phase filter PRBS - Pseudo random bit sequence PSDU - PHY service data unit PSD - Power spectral mask QFN - Quad flat no-lead package RF - Radio frequency RSSI - Received signal strength indicator RX - Receiver SCLK - SPI Interface: SPI clock /SEL - SPI Interface: SPI select SFD - Start-of-frame delimiter SHR - Synchronization header SPI - Serial peripheral interface SRAM - Static random access memory SSBF - Single side band filter TX - Transmitter VCO - Voltage controlled oscillator VREG - Voltage regulator XOSC - Crystal oscillator

16. Ordering Information

Ordering Code Package Voltage Range Temperature Range
AT86RF231-ZU QN	1.8V - 3.6V Industrial (-40°C to +85°C) Lead-free/Halogen-free
AT86RF231-ZF QN	1.8V - 3.6V Industrial (-40°C to +125°C) Lead-free/Halogen-free

Package Type Description
QN 32QN2, 32 lead	5.0x5.0 mm Body, 0.50 mm Pitch, Quad Flat No-lead Package (QFN) Sawn

Note: T&R quantity 5,000. Please contact your local Atmel sales office for more detailed ordering information and minimum quantities.

17. Soldering Information

Recommended soldering profile is specified in IPC/JEDEC J-STD-.020C.

18. Package Thermal Properties

Thermal Resistance
Velocity [m/s] Theta ja [K/W]
0	40.9
1	35.7
2.5	32.0

19. Package Drawing - 32QN2


D E Pin 1 Corner

Top View 

A A3 A2 A1

Side View 

Pin 1 Corner D2 E2 + e L b

Bottom View COMMON DIMENSIONS (Unit of Measure = mm)

SYMBOL	MIN	NOM	MAX	NOTE
D	5.00 BSC
E	5.00 BSC
D2	3.20 3.30	3.40
E2	3.20	3.30	3.40
A	0.80	0.90	1.00
A1	0.0	0.02	0.05
A2	0.0	0.65	1.00
A3	0.20 REF
L	0.30 0.40 0.50
e	0.50 BSC
b	0.18	0.23	0.30	2

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-220, Variation VHHD-6, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 11/26/07

Package Drawing Contact:[e-mail]

TITLE32QN2, 32-lead 5.0 x 5.0 mm Body, 0.50 mm Pitch,Quad Flat No Lead Package (QFN) Sawn

DRAWING NO.GREV.32QN2ZJZA

20. Appendix A - Continuous Transmission Test Mode

20.1 Overview

The AT86RF231 offers a Continuous Transmission Test Mode to support final application / production tests as well as certification tests. Using this test mode the radio transceiver transmits continuously a previously transferred frame (PRBS mode) or a continuous wave signal (CW mode). In CW mode two different signal frequencies per channel can be transmitted: - f_1 = f_CH + 0.5 MHz - f_2 = f_CH - 0.5 MHz Here f_CH is the channel center frequency programmed by register 0x08 (PHY\_CC\_CCA). Note, in CW mode it is not possible to transmit an RF signal directly on the channel center frequency. PSDU data in the Frame Buffer must contain at least a valid PHR (see Section 8.1 "Introduction - IEEE 802.15.4 - 2006 Frame Format" on page 79) followed by PSDU data. It is recommended to use a frame of maximum length (127 bytes) and arbitrary PSDU data for the PRBS mode. The SHR and the PHR are not transmitted. The transmission starts with the PSDU data and is repeated continuously.

20.2 Configuration

Before enabling Continuous Transmission Test Mode all register configurations shall be done as follow: • TX channel setting (optional) • TX output power setting (optional) - Mode selection (PRBS / CW) A register access to register 0x36 and 0x1C enables the Continuous Transmission Test Mode. The transmission is started by enabling the PLL (TRX\_CMD = PLL\_ON) and writing the TX\_START command to register 0x02. Even for CW signal transmission it is required to write valid PSDU data to the Frame Buffer. For PRBS mode it is recommended to write a frame of maximum length. The detailed programming sequence is shown in Table 20-1 on page 175. The column R/W informs about writing (W) or reading (R) a register or the Frame Buffer. Table 20-1. Continuous Transmission Programming Sequence.

Step	Action Register R/W	Value Description
1	RESET Reset AT86RF231
2	Register Access 0X0E	W 0x01 Set IRQ mask register, enable IRQ_0 (PLL_LOCK)
3	Register Access	0x04	W 0x00 Disable TX_AUTO_CRC_ON
4	Register Access	0x02	W 0x03 Set radio transceiver state TRX_OFF
5	Register Access	0x03	W 0x01 Set clock at pin 17 (CLKM)
6	Register Access	0x08	W 0x33 Set IEEE 802.15.4 CHANNEL, e.g. 19
7	Register Access	0x05	W 0x00 Set TX output power, e.g. to Pmax

8 Register Access 0x01 R	0x08 Verify	TRX_OFF state
9 Register Access 0x036	W 0x0F Enable Continuous Transmission Test Mode - step # 1
10^(1)	Register Access 0x0C W 0x03 Enable High Data Rate Mode, 2 Mb/s
11^(1)	Register Access 0x0A W 0xA7 Configure High Data Rate Mode
12^(2)	Frame BufferWrite Access	W Write PHR and PSDU data (even for CW mode), refer to Table 20-2 on page 176.
13	Register Access	0x1C	W 0x54 Enable Continuous Transmission Test Mode - step # 2
14	Register Access	0x1C	W 0x46 Enable Continuous Transmission Test Mode - step # 3
15	Register Access 0x02 W 0x09 Enable PLL_ON state
16	Interrupt event	0x0F	R 0x01 Wait for IRQ_0 (PLL_LOCK)
17	Register Access	0x02	W 0x02 Initiate Transmission, enter BUSY_TX state
18	Measurement
19	Register Access	0x1C	W 0x00 Disable Continuous Transmission Test Mode
20	RESET

Note: 1. Only required for CW mode, do not configure for PRBS mode. 2. Frame Buffer content depends on desired transmitter operation mode, either PRBS or CW mode. The content of the Frame Buffer has to be defined for Continuous Transmission PRBS mode or CW mode. To measure the power spectral density (PSD) mask of the transmitter it is recommended to use a random sequence of maximum length for the PSDU data. To measure CW signals it is necessary to write either 0x00 or 0xFF to the Frame Buffer, for details refer to Table 20-2 on page 176. Table 20-2. Frame Buffer Content for various Continuous Transmission Modulation Schemes

Step	Action	Frame Content	Comment
12	Frame Buffer Access	Random Sequence	modulated RF signal
		0x00 (each byte)	f_CH - 0.5 MHz, CW signal
		0xFF (each byte)	f_CH + 0.5 MHz, CW signal

20.3 Register Description

Register 0x36 (TST\_CTRL\_DIGI): Register TST\_CTRL\_DIG enables the continuous transmission test mode. 

B i t 7 6 5 4 3 2 1 +0x36 Reserved TST_CTRL_DIG TST_CTRL_DIGI Read/Write R/W R/W R/W R/W R/W R/W R/W R e s e t V a l u e C

- Bit [7:4] - Reserved - Bit [3:0] - TST\_CTRL\_DIG These register bits enable continuous transmission: Table 20-3. Continuous Transmission

Register Bit	Value	Description
TST_CTRL_DIG	0x0	Continuous Transmission disabled
	0xF	Continuous Transmission enabled
	0x1 - 0xE	Reserved

21. Appendix B - AT86RF231-ZF Extended Temperature Range

21.1 Introduction

Appendix B contains information specific to devices operating at temperatures up to 125°C. Only deviations to the standard device AT86RF231-ZU are covered in this appendix, all other information are similar to previous sections. Performance figures for 125°C are only valid for device part number AT86RF231-ZF.

21.2 Electrical Characteristics

If not otherwise stated, electrical characteristics for typical operating conditions are similar to figures provided in “Electrical Characteristics” on page 156. Table 21-1. Recommended Operating Range

No. Symbol Parameter Condition Min. Typ. Max Units
21.2.1 T	OP	Operating temperature range -40 +1	25 °C

21.3 Typical Characteristics

The following charts showing each a typical behavior of the AT86RF231. These figures are not tested during manufacturing for all supply voltages and all temperatures. All power consumption measurements are performed with pin 17 (CLKM) disabled, unless otherwise stated. Power consumption for the microcontroller required to program the radio transceiver is not included in the measurement results. The power consumption in SLEEP state mode is independent from CLKM master clock rate selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, and ambient temperature. The dominating factors are operating voltage and ambient temperature. If possible the measurement results are not affected by current drawn from I/O pins. Register, SRAM or Frame Buffer read or write accesses are not performed during current consumption measurements.

21.4 Active Supply Current

21.4.1 P\_ON and TRX\_OFF states

Figure 21-1. Current Consumption in P\_ON State  Figure 21-2. Current Consumption in TRX\_OFF State 

21.4.2 PLL\_ON state

Figure 21-3. Current Consumption in PLL\_ON State 

21.4.3 RX\_ON state

Figure 21-4. Current Consumption in RX\_ON State - High Sensitivity  Figure 21-5. Current Consumption in RX\_ON State - High Input Level  Figure 21-6. Current Consumption in RX\_ON State - Reduced Sensitivity 

21.4.4 TX\_BUSY state

Figure 21-7. Current Consumption in TX\_BUSY State - Minimum Output Power  Figure 21-8. Current Consumption in TX\_BUSY State - Output Power 0 dBm  Figure 21-9. Current Consumption in TX\_BUSY State - Maximum Output Power 

21.4.5 SLEEP

Figure 21-10. Current Consumption in SLEEP 

21.5 State Transition Timing

Figure 21-11. Transition Time from EVDD to P\_ON (CLKM available)  Figure 21-12. Transition Time from SLEEP to TRX\_OFF (IRQ\_4 (AWAKE\_END))  Figure 21-13. Transition Time from TRX\_OFF to PLL\_ON 

21.6 Receiver Performance

21.6.1 Sensitivity

Figure 21-14. Sensitivity 

21.6.2 Adjacent & Alternate Channel Selectivity (ACRx)

Figure 21-15. Adjacent and Alternate Channel Selectivity 

21.6.3 RSSI

Figure 21-16. RSSI 

21.7 Transmitter Performance

21.7.1 TX Output Power vs. TX Power Level

Figure 21-17. TX Output Power vs. TX\_PWR (EVDD = 3.0V, CH=19) 

21.7.2 TX Output Power vs. EVDD

Figure 21-18. TX Output Power vs. EVDD (TX\_PWR = 0, CH=19) 

21.7.3 TX Output Power vs. Channel

Figure 21-19. TX Output Power vs. Channel (EVDD = 3.0V, TX\_PWR = 0) 

21.7.4 TX EVM vs. EVDD

Figure 21-20. Error Vector Magnitude (EVM) vs. EVDD (TX\_PWR = 0, CH=19) 

22. Appendix C - Errata

22.1 AT86RF231 Rev.A

No known errata

23. Revision history

23.1 Rev.8111C - 09/09

1. Updated the datasheet with a new device AT86RF231-ZF. 2. Added "Appendix B - AT86RF231-ZF Extended Temperature Range" on page 178 3. Editorial updates.

23.2 Rev.8111B - 02/09

1. Updated figures and graphics in sections: 5.,6., 8.,9.,11., 12.and 13. 2. Changed register and sub-register names in "AT86RF231 Extended Feature Set" on page 128. 3. Editorial changes.

23.3 Rev.8111A - 05/08

1. Initial revision

References

[1]	IEEE Std 802.15.4TM-2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs)
[2]	IEEE Std 802.15.4TM-2003: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs)
[3]	ANSI / ESD-STM5.1-2001: ESD Association Standard Test Method for electrostatic discharge sensitivity testing - Human Body Model (HBM).
[4]	ESD-STM5.3.1-1999: ESD Association Standard Test Method for electrostatic discharge sensitivity testing - Charged Device Model (CDM).
[5]	NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/NIST, November 26, 2001
[6] AT	86RF231 Software Programming Model

Table of Contents

Features 1

1 Pin-out Diagram 2

1.1 Pin Descriptions ....3 1.2 Analog and RF Pins ....5 1.3 Digital Pins ....7

2 Disclaimer 9

3 Overview 9

4 General Circuit Description 10

5 Application Circuits 12

5.1 Basic Application Schematic 12 5.2 Extended Feature Set Application Schematic 14

6 Microcontroller Interface 16

6.1 SPI Timing Description ....17 6.2 SPI Protocol ....19 6.3 Radio Transceiver Status information 24 6.4 Radio Transceiver Identification 25 6.5 Sleep/Wake-up and Transmit Signal (SLP\_TR) 27 6.6 Interrupt Logic ......29

7 Operating Modes 33

7.1 Basic Operating Mode ....33 7.2 Extended Operating Mode ....47

8 Functional Description 79

8.1 Introduction - IEEE 802.15.4 - 2006 Frame Format ....79 8.2 Frame Check Sequence (FCS) 85 8.3 Received Signal Strength Indicator (RSSI) 89 8.4 Energy Detection (ED) 91 8.5 Clear Channel Assessment (CCA) 94 8.6 Link Quality Indication (LQI) 99

9 Module Description 101

9.1 Receiver (RX) 101 9.2 Transmitter (TX) 104 9.3 Frame Buffer 107 9.4 Voltage Regulators (AVREG, DVREG) 110 9.5 Battery Monitor (BATMON) 113 9.6 Crystal Oscillator (XOSC) 116 9.7 Frequency Synthesizer (PLL) 121 9.8 Automatic Filter Tuning (FTN) 125

10 Radio Transceiver Usage 126

10.1 Frame Receive Procedure ....126 10.2 Frame Transmit Procedure ....127

11 AT86RF231 Extended Feature Set 128

11.1 Security Module (AES) 128 11.2 Random Number Generator ....136 11.3 High Data Rate Modes ....137 11.4 Antenna Diversity ....142 11.5 RX/TX Indicator 147 11.6 RX Frame Time Stamping 150 11.7 Frame Buffer Empty Indicator ....152 11.8 Dynamic Frame Buffer Protection ....154 11.9 Configurable Start-Of-Frame Delimiter ..... 155

12 Electrical Characteristics 156

12.1 Absolute Maximum Ratings ....156 12.2 Recommended Operating Range ....156 12.3 Digital Pin Characteristics ....157 12.4 Digital Interface Timing Characteristics .....157 12.5 General RF Specifications ....158 12.6 Transmitter Characteristics ....159 12.7 Receiver Characteristics ....160 12.8 Current Consumption Specifications ....161 12.9 Crystal Parameter Requirements ....161

13 Typical Characteristics 162

13.1 Active Supply Current 162 13.2 State Transition Timing ....167

14 Register Summary 169

15 Abbreviations .... 171

16 Ordering Information 173 17 Soldering Information 173 18 Package Thermal Properties 173 19 Package Drawing - 32QN2 174 20 Appendix A - Continuous Transmission Test Mode 175 20.1 Overview 175 20.2 Configuration 175 20.3 Register Description ......177 21 Appendix B - AT86RF231-ZF Extended Temperature Range ..... 178 21.1 Introduction 178 21.2 Electrical Characteristics ......178 21.3 Typical Characteristics ....179 21.4 Active Supply Current 179 21.5 State Transition Timing ....185 21.6 Receiver Performance ......187 21.7 Transmitter Performance ......189 22 Appendix C - Errata 192 22.1 AT86RF231 Rev.A 192 23 Revision history 193 23.1 Rev.8111C - 09/09 ......193 23.2 Rev.8111B - 02/09 ...... 193 23.3 Rev.8111A - 05/08 ...... 193 References.... 194 Table of Contents...... i

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