SY89833AL - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY89833AL Microchip

3.3V Low-Noise, Ultra-Precision 1:4 LVDS

Fanout Buffer/Translator with Internal Termination

Features

• Ultra-Low Jitter Design:
• 8 0 f _RMS Additive Phase Jitter (typical)
• Guaranteed AC Performance Over Temperature and Voltage:
• DC-to > 2 GHz throughput
• <470 ps Propagation Delay (IN-to-Q)
• <20 ps Within-Device Skew
• <190 ps Rise/Fall Times
• Unique Input Termination and V_T Pin Accepts DC- and AC-Coupled Inputs
  • High-Speed LVDS Outputs
  • 3.3V Power Supply Operation
• Industrial Temperature Range: -40^ to +85^
  • Available in 16-Pin (3 mm × 3 mm) QFN Package

Applications

• Processor Clock Distribution
  • SONET Clock Distribution
  • Fibre Channel Clock Distribution
  • Gigabit Ethernet Clock Distribution

General Description

The SY89833AL is a lower noise version of the SY89833L 3.3V, high-speed 2 GHz differential, low voltage differential swing (LVDS) 1:4 fanout buffer optimized for ultra-low skew applications. Within device skew is guaranteed to be less than 20 ps over supply voltage and temperature.

The differential input buffer has a unique internal termination design that allows access to the termination network through a V_T pin. This feature allows the device to easily interface to different logic standards. A _REF-AC reference is included for AC-coupled applications.

The SY89833AL is part of Microchip's high-speed clock synchronization family. For 2.5V applications, the SY89832U provides similar functionality while operating from a 2.5V ±5% supply. For applications that require a different I/O combination, consult the Microchip website and choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators, and clock generators.

Package Type

SY89833AL 3x3 QFN (M) /Q0 Q0 VCC GND 13141516 Q1 1 12 IN /Q1 2 11 VT Q2 3 10 VREF-AC /Q2 4 9 /IN 5 6 7 8 Q3 /Q3 VCC EN

Functional Block Diagram

IN 50Ω VT 50Ω /IN VREF-AC EN (LVTTL/CMOS) D Q 1:4 Q0 /Q0 Q1 /Q1 Q2 /Q2 Q3 /Q3

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Supply Voltage ( V_CC )....-0.5V to +4.0V
Input Voltage ( V_IN ) -0.5V to V_CC + 0.3V
LVDS Output Current ( I_OUT )....+10 mA
Input Current Source or Sink Current on (IN, /IN)....±50 mA
V_T Current Source or Sink Current on (V_T) ..... ±100 mA
V_REF-AC Current Source or Sink Current on ( V_REF-AC )....±2 mA

Operating Ratings ‡

Supply Voltage Range ....+3.0V to +3.6V

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability.

‡ Notice: The device is not guaranteed to function outside its operating ratings.

TABLE 1-1: ELECTRICAL CHARACTERISTICS

Electrical Characteristics: T_A = -40°C to +85°C, unless otherwise stated. (Note 1).
Symbol	Parameters Min. Typ. Max. Units Conditions
V_CC	Power Supply Voltage Range 3.0 3.3	3.6 V —
I_CC	Power Supply Current — 75 100 mA	No load; max.	V			CC
R_IN	Input Resistance (IN-to- V_T )	45	50	55	Ω	—
R_DIFF-IN	Differential Input Resistance (IN-to-/IN)	90	100	110	Ω	—
V_IH	Input High Voltage (IN-to-/IN)	1.2	—	V_CC	V	—
V_IL	Input Low Voltage (IN-to-/IN)	0	—	V_IH-0.1	V	—
V_IN	Input Voltage Swing (IN-to-/IN)	0.1	—	1.7	V	See Figure 5-3
V_DIFF\_IN	Differential Input Voltage	0.2	—	—	V	See Figure 5-4
|I_IN|	Input Current (IN, /IN)	—	—	45	mA	Note 2
V_REF-AC	Reference Voltage	V_CC-1.525	V_CC-1.425	V_CC-1.325	V	—

Note 1: The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
2: Due to the internal termination (see "Input Buffer Structure" section) the input current depends on the applied voltages at IN, /IN, and V_T inputs. Do not apply a combination of voltages that causes the input current to exceed the maximum limit.

TABLE 1-2: LVDS OUTPUTS DC ELECTRICAL CHARACTERISTICS

Electrical Characteristics: V_CC = 3.3V ± 10% , R_L = 100 across the outputs; T_A = -40^ to +85°C. (Note 1)
Symbol P	Parameters Min. Typ. Max. Units	Conditions
V_OUT	Output Voltage Swing	250	325	—	mV	see Figure 5-3
V_DIFF\_OUT	Differential Output Voltage Swing	500	650	—	mV	see Figure 5-4
V_OCM	Output Common-Mode Voltage	1.125	—	1.275	V	—
V_OCM	Change in Common-Mode Voltage	-50	—	50	mV	—

Note 1: The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

TABLE 1-3: LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS

Electrical Characteristics: V_CC = 3.3V ± 10% , T_A = -40°C to +85°C . (Note 1)
Symbol	Parameters Min. Typ. Max. Units Conditions
V_IH	Input High Voltage	2.0	—	V_CC	V	—
V_IL	Input Low Voltage	0	—	0.8 V	—
I_IH	Input High Current	-125	—	30	μA	—
I_IL	Input Low Current	-300	—	μA	—

Note 1: The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

TABLE 1-4: AC ELECTRICAL CHARACTERISTICS

Electrical Characteristics: V_CC = 3.3V ± 10% , R_L = 100 across the outputs; T_A = -40°C to +85°C unless otherwise stated. (Note 1)
Symbol	Parameters Min. Typ. Max. Units Conditions
f_MAX	Maximum Frequency 2.0 — — GHz V					OUT ≥ 200 mV
t_pd	Propagation Delay	250	—	470	ps	—
t_SKEW	Within-Device Skew	—	5	20	ps	Note 2
	Part-to-Part Skew	—	—	200	ps	Note 3
t_S	Set-Up Time	400	—	—	ps	Note 4
t_H	Hold Time	400	—	—	ps	Note 4
t_JITTER	Additive Phase Jitter, RMS	—	80	—	fs	622.08 MHz @ 3.3V, Integration range: 12 kHz to 20 MHz
t_r/t_f	Output Rise/Fall Times (20% to 80%)	60	110	190	ps	At Full Output Swing
—	Duty Cycle	47	—	53	%	Differential I/O

Note 1: High-frequency AC parameters are guaranteed by design and characterization.
2: Within device skew is measured between two different outputs under identical input transitions.
3: Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs.
4: Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold times do not apply.

TEMPERATURE SPECIFICATIONS

Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Junction Operating Temperature T	J	— —	+125 °C Note 1
Storage Temperature Range T	S	-65 —	+150 °C —
Lead Temperature	— —	— +260 °C Soldering, 20s
Ambient Temperature	TA	-40 —	+85 °C —
Package Thermal Resistances (Note 2)
16-pin 3 mm x 3 mm QFN (Still-Air)	_JA	—	60	—	°C/W	—
16-pin 3 mm x 3 mm QFN	_JB	—	33	—	°C/W	—

Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., T_A , T_J , _JA ). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability.
2: Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB and _JA values are determined for a 4-layer board in still-air number, unless otherwise stated.

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

V_CC = 3.3V , GND = 0V, V_IN = 400 mV, R_L = 100 across the outputs; T_A = +25^ unless otherwise stated.

FIGURE 2-1: Output Swing vs. Frequency.

FIGURE 2-4: 1.5 GHz Output.

FIGURE 2-2: Propagation Delay vs. Input Voltage Swing.

FIGURE 2-5: 2 GHz Output.

FIGURE 2-3: 500 MHz Output.

FIGURE 2-6: Typical Additive Phase Jitter.

EN VCC/2 VCC/2 IN IN tS tH VIN /Q tpd tpd Q VOUT

FIGURE 2-7: Timing Diagram.

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

Pin Number Pin Name Description
15, 161, 23, 45, 6	Q0, /Q0Q1, /Q1Q2, /Q2Q3, /Q3	LVDS Differential Outputs: Normally terminated with 100 across the pair (Q, /Q).See the LVDS Outputs section, Figure 5-1. Unused outputs should be terminated with a 100 resistor across each pair.
8	EN	This single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The synchronous enable ensures that enable/disable will only occur when the outputs are in a logic low state. Note that this input is internally connected to a 25 k pull-up resistor and will default to logic high state (enabled) if left open.
9, 12 /IN, IN	Differential	Input: This input pair is the differential signal input to the device. Input accepts AC- or DC-Coupled differential signals as small as 100 mV . Each pin of the pair internally terminates to a V_T pin through 50 . Note that this input will default to an intermediate state if left open. Please refer to the Input Interface Applications section for more details.
10	V_REF-AC	Reference Voltage: These outputs bias to V_CC-1.425V .They are used when AC coupling the inputs (IN, /IN). For AC-coupled applications, connect V_REF-AC to V_T pin and bypass with 0.01 low-ESR capacitor to V_CC . See the Input Interface Applications section for more details. Maximum sink/source current is ± 1.5 mA .
11	V_T	Input Termination Center-Tap: Each side of the differential input pair terminates to a V_T pin. The V_T pin provides a center-tap to a termination network for maximum interface flexibility. See the Input Interface Applications section for more details.
13 GND Ground. GND		pin and exposed pad must be connected to the most negative potential of the device ground.
7, 14	V_CC	Positive Power Supply: Bypass with 0.1 //0.01 low-ESR capacitors and place as close as possible to each V_CC pin.

TABLE 3-2: TRUTH TABLE

IN	/IN	EN	Q	/Q
0	1	1	0	1
1	0	1	1	0
X	X	0	0 (Note 1)	1 (Note 1)

Note 1: On next negative transition of the input signal (IN).

4.0 INPUT INFORMATION

4.1 Input Stage

VCC IN 50Ω VT 50Ω /IN SY89833AL

FIGURE 4-1: Simplified Differential Input Buffer.

4.2 Input Interface Applications

Vcc = 3.3V V CC = 3.3V CML IN /IN SY89833AL NC □ VT NC □ VREF-AC

FIGURE 4-2: DC-Coupled CML Input Interface (Option: May Connect V_T to V_CC ).

Vcc = 3.3V V CML IN /IN SY89833AL VT VREF-AC 0.01μF Vcc cc = 3.3V

FIGURE 4-3: AC-Coupled CML Input Interface.

Vcc = 3.3V V CC = 3.3V LVPECL IN /IN 0.01μF Vcc -2V VT 50Ω NC VREF-AC SY89833AL

FIGURE 4-4: DC-Coupled LVPECL Input Interface.

Vcc = 3.3V LVPECL Rpd 100Ω Rpd 100Ω 0.01μF Vcc = 3.3V IN /IN SY89833AL VT VREF-AC Vcc

FIGURE 4-5: AC-Coupled LVPECL Input Interface.

Vcc = 3.3V V LVDS IN /IN SY89833AL NC □ VT NC □ VREF-AC cc = 3.3V

FIGURE 4-6: LVDS Input Interface.

5.0 LVDS OUTPUTS

LVDS specifies a small swing of 325 mV typical, on a nominal 1.20V common-mode above ground. The common-mode voltage has tight limits to permit large variations in ground noise between a LVDS driver and receiver.

VOUT 100Ω VOH, VOL VOH, VOL GND

FIGURE 5-1: LVDS Differential Measurement.

50Ω 50Ω V_OCM' ΔV_OCM GND

FIGURE 5-2: LVDS Common-Mode Measurement.

VOUT, VIN 325mV (TYPICAL)

FIGURE 5-3: Single-Ended Swing.

650mV V_DIFF_IN V_DIFF_OUT

FIGURE 5-4: Differential Swing.

6.0 PACKAGING INFORMATION

16-Lead QFN 3 mm x 3 mm Package Outline

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

TITLE

16 LEAD QFN 3x3mm PACKAGE OUTLINE & RECOMMENDED LAND PATTERN

DRAWING # QFN33-16LD-PL-1 UNIT MM

PIN 1 DOT BY MARKING 3.0000±0.050 1 2 3.0000±0.050

TOP VIEW NOTE 1, 2, 3

PIN #1 IDENTIFICATION CHAMFER 0.300 X 45° 1.5500±0.050 Exp.DAP 0.5000 BSC 0.2300±0.050 1.5000 Ref. 1.5500±0.050 Exp.DAP 1 2 4000±0.050

BOTTOM VIEW NOTE 1, 2, 3

0.850±0.050 0.000-0.050 0.2030±0.025

SIDE VIEW NOTE: 1, 2, 3

NOTE:

1. MAX PACKAGE WARPAGE IS 0.05 MM
2. MAX ALLOWABLE BURR [S 0.076 MM IN ALL DIRECTIONS
3. PIN #1 IS ON TOP WILL BE LASER MARKED
4. RED CIRCLE IN LAND PATTERN INDICATE THERMAL VIA. SIZE SHOULD BE 0.30-0.35 MM
   IN DIAMETER AND SHOULD BE CONNECTED TO GND FOR MAX THERMAL PERFORMANCE
5. GREEN RECTANGLES (SHADED AREA) indicate SOLDER STENCIL OPENING ON EXPOSED
   PAD AREA. SIZE SHOULD BE 0.60×0.60 MM IN SIZE, 0.20 MM SPACING.

16-Lead QFN 3 mm x 3 mm Recommended Land Pattern

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

POD-Land Pattern drawing # QFN33-16LD-PL-1

RECOMMENDED LAND PATTERN NOTE: 4, 5

Symmetrical geometric pattern with green diagonal hatching and a central crosshair (no text or symbols)

STACKED-UP

0.48±0.02 0.80±0.02 0.23±0.02 1.60±0.02 2.24±0.02 3.20±0.02 0.50 BSC 1.60±0.02 2.24±0.02 3.20±0.02 EXPOSED METAL TRACE

0.70±0.02 0.40±0.02 0.10±0.02 0.23±0.02 1.40±0.02 2.24±0.02 3.04±0.02 SOLDER STENCIL OPENING

APPENDIX A: REVISION HISTORY

Revision A (January 2018)

• Converted Micrel document SY89833AL to Microchip data sheet DS20005608A.
• Minor text changes throughout.
• Updated Figure 2-6.

NOTES:

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.

PART NO. Device Voltage Option Package Temperature Special Processing X X X — XX

Device: SY89833A: 3.3V Low-Noise, Ultra-Precision 1:4 LVDS

Fanout Buffer/Translator with Internal Termination

Voltage Option: L = 3.3V Only

Package: M = 16-Pin 3 mm x 3 mm QFN

Temperature: G = -40°C to +85°C

Special Blank = Bulk, 100 pcs.

Processing: TR = Tape and Reel, 1000/Reel

Note 1: Contact factory for die availability. Dice are guaranteed at T_A = 25^ , DC Electricals only.

Examples:

a) SY89833ALMG: 3.3V Low-Noise, Ultra-Pre-

cision 1:4 LVDS Fanout

Buffer/Translator with Inter-

nal Termination, 3.3V Volt-

age Option, -40^ to +85^

Temp. Range, 16-Pin QFN,

100 pcs.

b) SY89833ALMG-TR: 3.3V Low-Noise, Ultra-Pre-

cision 1:4 LVDS Fanout

Buffer/Translator with Inter-

nal Termination, 3.3V Volt-

age Option, -40^ to +85^

Temp. Range, 16-Pin QFN,

1000/Reel

NOTES:

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