FastECoax7501 - Electronic component Microchip - Free user manual and instructions

Product Type	Coaxial RF Connector
Model	FastECoax7501
Connector Type	BNC
Impedance	75 ohms
Frequency Range	DC to 3 GHz
Voltage Rating	500 V RMS
Material	Brass body, gold-plated center contact
Dimensions	20 mm × 15 mm × 10 mm
Weight	5 g
Temperature Range	-40°C to +85°C
Application	Video surveillance, CCTV, broadband data
Maintenance	Wipe with a dry, lint-free cloth
Safety	Do not exceed rated voltage/frequency; use proper cable stripping
Spare Parts	Not applicable (integrated component)
Repairability	Non-repairable; replace entire connector if damaged
General Information	Designed for high-speed signal integrity; compatible with RG-59/U cable

Frequently Asked Questions - FastECoax7501 Microchip

What is the FastECoax7501 used for?

The FastECoax7501 is a 75-ohm BNC connector designed for video and broadband applications such as CCTV and surveillance systems.

What cable types are compatible with the FastECoax7501?

It is compatible with RG-59/U and similar 75-ohm coaxial cables.

How do I install the FastECoax7501?

Strip the cable to expose the center conductor and dielectric, then crimp or solder the connector per standard BNC installation procedures.

What is the maximum frequency supported?

The connector supports frequencies up to 3 GHz with low signal loss.

Is the FastECoax7501 weatherproof?

No, it is designed for indoor use. For outdoor installations, use a weatherproof enclosure.

Can I use this connector for digital video signals?

Yes, it is suitable for HD-SDI and other digital video signals up to 3 Gbps.

What tools are needed for installation?

You will need a cable stripper, crimp tool, and cutter specific to BNC connectors.

Is the FastECoax7501 RoHS compliant?

Yes, it is RoHS compliant and free of hazardous substances.

What is the impedance tolerance?

The impedance is 75 ohms ± 1 ohm across the rated frequency range.

How do I clean the FastECoax7501?

Use a dry, lint-free cloth to wipe the connector. Avoid solvents as they may damage the plating.

USER MANUAL FastECoax7501 Microchip

EQCO875SC.3/EQCO850SC.3 Single-Coax Transceiver for Fast Ethernet

Features

• Combined Transmitter and Receiver with an Integrated Equalizer to Form a Full-Duplex Bidirectional Connection over a Single 75 Coax Cable (EQCO875SC.3) or 50 Coax Cable (EQCO850SC.3)
• Compatible with FX Version of Fast Ethernet
• Low-Power: 205 mW from Single 3.3V Supply
• Integrated Termination Resistors for Low External Discrete Count
• Fully Supports PoE-Based Power and Data Signal Distribution Over Coax
  • 16-Pin, 0.65 mm Pin Pitch, 4 mm QFN Package
  • Pb-Free and RoHS Compliant

Applications

This solution is useful and economical for many markets and applications, including the following:

• Camera Networks
• Home Security, Surveillance, Industrial/Inspection, Medical Cameras
  • Home Networking over Coax Infrastructure
• When Cat5 or Cat6 cabling is not available and existing 75Ω coax is not used for analog TV signals
  • TV, STB, PVR Connections Including Inter-Room Links

TABLE 1: TYPICAL DEVICE PERFORMANCE FOR EQCO875SC.3

Version	EQCO875SC.3 Range Using
	RG11 RG6 (∅ 5 mm)
EQCO875SC.3 225m 150m

TABLE 2: TYPICAL DEVICE PERFORMANCE FOR EQCO850SC.3

Version	EQCO850SC.3 Range Using
	RG174 RTK RG58
EQCO850SC.3 40m 70m 70m

Table of Contents

1.0 Device Overview 3
2.0 Application Information....7
3.0 Electrical Characteristics 9
4.0 Packaging....11

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Most Current Data Sheet

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1.0 DEVICE OVERVIEW

The EQCO875SC.3 single-coax transceiver is designed to simultaneously transmit and receive signals on a single 75Ω coax cable for Fast Ethernet. A sister product, the EQCO850SC.3, can achieve similar performance when used in 50Ω coaxial systems.

The EQCO875SC.3 is ideally suited for Fast Ethernet connections over a 75Ω coax cable at a 125 Mbps data rate. The EQCO875SC.3 connects seamlessly to any FX-compliant physical layer controller (PHY). For correct operation, the signals are expected to be 4B/5B encoded, DC balanced and to have a bit rate of 125 Mbps.

This EQCO875SC.3 is useful and economical for connecting remote PoE-enabled Fast Ethernet IP cameras and other Ethernet over Coax applications.

Figure 1-1 illustrates a typical Ethernet Coaxial connection:
FIGURE 1-1: COAXIAL ETHERNET PMD CONNECTION

graph LR
    A["IEEE 802.3 FX Compliant PHY"] --> B["EQCO875SC"]
    B --> C["75Ω Coax (including inline connectors as required)"]
    C --> D["EQCO875SC"]
    D --> E["IEEE 802.3 FX Compliant PHY"]
    style B fill:#99CCFF,stroke:#333
    style D fill:#99CCFF,stroke:#333
    note right of B "Up to 225 meters"

FIGURE 1-2: EQCO875SC.3 PIN DIAGRAM (VIEWED FROM TOP)
(1)

CCUT DVCC OPT0 DGND 16 15 14 13 AVCC 1 SDIO 2 REF 3 AGND 4 EQCO875SC.3 GND TAB 12 SDOp 11 SDOn 10 SDIp 9 SDIn 5 6 7 8 OPT1 CLK DAT NC

Note 1: Devices named EQCO850SC.2 can be used for all applications contained in this data sheet. They are the same in all aspects.

TABLE 1-1: EQCO875SC.3 PIN DESCRIPTIONS

Pin Number Pin Name Signal		Type Description
(TAB) GND Power	Connect to ground of power supply.
15 DVCC Power Digital VCC. Connect to +3.3V of power supply.
13	DGND	Power Digital	GND. Connect to ground of power supply.
1	AVCC	Power Analog	VCC. Connect to +3.3V of power supply via ferrite bead (RF choke) and capacitor to cable outer screen.
4	AGND	Power Analog	GND. Connect to cable outer screen.
2	SDIO	Bidirectional	Serial Input/Output. Connect to center conductor of 75Ω coax cable.
3	REF	Bidirectional	Reference. Connect through 75Ω resistor (or impedance matched to cable) to cable outer screen.
8	NC	Output	Do not connect.
10, 9	SDIp/SDIn	Input	Positive/negative differential serial input. Connect to the Ethernet PHY FX Out pins.
12, 11	SDOp/SDOn	Output	Positive/negative differential serial output. Connect to the Ethernet PHY FX In pins.
14, 5	OPT0, OPT1	Input	Connect Opt0 to DGND and Opt1 to DVCC to enable Fast Ethernet mode.
6, 7	CLK, DAT	Input	Used for production test. Connect to DGND.
16 CCUT	Analog	Connect to DVCC.

FIGURE 1-3: EQCO875SC.3 BLOCK DIAGRAM SHOWING ELECTRICAL CONNECTIONS

graph TD
    A["SDIp"] --> B["Input Pre-Driver"]
    C["SDIn"] --> B
    B --> D["Active Signal Splitter/Combiner"]
    D --> E["Equalizer Core"]
    E --> F["RX Output Driver"]
    G["SDOp"] --> F
    H["SDOn"] --> F
    F --> I["Transmit Wake-Up Detection"]
    I --> B
    D --> J["REF"]
    D --> K["SDIO"]

1.1 SDIp/SDIn

SDIp/SDIn together form a differential input pair. The serial data received on these pins will be transmitted on SDIO. The Input Pre-Driver automatically corrects for variations in signal levels and different edge slew rates at these inputs before they go into the Active Splitter/Combiner for transmission over the coax.

Both SDIp and SDIn inputs are differentially terminated by 110Ω on-chip. The center of the 110Ω is connected to DGND with a 10 kΩ resistor for DC biasing. The inputs also have protection diodes to ground for ESD purposes. These inputs should always be capacitively coupled to the FX output of the Ethernet PHY. A Transmit Wake-Up detection circuit puts both the Input Pre-Driver and the Active Signal Splitter/Combiner into a low-power mode when no signal is detected on the SDIp/SDIn signal pair.

1.2 SDIO/REF

The signal on the SDIO pin is the sum of the incoming signal (i.e. the signal transmitted by the EQCO875SC on the far-end side of the coax) and the outgoing signal (i.e. the signal created based on SDIp/SDIn). The far-end signal is extracted by subtraction of the near-end signal, and it is this voltage that the equalizer analyses and adaptively equalizes for level and frequency response based on the knowledge that the originating signal is 4B/5B encoded before transmission.

The REF signal carries a precise anti-phase current to the transmit current on SDIO. REF must be connected directly to AGND at the connector (see Figure 3-2) via a resistor precisely matched to the impedance of the coaxial cable used.

1.3 SDOp/SDOn

SDOp/SDOn together form a differential pair outputting the reconstructed far-end transmit signal. The EQCO850SC-HS uses LVDS drivers with source matching for a 100Ω transmission line. This LVDS signal can normally be connected (subject to input common-mode requirements) directly to the RX signal pair of a standard LVDS receiver.

1.4 OPT0, OPT1

Connect Opt0 to DGND and Opt1 to DVCC to enable Fast Ethernet mode.

1.5 CLK, DAT Pins

These pins are normally used to access an internal register during production test. Connect them to DGND for normal operation. They should not be left floating.

The pre-driver removes any dependency on Ethernet PHY for the amplitude and rise time of the outgoing signal on SDIO.

2.2 Active Signal Splitter/Combiner

The Active Splitter/Combiner controls the amplitude and rise time of the outgoing coax signal and transmits it via a precise 75Ω output termination resistor. The output resistor, when balanced with the coax characteristic impedance, also forms part of a hybrid splitter circuit which subtracts the TX output from the signal on the SDIO output to give yield the far-end TX signal. The return-loss of the coax termination is a key factor in the performance of the line hybrid.

2.3 Equalizer Core

The EQCO875SC-HS has an embedded high-speed equalizer in the receive path with unique characteristics:

- Auto-adaptive

The equalizer controls a multiple-pole analog filter which compensates for attenuation of the cable, as illustrated in Figure 2-1. The filter frequency response needed to restore the signal is automatically determined by the device using a time-continuous feedback loop that measures the frequency components in the signal. Upon the detection of a valid signal, the control loop converges within a few microseconds.

- Variable gain

EQCO875SCs are used in pairs, with one at each end of the coax cable. The EQCO875SC can be used with any Fast Ethernet compliant fiber optic PHY; any differences in transmit amplitude are removed by the input pre-driver. The receiver equalizer has variable gain to compensate for attenuation through the coax cable.

FIGURE 2-1: PRINCIPLE OF EQUALIZER OPERATION

graph TD
    A["Transmission Line Driver"] --> B["Transmission Line"]
    B --> C["Equalizer"]
    C --> D["Digital Receiver"]
    C --> E["Cable Attenuation"]
    C --> F["Equalizer Gain"]
    C --> G["Equalized Path Loss"]
    E --> H["Amplitude (dB) vs Frequency (MHz)"]
    F --> I["Gain (dB) vs Frequency (MHz)"]
    G --> J["Amplitude (dB) vs Frequency (MHz)"]
    style A fill:#cce5ff,stroke:#333
    style B fill:#e6f7ff,stroke:#333
    style C fill:#e6f7ff,stroke:#333
    style D fill:#ffe6cc,stroke:#333
    style E fill:#ffcccc,stroke:#333
    style F fill:#e6f7ff,stroke:#333
    style G fill:#e6f7ff,stroke:#333
    style H fill:#e6f7ff,stroke:#333
    style I fill:#e6f7ff,stroke:#333
    style J fill:#e6f7ff,stroke:#333

3.0 APPLICATION INFORMATION

Figure 3-1 illustrates a typical schematic implementation for the EQCO875SC.3 in Ethernet mode.

FIGURE 3-1: EQCO875SC.3 TYPICAL APPLICATION CIRCUIT

48V_DC C10 1u 100V L1 1812PS-103KLB J1 GND C5 10n 2 100V R1 C6 10n 3 100V 50R/75R FB1 BLM15HD182SN1D 17 16 15 14 13 TAB CCUT DVCC OPT0 DGND AVCC SD Op 12 100nC3 SDOp SDU SD On 11 100nC4 SDOn REF SDIp 10 100nC1 SDIp AGND SDIn 9 100nC2 SDIn OPT1 CLK DAT NC 5 6 7 8 VCC GND U1 EQCO850SC.3/EQCO875SC.3

To improve isolation from noise on the board power plane and improve EMC immunity and emissions, it is recommended to power the transmit side of the equalizer (AVCC) through a ferrite bead (FB1). C9 is used to reference AVCC to the ground directly at the connector J1, while AGND is also connected directly to the connector.

A 100 nF decoupling capacitor (C7) should be placed as close as possible between the DVCC pin and the DGND pin. The REF and SDIO signals are AC-coupled with identical capacitors, C5 and C6. Termination resistor R1 should match the characteristic impedance of the system, 50Ω for EQCO850SC.3 and 75Ω for EQCO875SC.3.

A CoilCraft 1812PS-103KLB inductor (L1) is recommended for best performance when using power over coax. L1 and C10 can be removed if power over coax is not required.

3.1 Guidelines for PCB Layout

Because signals are strongly attenuated by long cables, special attention must be paid on the PCB layout between the coaxial connector and the EQCO875SC.3. The EQCO875SC.3 should be placed as close as is practical to the coaxial connector. The trace between the coaxial connector and the SDIO pin of the EQCO875SC.3 must be a 75Ω (50Ω for EQCO850SC.3) trace referenced to GND. To avoid noise pickup, other traces carrying digital signals or fast-switching signals should be placed as far away as possible from this trace.

The ground layout on the EQCO875SC.3 is crucial to the EMC and EMI performance of the circuit. The AGND connection should be connected directly to the body of the connector as shown. Similarly, AVCC

should be decoupled directly to the connector body (see the position of C9). The termination resistor (R1 in Figure 3-1 and Figure 3-2) must have its ground connection at the connector body. The impedance of all the traces must be well controlled, including on the connector itself. To compensate for parasitic capacitances, the ground and power planes underneath L1 and part of the coax connector need to be removed, as indicated by the green areas on Figure 3-2.

The SDIp/SDIn and SDOp/SDOn differential traces should be laid out as 100Ω differential traces.

The following diagram shows the layout of the critical section of the PCB corresponding to the circuit of Figure 3-1 from the coax connector to the twin differential pairs:

FIGURE 3-2: TYPICAL PCB LAYOUT

010 J1 GND : GND 2.48V_DC C9 C8 C7 U1 SIG NetC5_1 1: NetC5_1 17 GND C3 C4 C1 C2 GND : GND R1

4.0 ELECTRICAL CHARACTERISTICS

4.1 Absolute Maximum Ratings

Stresses beyond those listed under this section may cause permanent damage to the device. These are stress ratings only and are not tested. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

TABLE 4-1: ABSOLUTE MAXIMUM RATINGS

Parameter Min. Typ. Max. Units Conditions
Storage Temperature -65 — +150 °C
Ambient Temperature -55 — +125 °C Power Applied
Supply Voltage to Ground	-0.5	—	+4.0	V
DC Input Voltage	-0.5	—	+4.0	V
DC Voltage to Outputs	-0.5	—	+4.0	V
Output Current into Outputs	—	—	90	mA	Outputs Low

TABLE 4-2: ELECTRICAL CHARACTERISTICS

Parameter	Min.	Typ.	Max.	Unit	Description
Power Supply
V_cc	3.2	3.3	3.4	V	Supply voltage.
I_s	47.5	62.5	75.5	mA	Supply current, both transmitting and receiving.
I_SR	25	35	43	mA	Supply current when not transmitting.
SDIp/SDIn Input (LVDS-like)
V_i	250	—	800	mV	Input amplitude V_SDIp,n .
V_turnon	100	140	200	mV	Minimal V_i to turn on transmit function.
V_cmin	—	0	—	V	Common-mode input voltage (terminated to ground with protection diodes).
R_input	85	104	115	Ω	Differential input termination.
SDIO Connection to Coax
Z_coax	72 (48)	75 (50)	78 (52)	Ω	Required coax cable characteristic impedance.
R_SDIO	65 (46)	75 (51)	86 (55)	Ω	Input impedance between SDIO and AGND.
R_loss	20	—	—	dB	Coax return-loss as seen on SDIO pin. Frequency range = 10 MHz-62.5 MHz.
V_TX	250	300	350	mV	Transmit amplitude.
t_rise\_tx	350	450	550	ps	Rise/fall time 20% to 80% of V_TX .
Att_max	—	10	—	dB	Cable attenuation budget @ 62.5 MHz.
V_RXmin	—	40	—	mV	Minimum input for fully reconstructed output.
SDOp/SDOn Outputs (LVDS-like)
V_o	250 350	450 mV	Output amplitude	V	SDOp,n.
V_cmout	1.1 1.2	1.3 V	Common-mode output voltage.
R_output	85 102	115 Ω	Differential termination between SDOp and SDOn.
t_rise\_o	150 240	350	ps Rise/fall time 20% to 80% of V		SDOp,n.

TABLE 4-3: JITTER PERFORMANCE

Parameter	Min.	Typ.	Max.	Units	Conditions
Jitter peak-to-peak on SDO	—	40%	50%	UI	150m RG6 coax; over full V_CC , V_TX , and temp range; 125 Mbps; pattern PRBS7

TABLE 4-4: TEMPERATURE SPECIFICATIONS

Parameter	Symbol	Min.	Typ.	Max.	Unit
Temperature Ranges
Operating Ambient Temperature	T_A	-10	-	70	°C
Operating Junction Temperature	T_J	-10	-	85	°C
Thermal Package Resistances
Typical Junction to Package	_JT	-	1.2	-	°C/W
Typical Junction to Ambient	_JA	-	59	-	°C/W
Typical Junction to Case	_JC	-	10	-	°C/W

5.0 PACKAGING INFORMATION

5.1 Package Marking Information

16-Lead Plastic Quad Flat, No Lead Package - 4x4x0.9 mm Body [QFN]

16-Lead QFN (4x4x0.9 mm) Example

PIN 1-PIN 1 XXXXX XXXXXX XXXXXX YYWWNNN

EQCO 875SC.3 YYWWNNN

Legend: XX...X Part number

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week '01')

NNN Alphanumeric traceability code (optional)

Pb-free JEDEC ^® designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.

16-Lead Plastic Quad Flat, No Lead Package (8E) - 4x4x0.9 mm Body [QFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

NOTE 1 1 2 (DATUM B) (DATUM A) 2X 0.20 C 2X 0.20 C TOP VIEW SEATING PLANE C A (A3) // 0.10 C A1 SIDE VIEW 16X 0.08 C ⊕ 0.10 A B D2 (16X K) ⊕ 0.10 A B e2 2 1 E2 16X L N e 16X b BOTTOM VIEW ⊕ 0.10 A B 0.05

Microchip Technology Drawing C04-259B Sheet 1 of 2

16-Lead Plastic Quad Flat, No Lead Package (8E) - 4x4x0.9 mm Body [QFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Two isometric line drawings of an integrated circuit chip, one with a square top and the other with a rectangular base (no text or symbols)

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Number of Pins	N	16
Pitch	e	0.65 BSC
Overall Height	A	0.80	0.87	0.95
Standoff	A1	0.00	0.02	0.05
Terminal Thickness	A3	0.20 REF
Overall Width	E	4.00 BSC
Exposed Pad Width	E2	1.95	2.05	2.15
Overall Length	D	4.00 BSC
Exposed Pad Length	D2	1.95	2.05	2.15
Terminal Width	b	0.25	0.30	0.35
Terminal Length	L	0.45	0.55	0.65
Terminal-to-Exposed-Pad	K 0.425 REF

Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-259B Sheet 2 of 2

16-Lead Plastic Quad Flat, No Lead Package (8E) - 4x4x0.9 mm Body [QFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

C1 X2 16 G1 C2 Y2 1 2 X1 Y1 E SILK SCREEN

RECOMMENDED LAND PATTERN

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Contact Pitch	E	0.65 BSC
Optional Center Pad Width	X2			2.15
Optional Center Pad Length	Y2			2.15
	C1Contact Pad Spacing 3.625
Contact Pad Spacing	C2		3.625
Contact Pad Width (X16)	X1			0.30
Contact Pad Length (X16)	Y1			0.725
Contact Pad to Center Pad (X16) G1	0.20

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2259A

APPENDIX A: REVISION HISTORY

Revision A (April 2016)

This is the initial release of the document in the Microchip format. This replaces EqcoLogic document version 2.0.

TABLE A-1: REVISION HISTORY

Version Date Comments
2v0	1/28/14	Merged 50Ω and 75Ω systems into one data sheet.
1v2 10/25/11	Fixed lower temperature limit.
1v1 6/8/11	Fixed bitrate, temperature range, SDIP/SDIN descriptions.
0v4 2/28/11	Internal quality review.	Removed Preliminary status.
0v3 10/26/09	Technical review.	Revised Section 5.1
0v2 10/15/09	Internal review.
0v1 10/15/09	Modified from EQCO	875SC IEEE1394 data sheet.

NOTES:

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PRODUCT IDENTIFICATION SYSTEM

To order parts, including industrial, or obtain information, for e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

XXXX

Device

Package

Device: EQCO875SC.3

EQCO850SC.3

Package: TRAY = Tray

"blank" = Tube

Examples:

a) EQCO875SC.3-TRAY = 75Ω Coax,

Industrial temperature,

16-Lead QFN package,

Tray packaging

b) EQCO850SC.3

= 50Ω Coax,

Industrial temperature,

16-Lead QFN package,

Tube packaging

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Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

© 2009-2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

ISBN: 978-1-5224-0468-2

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