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USER MANUAL SY89835U Microchip
The SY89835U is a 2.5V, high-speed 2GHz differential Low Voltage Differential Swing (LVDS) 1:2 fanout buffer optimized for ultra-low skew applications. Within device skew is guaranteed to be less than 20ps over supply voltage and temperature. A unique Fail-Safe Input (FSI) protection prevents metastable conditions when no signal is present or when the selected input clock fails to a DC voltage (voltage between the pins of the differential input drops sufficiently below 100 mV).
The SY89835U is part of Micrel's high-speed clock synchronization family. For applications that require a different I/O combination, consult Micrel's web site, and choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators and clock generators.
Data sheets and support documentation can be found on Micrel's web site at: www.micrel.com.
Functional Block Diagram

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IN 100Ω /IN Q0 /Q0 Q1 /Q1
Precision Edge®
Features
• Guaranteed AC performance over temperature and voltage:
- DC-to > 3.2Gbps throughput
- 210ps typical propagation delay (IN-to-Q)
- <20ps within-device skew
- <150ps rise/fall times
- Fail Safe Input
– Prevents outputs from oscillating
- Ultra-low jitter design
- < 1 ps_RMS cycle-to-cycle jitter
- <10psPP total jitter
- < 1 ps_RMS random jitter
- < 10ps_PP deterministic jitter
• High-speed LVDS outputs
• 2.5V ±5% power supply operation
- Industrial temperature range: -40^ to +85^
• Available in 8-pin (2mm x 2mm) MLF™ package
Applications
- Clock or data distribution
• SONET clock or data distribution
• Fibre Channel clock or data distribution
• Gigabit Ethernet clock or data distribution
Markets
- DataCom
- Telecom
- Storage
- ATE
• Precision test and measurement
Precision Edge is a registered trademark of Micrel, Inc.
MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax +1 (408) 474-1000 • http://www.micrel.com
Ordering Information ^(1)
| Part Number | Package Type | Operating Range | Package Marking | Lead Finish |
| SY89835UMG | MLF-8 | Industrial | 835 with Pb-Free bar-line indicator | NiPdAu Pb-Free |
| SY89835UMGTR(2) | MLF-8 | Industrial | 835 with Pb-Free bar-line indicator | NiPdAu Pb-Free |
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration

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VCC 1 8 Q0 IN 2 7 /Q0 /IN 3 6 Q1 GND 4 5 /Q18-Pin MLF™ (MLF-8)
Pin Description
| Pin Number Pin Name Pin Function | ||
| 1 | VCC | Positive Power Supply: Bypass with 0.1μF//0.01μF low ESR capacitor and place as close to VCC pin as possible. Power supply tolerance is ±5%. |
| 2, 3 IN, /IN | Differential Inputs: This input pair is the differential signal input to the device. Input accepts DC-Coupled differential signals as small as 100mV (200mVpp). The input is internally terminated with 100Ω between IN and /IN. If the input swing falls below a certain threshold (typically 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by latching the output to its last valid state. Please refer to the “Input Interface Applications” section for more details. | |
| 4 | GND | Ground. GND pins and exposed pad must be connected to the most negative potential of the device ground. |
| 5, 67, 8 | /Q1, Q1/Q0, Q0 | Differential Outputs (LVDS): Normally terminated with 100Ω across the pair (Q, /Q). See “LVDS Outputs” section, Figure 2a. |
Truth Table
| IN | /IN | Q | /Q |
| 0 | 1 | 0 | |
| 1 | 0 | 1 |
Absolute Maximum Ratings ^(1)
Supply Voltage (Vcc) -0.5V to +4.0V
Input Voltage ( V_IN ) -0.5V to V_CC + 0.3V
LVDS Output Current ( I_OUT )....±10mA
Input Current
Source or Sink Current on (IN, /IN) ....±50mA
Lead Temperature (soldering, 20sec.)....260°C
Storage Temperature ( T_s ) -65^ to +150^
Operating Ratings ^(2)
Supply Voltage ( V_IN )....+2.375V to +2.635V
Ambient Temperature ( T_A ) -40^ to +85^
Package Thermal Resistance ^(3)
MLF ^TM
Still-air ( _JA ).... 93°C/W
Junction-to-board ( _JB ) 32°C/W
DC Electrical Characteristics ^(4)
T_A = -40^ to +85^ , unless otherwise stated.
| Symbol | Parameter Condition | Min | Typ | Max | Units | ||||
| V_CC | Power Supply Voltage Range | 2.375 | 2.5 | 2.625 | V | ||||
| I_CC | Power Supply Current | No load, max. V_CC | 50 | 70 | mA | ||||
| R_DIFF\_IN | Differential Input Resistance (IN-to-/IN) | 90 | 100 | 110 | Ω | ||||
| V_IH | Input HIGH Voltage (IN, /IN) | 1.2 | V_CC | V | |||||
| V_L | Input LOW Voltage (IN, /IN) | 0 | V_IH-0.1 | V | |||||
| V_IN | Input Voltage Swing (IN, /IN) | see Figure 2c | 0.1 | V_CC | V | ||||
| V_DIFF\_IN | Differential Input Voltage Swing (|IN - /IN|) | see Figure 2d | 0.2 | V | |||||
| V_IN\_FSI | Input Voltage Threshold that Triggers FSI | 30 | 100 | mV | |||||
LVDS Outputs DC Electrical Characteristics ^(4)
V_CC = +2.5V ± 5% , R_L = 100 across the outputs; T_A = -40^ to +85^ , unless otherwise stated.
| Symbol | Parameter Condition | Min | Typ | Max | Units | ||||
| V_OUT | Output Voltage Swing | See Figure 2c | 250 | 325 | mV | ||||
| V_DIFF\_OUT | Differential Output Voltage Swing | See Figure 2d | 500 | 650 | mV | ||||
| V_OCM | Output Common Mode Voltage | 1.125 | 1.20 | 1.275 | V | ||||
| V_OCM | Change in Common Mode Voltage | -50 | 50 | mV | |||||
Notes:
- Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
- The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
- Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB and _JA values are determined for a 4-layer board in still-air number, unless otherwise stated.
- The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
AC Electrical Characteristics ^(5)
V_CC = +2.5V ± 5% , R_L = 100 across the outputs; T_A = -40^ to +85^ , unless otherwise stated.
| Symbol | Parameter Condition | Min Typ Max Units | |||||
| MAX | Maximum Frequency | V_OUT>200mV NRZ Data 3.2 Gbps f | |||||
| Clock | 2.0 | 3.0 | GHz | ||||
| t_PD | Propagation Delay IN-to-Q | V_IN:100mV-200mV>200mV | 150 | 300 | 500 | ps | |
| 100 | 210 | 400 | |||||
| t_Skew | Within Device Skew | Note 6 | 5 | 20 | ps | ||
| Part-to-Part Skew | Note 7 | 200 | ps | ||||
| t_Jitter | Data Random Jitter | Note 8 | 1 | ps_RMS | |||
| Deterministic Jitter | Note 9 | 10 | ps_PP | ||||
| Clock Cycle-to-Cycle Jitter | Note 10 | 1 | ps_RMS | ||||
| Total Jitter | Note 11 | 10 | ps_PP | ||||
| t_r,t_f | Output Rise/Fall Times(20% to 80%) | At full output swing. | 40 | 75 | 150 | ps | |
| Duty Cycle | Differential I/O | 47 | 53 | % | |||
Notes:
- High-frequency AC parameters are guaranteed by design and characterization.
- Within device skew is measured between two different outputs under identical input transitions.
- Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs.
- Random jitter is measured with a K28.7 pattern, measured at ≤ f_MAX
- Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2^23-1 PRBS pattern.
- Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. t_JITTER_CC = T_n - T_n+1 , where T is the time between rising edges of the output signal.
- Total jitter definition: with an ideal clock input frequency of ≤ f_MAX (device), no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value.
Functional Description
Fail-Safe Input (FSI)
The input includes a special failsafe circuit to sense the amplitude of the input signal and to latch the outputs when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mV_PK ( 200mV_PP ).
Input Clock Failure Case
If the input clock fails to a floating, static, or extremely low signal swing, the FSI function will eliminate a
metastable condition and guarantee a stable output signal. No ringing and no undetermined state will occur at the output under these conditions.
Please note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend upon the rise and fall time of the input signal and on its amplitude. Refer to "Typical Operating Characteristics" for detailed information.
Timing Diagrams

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| Signal | Time Segment | Amplitude Level | |--------|--------------|-----------------| | IN | t_pd | V_IN | | Q | t_pd | V_OUT | | /Q | t_pd | V_IN |Typical Characteristics
V_CC = 2.5V , GND = 0V, V_IN = 100mV , R_L = 100 across the outputs, T_A = 25^ , unless otherwise stated.

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| FREQUENCY (MHz) | OUTPUT SWING (mV) | | --------------- | ----------------- | | 0 | 320 | | 500 | 318 | | 1000 | 315 | | 1500 | 305 | | 2000 | 295 | | 2500 | 285 | | 3000 | 270 | | 3500 | 265 |
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| INPUT RISE/FALL TIME (ps) | PROPAGATION DELAY (ps) | | ------------------------- | ---------------------- | | 0 | 240 | | 200 | 250 | | 400 | 280 | | 600 | 310 | | 800 | 340 | | 1000 | 360 |
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| INPUT RISE/FALL TIME (ps) | PROPAGATION DELAY (ps) | | ------------------------- | ---------------------- | | 0 | 220 | | 200 | 230 | | 400 | 250 | | 600 | 260 | | 800 | 265 | | 1000 | 270 |
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| INPUT RISE/FALL TIME (ps) | PROPAGATION DELAY (ps) | | ------------------------- | ---------------------- | | 0 | 200 | | 200 | 210 | | 400 | 230 | | 600 | 240 | | 800 | 250 | | 1000 | 260 |Functional Characteristics
V_CC = 2.5V , GND = 0V, V_IN = 100mV , R_L = 100 across the outputs, T_A = 25^ , unless otherwise stated.

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| Time (600ps/div.) | Output Swing (70mV/div.) | | ----------------- | ------------------------ | | 0 | 0 | | 1 | 1 | | 2 | 0 | | 3 | 1 | | 4 | 0 | | 5 | 1 | | 6 | 0 | | 7 | 1 | | 8 | 0 | | 9 | 1 | | 10 | 0 | | 11 | 1 | | 12 | 0 | | 13 | 1 | | 14 | 0 | | 15 | 1 | | 16 | 0 | | 17 | 1 | | 18 | 0 | | 19 | 1 | | 20 | 0 | | 21 | 1 | | 22 | 0 | | 23 | 1 | | 24 | 0 | | 25 | 1 | | 26 | 0 | | 27 | 1 | | 28 | 0 | | 29 | 1 | | 30 | 0 | | 31 | 1 | | 32 | 0 | | 33 | 1 | | 34 | 0 | | 35 | 1 | | 36 | 0 | | 37 | 1 | | 38 | 0 | | 39 | 1 | | 40 | 0 | | 41 | 1 | | 42 | 0 | | 43 | 1 | | 44 | 0 | | 45 | 1 | | 46 | 0 | | 47 | 1 | | 48 | 0 | | 49 | 1 | | 50 | 0 | | 51 | 1 | | 52 | 0 | | 53 | 1 | | 54 | 0 | | 55 | 1 | | 56 | 0 | | 57 | 1 | | 58 | 0 | | 59 | 1 | | 60 | 0 | | 61 | 1 | | 62 | 0 | | 63 | 1 | | 64 | 0 | | 65 | 1 | | 66 | 0 | | 67 | 1 | | 68 | 0 | | 69 | 1 | | 70 | 0 | | | |
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| TIME (150ps/div.) | Output Swing (70mV/div) | | ----------------- | ------------------------ | | 0 | 0 | | 1 | 1 | | 2 | 0 | | 3 | -1 | | 4 | 0 | | 5 | 1 | | 6 | 0 | | 7 | -1 | | 8 | 0 | | 9 | 1 | | 10 | 0 | | 11 | -1 | | 12 | 0 | | 13 | 1 | | 14 | 0 | | 15 | -1 | | 16 | 0 | | 17 | 1 | | 18 | 0 | | 19 | -1 | | 20 | 0 | | 21 | 1 | | 22 | 0 | | 23 | -1 | | 24 | 0 | | 25 | 1 | | 26 | 0 | | 27 | -1 | | 28 | 0 | | 29 | 1 | | 30 | 0 | | 31 | -1 | | 32 | 0 | | 33 | 1 | | 34 | 0 | | 35 | -1 | | 36 | 0 | | 37 | 1 | | 38 | 0 | | 39 | -1 | | 40 | 0 | | 41 | 1 | | 42 | 0 | | 43 | -1 | | 44 | 0 | | 45 | 1 | | 46 | 0 | | 47 | -1 | | 48 | 0 | | 49 | 1 | | 50 | 0 | | 51 | -1 | | 52 | 0 | | 53 | 1 | | 54 | 0 | | 55 | -1 | | 56 | 0 | | 57 | 1 | | 58 | 0 | | 59 | -1 | | 60 | 0 | | 61 | 1 | | 62 | 0 | | 63 | -1 | | 64 | 0 | | 65 | 1 | | 66 | 0 | | 67 | -1 | | 68 | 0 | | 69 | 1 | | 70 | 0 | | 71 | -1 | | 72 | 0 | | 73 | 1 | | 74 | 0 | | 75 | -1 | | 76 | 0 | | 77 | 1 | | 78 | 0 | | 79 | -1 | | 80 | 0 | | Note: The data is extracted from the code and presented in CSV format as requested. The output values are estimated based on the provided code. There is no additional data series in this case. |
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| TIME (50ps/div.) | Output Swing (70mV/div) | | ---------------- | ------------------------ | | 0 | 0 | | 50 | 100 | | 100 | 0 | | 150 | -100 | | 200 | 0 | | 250 | 100 | | 300 | 0 | | 350 | -100 | | 400 | 0 | | 450 | 100 | | 500 | 0 | | 550 | -100 | | 600 | 0 | | 650 | 100 | | 700 | 0 | | 750 | -100 | | 800 | 0 | | 850 | 100 | | 900 | 0 | | 950 | -100 | | 1000 | 0 |Input Stage

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VCC IN 100Ω /IN GNDFigure 1. Simplified Differential Input Buffer
LVDS Outputs
LVDS specifies a small swing of 325mV typical, on a nominal 1.20V common mode above ground. The common mode voltage has tight limits to permit large variations in ground noise between an LVDS driver and receiver. These outputs can drive AC- or DC-coupled differential signals.
The SY89835U can drive long lengths of coaxial cables and FR4 traces. Table 1 below shows typical lengths of cables driven at different clock and data rates.
| Clock/Data Rate | Coaxial Cable Length(1) | FR4 Cable Length(2) |
| 100MHz | 4.5m | 1.40m |
| 622MHz | 3.5m | 0.85m |
| 1.25Gbps | 3.8m | 0.80m |
| 2.50Gbps | 3.3m | 0.50m |
Table 1. Typical Lengths of Coaxial and FR4 Traces
Notes:
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Specifications for the center conductor of the coaxial cables used are "19 1/19 spcw OD .037 inch ± 0.001". These are 1m cables, p/n SB-142 manufactured by Harbour Industries. www.harbourind.com.
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The FR4 traces are 6.25mil wide and 6mil thick. Horizontal distance between adjacent traces is 7.75mil. These traces are fabricated on a Molex GBX Reference Backplane. www.molex.com.

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VOUT 100Ω VOH, VOL VOH, VOL GNDFigure 2a. LVDS Differential Measurement

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50Ω 50Ω VOCM, ΔVOCM GNDFigure 2b. LVDS Common Mode Measurement

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VOUT, VIN 325mV (typical)Figure 2c. Single-Ended Swing

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650mV VDIFF_IN, VDIFF_OUTFigure 2d. Differential Swing
Input Interface Applications

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VCC = 2.5V LVDS IN /IN 100Ω VCC = 2.5V SY89835UFigure 3. LVDS Input Interface
Related Product and Support Documents
| Part Number Function Data Sheet Link | ||
| SY89542U | 2.5V, 3.2Gbps Dual, Differential 2:1 LVDS Multiplexer with Internal Termination | http://www.micrel.com/_PDF/HBW/sy89542u.pdf |
| SY89543L | 3.3V, 3.2Gbps Dual, Differential 2:1 LVDS Multiplexer with Internal Termination | http://www.micrel.com/_PDF/HBW/sy89543u.pdf |
| SY89544U | 2.5V, 3.2Gbps Differential 4:1 LVDS Multiplexer with Internal Input Termination | http://www.micrel.com/_PDF/HBW/sy89544u.pdf |
| MLFTM Manufacturing Guidelines Exposed Pad Application Notes | http://www.amkor.com/products/notes-papers/MLF_appnote_0301.pdf | |
| HBW Solutions | New Products and Termination Application Notes | http://www.micrel.com/product-info/products/sy89830u.shtml |
Package Information

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PIN #1 ID BY MARKING 2.000±0.050 2.000±0.050TOP VIEW

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1.300±0.050 0.350 0.250±0.050 8 7 0.500 BSC 6 5 R0.100 1 I.200±0.050 EXP. PAD 3 4 0.600±0.050 EXP. PAD 1.750 REF 0.125±0.050BOTTOM VIEW

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0.850±0.050 0.000-0.050 1 2 3 0.203±0.025SIDE VIEW
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm.
3. MAXIMUM ALLOWABE BURRS IS 0.076 mm IN ALL DIRECTIONS
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.
8-Pin MLF™ (MLF-8)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
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