SY89834U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY89834U Microchip

■ Selects between two LVTTL/CMOS inputs and provides 4 LVPECL output copies
■ Guaranteed AC performance over temperature and voltage:

• DC-to >1.0GHz throughput
  • <500ps propagation delay (IN-to-Q)
  • < 20ps within-device skew
• < 225ps rise/fall time

■ Ultra-low jitter design:

• < 1ps RMS cycle-to-cycle jitter
• < 1ps RMS random jitter
• < 10ps PP deterministic jitter
• < 10ps PP total jitter (clock)

■ Low voltage 2.5V and 3.3V supply operation
■ 100K LVPECL outputs
■ Industrial temperature range: -40^ to +85^
■ Includes a 2:1 MUX select input
■ Accepts single-ended TTL/CMOS inputs and provides four LVPECL outputs
■ Available in 16-pin (3mm · 3mm) MLF™ package

Precision Edge®

DESCRIPTION

The SY89834U is a high-speed, 1GHz LVTTL/CMOS-to-LVPECL fanout buffer/translator optimized for high-speed ultra-low skew applications. The input stage is designed to accept two single-ended LVTTL/CMOS compatible signals that feed into a 2:1 MUX. The selected input is translated and distributed as four differential 100K LVPECL outputs. Within device skew is guaranteed to be less than 20ps over supply voltage and temperature.

The single-ended input buffers accept TTL/CMOS logic levels. The internal threshold of the buffers is defined as V_CC/2 .

The SY89834U is a part of Micrel's high-speed Precision Edge® family. For applications that require a different I/O combination, consult Micrel's website at: www.micrel.com, and choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators and clock generators.

APPLICATIONS

■ Processor clock distribution/translation
■ SONET clock distribution/translation
■ Fibre Channel clock distribution/translation
■ Gigabit Ethernet clock distribution/translation
■ Single-ended ASIC-to-differential communication IC signal translation

FUNCTIONAL BLOCK DIAGRAM

graph TD
    A["IN1 (LVTTL/CMOS)"] --> B["MUX 0"]
    C["IN2 (LVTTL/CMOS)"] --> B
    D["EN LVTTL/CMOS"] --> E["D Q"]
    B --> F["1:4"]
    E --> F
    F --> G["Q0 /Q0"]
    F --> H["Q1 /Q1"]
    F --> I["Q2 /Q2"]
    F --> J["Q3 /Q3"]
    style A fill:#f9f,stroke:#333
    style C fill:#f9f,stroke:#333
    style D fill:#f9f,stroke:#333
    style B fill:#ccf,stroke:#333
    style E fill:#ccf,stroke:#333
    style F fill:#ccf,stroke:#333
    style G fill:#cfc,stroke:#333
    style H fill:#cfc,stroke:#333
    style I fill:#cfc,stroke:#333
    style J fill:#cfc,stroke:#333

Precision Edge is a registered trademark of Micrel, Inc.

MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.

PACKAGE/ORDERING INFORMATION

/Q0 /Q0 VCC GND 16 15 14 13 Q1 1 /Q1 2 Q2 3 /Q2 4 5 6 7 8 Q3 /Q3 VCC EN IN1 SEL NC IN2

16-Pin MLF™ (MLF-16)

Ordering Information ^(1)

Part Number Type Range	Package Operating Package Lead
	Marking	Finish
SY89834UMI	MLF-16	Industrial	834U	Sn-Pb
SY89834UMITR(2)	MLF-16	Industrial	834U	Sn-Pb
SY89834UMG(3)	MLF-16	Industrial	834U with Pb-Free bar line indicator	NiPdAu Pb-Free
SY89834UMGTR(2, 3)	MLF-16	Industrial	834U with Pb-Free bar line indicator	NiPdAu Pb-Free

Notes:

1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ , DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.

PIN DESCRIPTION

Pin Number	Pin Name Pin Function
15, 161, 2,3, 4,5, 6	Q0, /Q0Q1, /Q1Q2, /Q2Q3, /Q3	Differential 100K LVPECL Outputs: These LVPECL outputs are the precision, low skew copies of the inputs. Please refer to the “Truth Table” section for details. Unused output pairs may be left open. Terminate with 50 to V_CC - 2V . See “Output Termination Recommendations” section for more details.
8	EN	This single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The synchronous enable ensures that enable/disable will only occur when the outputs are in a logic LOW state. Note that this input is internally connected to a 25k pull-up resistor and will default to logic HIGH state (enabled) if left open.
12,9	IN1IN2	Single-ended TTL/CMOS-compatible inputs to the device. These inputs are internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. The input threshold is V_CC/2 .
10	NC	No connect. Not internally connected.
11	SEL	TTL/CMOS Compatible Select Input for signals IN1 and IN2. The input threshold is V_CC/2 . HIGH at the SEL input selects signal IN1. LOW at the SEL input selects signal IN2. SEL includes a 25k pull-up resistor. The default state is HIGH when left floating.
13	GND	Ground. GND pins and exposed pad must be connected to the most negative potential of the device ground.
7, 14	VCC	Positive Power Supply: Bypass with 0.1 F//0.01 F low ESR capacitors and place as close to each VCC pin as possible.

TRUTH TABLE

IN1 IN2 EN SEL		Q0-Q3 /Q0-Q3
0	X	1	1	0
1	X	1	1	1
X	0	1	0	0
X	1	1	0	1
X	X	0	X	0^(1)	0^(1)

Note:

1. On next negative transition of the input signal (IN).

Absolute Maximum Ratings ^(1)

Supply Voltage (V _CC ) ...... -0.5V to +4.0V

Input Voltage ( V_IN ) -0.5V to V_CC + 0.3V

LVPECL Output Current ( I_OUT ) Continuous ....50mA Surge....100mA

Input Current (IN1, IN2) ....±50mA

Lead Temperature (Soldering, 20sec.), 260°C

Storage Temperature ( T_S ) -65^ to +150^

Operating Ratings ^(2)

Supply Voltage Range ....+2.375V to +2.625V ....+3.0V to +3.6V

Ambient Temperature ( T_A ) -40^ to +85^

Package Thermal Resistance ^(3) MLF ^TM ( _JA )

Still-Air 60°C/W

MLF ^TM ( _JB ) Junction-to-Board ....32°C/W

DC ELECTRICAL CHARACTERISTICS ^(4)

T_A = -40^ to +85^ , unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units
V_CC	Power Supply 2.375 2.625 V		3.0		3.6	V
I_CC	Power Supply Current	No load, max. V_CC .		50	75	mA

LVTTL/CMOS INPUTS DC ELECTRICAL CHARACTERISTICS ^(4)

V_CC = 2.5V ± 5% or V_CC = 3.3V ± 10% ; T_A = -40^ C to +85^ C , unless otherwise stated.

Symbol Parameter Condition Min Typ Max		Units
V_IH	Input HIGH Voltage		2.0			V
V_IL	Input LOW Voltage				0.8 V
I_IH	Input HIGH Current	I_IH @ V_IN = 2.7V	-125		30	A
I_IL	Input LOW Current		-125			A

(100KEP) LVPECL OUTPUTS DC ELECTRICAL CHARACTERISTICS ^(4)

V_CC = 2.5V ± 5% or V_CC = 3.3V ± 10% , R_L = 50 to V_CC - 2V ; T_A = -40^ C to +85^ C , unless otherwise stated.

Symbol Parameter Condition		Min	Typ Max Units
V_OH	Output HIGH Voltage			V_CC-1.145	V_CC-1.020	V_CC-0.895	V
V_OL	Output LOW Voltage			V_CC-1.945	V_CC-1.820	V_CC-1.695	V
V_OUT	Output Voltage Swing	See Figures 2a.		550	800	1050	mV
V_DIFF\_OUT	Differential Output Voltage Swing	See Figures 2b.		1100	1600	2100	mV

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JA and _JB values are determined for a 4-layer board in still-air, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC ELECTRICAL CHARACTERISTICS ^(5)

V_CC = 2.5V ± 5% or V_CC = 3.3V ± 10% , R_L = 50 to V_CC - 2V ; T_A = -40^ to +85^ , unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units
f_MAX	Maximum Frequency Input t	r/t_f ≥ 350 ps 1.0 GHz
t_pd	Propagation Delay IN-to-Q Note 6 200	320 500 ps
t_SW	Switchover Time SEL-to-Q 200 320 500 ps
t_SKEW	Within-Device Skew	Note 7		5 20	ps
	Part-to-Part Skew	Note 8			300 ps
t_JITTER	DataRandom Jitter (RJ)Deterministic Jitter (DJ)	Note 9Note 10			110	ps_RMS ps_PP
	ClockCycle-to-Cycle JitterTotal Jitter (TJ)	Note 11Note 12			110	ps_RMS ps_PP
DC	Duty Cycle	Input t_f/t_f ≥ 350 ps , Note 13	45	50	55	%
t_S	Set-Up Time EN to IN1, IN Note 14 and Note 15	300			ps
t_H	Hold Time EN to IN1, IN	Note 14 and Note 15	500			ps
t_r, t_f	Output Rise/Fall Times(20% to 80%)		70	140 22	5 ps

Notes:

1. High-frequency AC parameters are guaranteed by design and characterization.
2. V_IH = 2.0V , V_IL = 0.8V , 50% duty cycle. Delay measured at 100MHz from the crossing of the input signal with V_CC/2 as the crossing of the differential output signal. See Figure 1.
3. Within device skew is measured between two different outputs under identical input transitions.
4. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs.
5. Random jitter is measured with a K28.7 pattern, measured at ≤ f_MAX .
6. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2^23-1 PRBS pattern.
7. Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs. T_JITTER CC = T_n - T_n+1 , where T is the time between rising edges of the output signal.
8. Total jitter definition: with an ideal clock input frequency of ≤ f_MAX (device), no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value.
9. If t_r / 14 is less than 350ps, the duty cycle distortion will increase beyond the duty cycle limits.
10. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications set-up and hold times do not apply.
11. See "Timing Diagrams," Figure 1a.

TIMING DIAGRAMS

EN VCC/2 VCC/2 VIN IN VCC/2 VCC/2 VCC/2 VCC/2 tS tH tpd tpd /Q Q VOUT

Figure 1a. Timing Diagram (EN, IN1, IN2)

IN2 HIGH IN1 LOW SEL Vcc/2 Vcc/2 /Q tSWITCHOVER tSWITCHOVER Q VOUT

Figure 1b. Timing Diagram (SEL)

SINGLE-ENDED AND DIFFERENTIAL SWINGS

VOUT

Figure 2a. Single-Ended Swing

V DIFF_OUT

Figure 2b. Differential Swing

TYPICAL OPERATING CHARACTERISTICS

V_CC = 3.3V, GND = 0V, R_L = 50 to V_CC - 2V; T_A = 25^, unless otherwise stated.

FUNCTIONAL CHARACTERISTICS

V_CC = 3.3V, GND = 0V, R_L = 50 to V_CC - 2V, T_A = 25^, unless otherwise stated.

155MHz Output

TIME (1ns/div.)

622MHz Output

TIME (321.9ps/div.)

1GHz Output

TIME (200ps/div.)

DIFFERENTIAL INPUT

Vcc 25k IN1 IN2 SEL EN R R GND

Figure 3. Simplified TTL/CMOS Input Buffer

RELATED PRODUCTS AND SUPPORT DOCUMENTATION

Part Number Function Data Sheet Link
SY89830U 2.5V	/3.3V/5V 2.5GHz 1:4 PECL/ECL http://www.micrel.com/product-info/products/sy89830u.shtmlClock Driver with 2:1 Differential Input Mux
SY89831U Ultra	-Precision 1:4 LVPECL Fanout Buffer/ http://www.micrel.com/product-info/products/sy89831u.shtmlTranslator with Internal Termination
SY89832U 2.5V	Ultra-Precision 1:4 LVDS Fanout Buffer/ http://www.micrel.com/product-info/products/sy89832u.shtmlTranslator with Internal Termination
SY89833U 3.3V	Ultra-Precision 1:4 LVDS Fanout Buffer/ http://www.micrel.com/product-info/products/sy89833u.shtmlTranslator with Internal Termination
	16-MLFTM Manufacturing GuidelinesExposed Pad Application Note MLF-appnote-0301.pdf	http://www.amkor.com/products/notes-papers/
HBW Solutions	New Products + Termination App Note	http://www.micrel.com/product-info/as/solutions.shtml

TERMINATION RECOMMENDATIONS

+3.3V Z₀ = 50Ω Z₀ = 50Ω R1 130Ω +3.3V R1 130Ω +3.3V R2 82Ω R2 82Ω Vₜ = Vₓₓ -2V

Figure 4a. Parallel Termination—Thevenin Equivalent

Note:

1. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω
   For +3.3V systems: R1 = 130Ω, R2 = 82Ω

+3.3V +3.3V Z = 50Ω Z = 50Ω "source" 50Ω 50Ω 50Ω Rb Vcc "C1 0.01μF (optional) "destination"

Figure 4b. Three-Resistor "Y-Termination"

Notes:

1. Power-saving alternative to Thevenin termination.
2. Place termination resistors as close to destination inputs as possible.
3. R_b resistor sets the DC bias voltage, equal to V_t . For +3.3V systems R_b=50 . For +2.5V systems R_b=19 .

+3.3V +3.3V R1 130Ω Zo = 50Ω +3.3V R1 130Ω R3 1kΩ Vt = VCC -1.3V +3.3V R2 82Ω R4 1.6kΩ Vt = VCC -2V +Q -VCC

Figure 4c. Terminating Unused LVPECL I/O

Notes:

1. Unused output (/Q) must be terminated to balance the output.
2. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω, R3 = 1.25kΩ, R4 = 1.2kΩ.
3. Unused output pairs (Q and /Q) may be left floating.

16 LEAD EPAD MicroLeadFrame™ (MLF-16)

Pin 1 Dot By Marking 3.000±0.050 3.000±0.050

TOP VIEW

PIN #1 IDENTIFICATION CHAMFER 0.300 X 45° 1.550±0.050 Exp. DAP 0.400±0.050 1.550±0.050 Exp. DAP 0.500 Bsc 0.230±0.050 0.400±0.050 1.500 Ref.

BOTTOM VIEW

0.850±0.050 0.000-0.050 0.203±0.025

SIDE VIEW
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm.
3. MAXIMUM ALLOWABE BURRS IS 0.076 mm IN ALL DIRECTIONS.
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.

Package EP- Exposed Pad Dia CompSide Island Heat Dissipation Heat Dissipation Heavy Copper Plane V_EF V_LL

PCB Thermal Consideration for 16-Pin MLF™ Package (Always solder, or equivalent, the exposed pad to the PCB.)

Package Notes:

Note 1. Package meets Level 2 moisture sensitivity classification, and are shipped in dry-pack form.
Note 2. Exposed pads must be soldered to a ground for proper thermal management.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

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The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

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