SY89833L - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY89833L Microchip

The SY89833L is a 3.3V, high-speed 2GHz differential low voltage differential swing (LVDS) 1:4 fanout buffer optimized for ultra-low skew applications. Within device skew is guaranteed to be less than 20ps over supply voltage and temperature.

The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications.

The SY89833L is part of Micrel's high-speed clock synchronization family. For 2.5V applications, the SY89832U provides similar functionality while operating from a 2.5V ±5% supply. For applications that require a different I/O combination, consult the Micrel website at www.micrel.com, and choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators and clock generators.

Datasheets and support documentation are available on Micrel's web site at: www.micrel.com.

Features

- Guaranteed AC performance over temperature and voltage:

- DC-to > 2GHz throughput

- <600ps propagation delay (IN-to-Q)

- <20ps within-device skew

- <150ps rise/fall times

- Ultra-low jitter design:

- 98fs _RMS phase jitter

- Patented Any-In input termination and VT pin accepts DC- and AC-coupled inputs

• High-speed LVDS outputs

• 3.3V power supply operation:

- Industrial temperature range: -40°C to +85°C

• Available in 16-pin (3mm × 3mm) QFN package

Applications

- Processor clock distribution

• SONET clock distribution

• Fibre Channel clock distribution

• Gigabit Ethernet clock distribution

Functional Block Diagram

graph TD
    IN["IN 50Ω"] --> A["NOT"]
    VT["VT 50Ω"] --> A
    IN --> B["NOT"]
    VREF-AC["VREF-AC"] --> A
    EN["(LVTTL/CMOS)"] --> A
    A --> D["D Flip-Flop"]
    D --> Q["Q"]
    Q --> Q0["Q0"]
    Q --> Q1["Q1"]
    Q --> Q2["Q2"]
    Q --> Q3["Q3"]
    Q0 --> Q0_out["1:4"]
    Q1 --> Q1_out
    Q2 --> Q2_out
    Q3 --> Q3_out

Typical Performance

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Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • http://www.micrel.com

Ordering Information ^(1)

Part Number	Package Type	Operating Range	Package Marking	Lead Finish
SY89833LMG	QFN-16	Industrial	833L with Pb-Free Bar Line Indicator	NiPdAuPb-Free
SY89833LMG TR(2)	QFN-16	Industrial	833L with Pb-Free Bar Line Indicator	NiPdAuPb-Free

Notes:

1. Contact factory for die availability. Dice are guaranteed at T_A=25^ , DC Electricals only.
2. Tape and Reel.

Pin Configuration

/Q0 Q0 VCC GND 16 15 14 13 Q1 1 12 IN /Q1 2 11 VT Q2 3 10 VREF-AC /Q2 4 9 /IN 5 6 7 8 Q3 /Q3 VCC EN

16-Pin 3mm × 3mm QFN

Pin Description

Pin Number	Pin Name	Pin Function
15, 16	Q0, /Q0
1, 2	Q1, /Q1	LVDS Differential Outputs: Normally terminated with 100Ω across the pair (Q, /Q). See “LVDS Outputs” section. Unused outputs should be terminated with a 100Ω resistor across each pair.
3, 4	Q2, /Q2
5, 6	Q3, /Q3
8 EN		This single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The synchronous enable ensures that enable/disable will only occur when the outputs are in a logic LOW state. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state (enabled) if left open.
9, 12 /IN, IN		Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept AC- or DC-Coupled differential signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50Ω. Note that these inputs will default to an intermediate state if left open. Please refer to the “Input Interface Applications” section for more details.
10 VREF-AC		Reference Voltage: These outputs bias to V_cc-1.4V . They are used when AC coupling the inputs (IN, /IN). For AC-Coupled applications, connect VREF-AC to VT pin and bypass with 0.01μF low ESR capacitor to V_cc . See “Input Interface Applications” section for more details. Maximum sink/source current is ±1.5mA. Due to the limited drive capability, each VREF-AC pin is only intended to drive its respective VT pin.
11 VT		Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT pins provide a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section for more details.
13 GND		Ground. GND pins and exposed pad must be connected to the most negative potential of the device ground.
7, 14 VCC		Positive Power Supply: Bypass with 0.1 F//0.01 F low ESR capacitors and place as close to each VCC pin as possible.

Truth Tables

IN /IN EN Q	/Q
0 1 1 0 1
1 0 1 1 0
X X 0	0		(3)	1^(3)

Note:

1. On next negative transition of the input signal (IN).

Absolute Maximum Ratings ^(4)

Supply Voltage ( V_cc )....-0.5V to +4.0V

Input Voltage ( V_IN )....-0.5 to VCC +0.3V

LVDS Output Current (IOUT)....+10mA

Input Current

Source or Sink Current on (I _VT )......±2mA

Maximum Operating Junction Temperature.... 125°C

Lead Temperature (Soldering, 20 s) 260°C

Storage Temperature ( T_s )....-65°C to +150°C

Operating Ratings ^(5)

Supply Voltage Range ....+3.0V to +3.6V

Ambient Temperature ( T_A ) -40^ to +85^

Junction Thermal Resistance ^(6)

QFN ( J A)

Still-Air 60°C/W

QFN (ΨJ B)....33°C/W

Electrical Characteristics ^(7)

T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min.	Typ.	Max.	Units
V_CC	Power Supply Voltage Range		3.0	3.3	3.6	V
I_CC	Power Supply Current	No load, maximum V_CC		75	100	mA
R_IN	Input Resistance (IN-to-VT)		45	50	55	Ω
R_DIFF-IN	Differential Input Resistance (IN-to-/IN)		90	100	110	Ω
V_IH	Input HIGH Voltage (IN-to-/IN)		0.1		V_CC + 0.3	V
V_IL	Input LOW Voltage (IN-to-/IN)		-0.3		V_IH - 0.1	V
V_IN	Input Voltage Swing (IN-to-/IN)	Note 8, see Figure 4.	0.1		V_CC	V
V_DIFF-IN	Differential Input Voltage	Note 8, see Figure 5.	0.2			V
|IIN|	Input Current (IN, /IN)	Note 8.			45	mA
V_REF-AC	Reference Voltage		V_CC - 1.525	V_CC - 1.425	V_CC - 1.325	V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB and _JA values are determined for a 4-layer board in still-air number, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. Due to the internal termination (see "Input Buffer Structure" section) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not apply a combination of voltages that causes the input current to exceed the maximum limit.

LVDS Outputs DC Electrical Characteristics ^(9)
V_CC = 3.3V ± 10% , R_L = 100 across the outputs; T_A = -40^ to +85^ .

Symbol	Parameter	Condition	Min.	Typ.	Max.	Units
V_OUT	Output Voltage Swing	See Figure 4.	250	325		mV
V_DIFF\_OUT	Differential Output Voltage Swing	See Figure 5.	500	650		mV
V_OCM	Output Common Mode Voltage		1.125		1.275	V
V_OCM	Change in Common Mode Voltage		-50		50	mV

Note:
9. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

LVTTL/CMOS DC Electrical Characteristics ^(9)
V_CC = 3.3V ± 10% , T_A = -40^ C to +85^ C .

Symbol	Parameter	Condition	Min.	Typ.	Max.	Units
V_IH	Input HIGH Voltage		2.0		V_CC	V
V_IL	Input LOW Voltage		0		0.8	V
I_IH	Input HIGH Current		-125		30	V
I_IL	Input LOW Current				-300	mV

AC Electrical Characteristics ^(10)
V_cc = 3.3V ± 10% , R_L = 100 across the outputs; T_A = -40^ C to +85^ C unless otherwise stated

Symbol	Parameter	Condition	Min	Typ	Max	Units
f_MAX	Maximum Frequency	V_OUT ≥ 200mV	2.0			GHz
t_pd	Propagation Delay IN-to-Q	V_IN < 400mV	400	500	600	ps
		V_IN ≥ 400mV	330	440	530	ps
t_SKEW	Within-Device Skew	Note 11		4	20	ps
	Part-to-Part Skew	Note 12			200	ps
t_S	Set-up Time EN to IN, /IN	Note 13	300			ps
t_H	Hold Time EN to IN, /IN	Note 13	500			ps
t_JITTER	Additive Jitter	Output = 622MHzIntegration Range: 12kHz – 20MHz		98		fs
t_r, t_f	Output Rise/Fall Times(20% to 80%)	At full output swing.	60	110	190	ps

Notes:
10. High-frequency AC parameters are guaranteed by design and characterization.
11. Within device skew is measured between two different outputs under identical input transitions.
12. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs.
13. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold times do not apply.

Timing Diagram

EN Vcc/2 Vcc/2 IN tS tH IN VIN /Q tpd Q tpd VOUT

Typical Characteristics

V_CC = 3.3V , GND = 0V, V_IN = 400mV , R_L = 100 across the outputs; T_A = 25^ unless otherwise stated.

Functional Characteristics

Additive Phase Noise Plot

Input Stage

VCC 1.86kΩ 1.86kΩ 1.86kΩ IN 50Ω VT 50Ω /IN GND

Figure 1. Simplified Differential Input Buffer

LVDS Outputs

LVDS specifies a small swing of 325mV typical, on a nominal 1.20V common mode above ground. The common-mode voltage has tight limits to permit large variations in ground noise between a LVDS driver and receiver.

VOUT 100Ω VOH' VOL VOH' VOL GND

Figure 2. LVDS Differential Measurement

50Ω 50Ω V_OCM' ΔV_OCM GND

Figure 3. LVDS Common Mode Measurement

VOUT, VIN 325mV (TYPICAL)

Figure 4. Single-Ended Swing

650mV V_DIFF_IN, V_DIFF_OUT

Figure 5. Differential Swing

Input Interface Applications

Vcc = 3.3V CML IN /IN NC □ VT NC □ VREF-AC SY89833L Vcc = 3.3V

Figure 6. DC-Coupled CML Input Interface

VCC = 3.3V CML IN /IN SY89833L VT VREF-AC 0.01μF VCC = 3.3V

Figure 7. AC-Coupled CML Input Interface

VCC = 3.3V VCC = 3.3V LVPECL IN /IN SY89833L VCC -2V VT VREF-AC 0.01μF 50Ω NC

Figure 8. DC-Coupled LVPECL Input Interface

Vcc = 3.3V LVPECL Rpd 100Ω Rpd 100Ω 0.01mF Vcc = 3.3V IN /IN SY89833L VT VREF-AC

Figure 9. AC-Coupled LVPECL Input Interface

Vcc = 3.3V LVDS IN /IN NC □ VT NC □ VREF-AC SY89833L Vcc = 3.3V

Figure 10. LVDS Input Interface

Vcc LVDS IN /IN SY58020U VT VREF-AC 0.01μF

Figure 11. AC-Coupled LVDS Input Interface Note: Be certain that the LVDS driver can be AC-coupled.

Package Information ^(14)

PIN 1 DOT BY MARKING 3.0000±0.050 1 2 3.0000±0.050

TOP VIEW NOTE: 1, 2, 3

PIN #1 IDENTIFICATION CHAMFER 0.300 X 45° 1.5500±0.050 Exp.DAP 0.5000 BSC 0.2300±0.050 1.5000 Ref. 1.5500±0.050 Exp.DAP 1 4000±0.050 2 1.5500±0.050 Ref.

BOTTOM VIEW NOTE: 1, 2, 3

0.850±0.050 0.000-0.050 0.2030±0.025

SIDE VIEW NOTE: 1, 2, 3

0.48±0.05 0.23±0.05 1.60±0.05 2.72±0.05 1.60±0.05 2.72±0.05 0.50 BSC

RECOMMENDED LAND PATTERN NOTE: 4, 5

NOTE:

1. MAX PACKAGE WARPAGE IS 0.05 MM

2. MAX ALLOWABLE BURR IS 0.076MM IN ALL DIRECTIONS

3. PIN #1 IS ON TOP WILL BE LASER MARKED

4. RED CIRCLE IN LAND PATTERN INDICATE THERMAL VIA

SIZE SHOULD BE 0.30-0.3M IN DIAMETER AND SHOULD BE

CONNECTED TO GND FOR MAX THERMAL PERFORMANCE

1. GREEN RECTANGLES (SHADED AREA) Indicate SOLDER

STENCIL OPENING ON EXPOSED PAD AREA. SIZE SHOULD BE

0.60×0.60 MM IN SIZE, 0.20 MM SPACING.

16-Pin 3mm × 3mm QFN (MM)

Note:

1. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL [phone] FAX [phone] WEB http://www.micrel.com

Micrel, Inc. is a leading global manufacturer of IC solutions for the worldwide high-performance linear and power, LAN, and timing & communications markets. The Company's products include advanced mixed-signal, analog & power semiconductors; high-performance communication, clock management, MEMs-based clock oscillators & crystal-less clock generators, Ethernet switches, and physical layer transceiver ICs. Company customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunications, automotive, and computer products. Corporation headquarters and state-of-the-art wafer fabrication facilities are located in San Jose, CA, with regional sales and support offices and advanced technology design centers situated throughout the Americas, Europe, and Asia. Additionally, the Company maintains an extensive network of distributors and reps worldwide.

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