SY89858U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY89858U Microchip

The SY89858U is a 2.5V/3.3V precision, high-speed, fully differential LVPECL 1:8 fanout buffer optimized to provide eight identical output copies with less than 30ps of skew and less than 10ps total jitter. It can process clock signals as fast as 2.0GHz.

The differential input includes Micrel's unique, 3-pin input termination architecture that allows the SY89858U to directly interface to LVPECL, CML, and LVDS differential signals (AC- or DC-coupled) as small as 100mV without any level shifting or termination resistor networks in the signal path. The result is a clean, stub-free, low-jitter interface solution. The LVPECL (100k temperature compensated) outputs feature 800mV typical swing into 50Ω loads, and provide fast rise/fall times guaranteed to be less than 200ps.

The SY89858U operates from a 2.5V ±5% supply or 3.3V ±10% supply and is guaranteed over the full industrial temperature range of -40°C to +85°C. For applications that require a higher speed fanout buffer, consider the SY58032U. The SY89858U is part of Micrel's high-speed, Precision Edge® product line. All support documentation can be found on Micrel's web site at: www.micrel.com.

Precision Edge®

Features

• Precision 1:8, LVPECL fanout buffer
• Low power: 238mW (2.5V)
• Guaranteed AC performance over temperature and supply voltage:
- Wide operating frequency: DC to 2.0GHz
- <380ps In-to-Out t_pd
- <200ps t_r / t_f
- <30ps skew

- Ultra-low jitter design: - 710fs RMS phase jitter (Typ)

• 100k LVPECL compatible outputs

• Fully differential inputs/outputs

- Accepts an input signal as low as 100mV (200mV _pp )

- Unique patent pending input termination and VT pin accepts DC-coupled and AC-coupled differential inputs (LVPECL, LVDS, and CML)

• Power supply 2.5V ±5% or 3.3V ±10%

- -40°C to +85°C industrial temperature range

• Available in 32-pin (5mm x 5mm) QFN package

Applications

• All SONET and GigE clock distribution
• All Fibre Channel clock and data distribution
• Network routing engine timing distribution
- High-end, low-skew multiprocessor synchronous clock distribution

Markets

• LAN/WAN
- Enterprise servers
- ATE
• Test and measurement

Precision Edge is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • http://www.micrel.com

Typical Application

1:8 LVPECL FOB IN 50Ω VT 50Ω /IN VREF-AC Q0 /Q0 Q1 /Q1 Q2 /Q2 Q3 /Q3 Q4 /Q4 Q5 /Q5 Q6 /Q6 Q7 /Q7

Ordering Information ^(1)

Part Number	Package Type	Operating Range	Package Marking	Lead Finish
SY89858UMG	QFN-32	Industrial	SY89858 with Pb-Free bar-line indicator	NiPdAu Pb-Free
SY89858UMGTR^(2)	QFN-32	Industrial	SY89858 with Pb-Free bar-line indicator	NiPdAu Pb-Free

Notes:

1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ C , DC Electricals Only.
2. Tape and Reel.

Pin Configuration

VCC Q0 /Q0 Q1 /Q1 Q2 /Q2 VCC 32 31 30 29 28 27 26 25 VCC 1 GND 2 IN 3 VT 4 VREF-AC 5 /IN 6 GND 7 VCC 8 VCC /Q7 Q7 Q6 Q5 Q4 Q3 /Q3 Q4 /Q4 VCC /Q7 Q7 Q6 Q5 Q4 Q3 /Q3 Q4 /Q4 VCC /Q7 Q7 Q6 Q5 Q4 Q3 /Q3 Q4 /Q4 VCC /Q7 Q7 Q6 Q5 Q4 Q3 /Q3 Q4 /Q4 VCC /Q7 Q7 Q6 Q5 Q4 Q3 /Q3 Q4 /Q4 VCC

32-Pin QFN

Pin Description

Pin Number	Pin Name	Pin Function
3, 6	IN, /IN	Differential Input: This differential input accepts AC- or DC-coupled signals as small as 100mV (200mV PP). Each pin of this pair internally terminates to a VT pin through 50. Note that these inputs will default to an indeterminate state if left open. Please refer to the “Input Interface Applications” section for more details.
4	VT	Input Termination Center-Tap: Each side of the differential input pair terminates to this VT pin. The VT pin provides a center-tap to a termination network fo maximum interface flexibility. See the “Input Interface Applications” section for more details.
5	VREF-AC	Reference Voltage: This output biases to V CC-1.2V (typical). It is used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01uF low ESR capacitor to V CC. Maximum sink/source capability is 1.5mA.
1, 8, 9, 16, 18, 23, 25, 32	VCC	Positive Power Supply: Bypass with 0.1 □F//0.01 □F low ESR capacitors as close to the VCC pins as possible.
31, 30, 29, 28, 27, 26, 22, 21, 20, 19, 15, 14, 13, 12, 11, 10	Q0, /Q0, Q1, /Q1, Q2, /Q2, Q3, /Q3, Q4, /Q4, Q5, /Q5, Q6, /Q6, Q7, /Q7	100k LVPECL Differential Outputs: Differential buffered output copy of the input signal. The LVPECL output swing is typically 800mV into 50Ω to VCC-2V. Unused output pairs may be left floating with no impact on jitter. See “LVPECL Output” section.
2, 7, 17, 24	GND Exposed Pad	Ground: Ground pins and exposed pad must be connected to the same ground plane.

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_cc ) -0.5V to +4.0V

Input Voltage ( V_IN ) ......-0.5V to V_CC

Termination Current

Source or sink current on V T ±100mA

Reference Current ^(3)

Source or sink current on V REF-AC .... ±1.5mA

LVPECL Output Current ( I_OUT )

Continuous .... 50mA Surge.... 100mA

Lead Temperature (soldering, 20 sec.) ..... +260°C

Storage Temperature ( T_s )....-65°C to 150°C

Operating Ratings ^(2)

Supply Voltage (Vcc)....+2.375V to +2.625V

......+3.0V to +3.6V

Ambient Temperature ( T_A )....-40°C to +85°C

Package Thermal Resistance ^(4)

QFN ( _JA ) Still-Air 35°C/W

QFN ( _JB ) Junction-to-Board 20°C/W

DC Electrical Characteristics ^(5)

T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_CC	Power Supply		2.375	2.5	2.625	V
			3.0	3.3	3.6	V
I_CC	Power Supply Current	No load, max. V_CC		95	150	mA
R_IN	Input Resistance (IN-to- V_T )		45	50	55	Ω
R_DIFF\_IN	Differential Input Resistance (IN-to-/IN)		90	100	110	Ω
V_IH	Input High Voltage (IN, /IN)	Note 6	V_CC -1.6		V_CC	V
V_IL	Input Low Voltage (IN, /IN)		0		V_IH-0.1	V
V_IN	Input Voltage Swing (IN, /IN)	See Figure 1a.	0.1		1.7	V
V_DIFF\_IN	Differential Input Voltage Swing |IN-/IN|	See Figure 1b.	0.2			V
V_T\_IN	IN-to- V_T (IN, /IN)				1.28	V
V_REF-AC	Output Reference Voltage		V_CC-1.3V	V_CC-1.2V	V_CC-1.1V	V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability use for input of the same package only.
4. Package Thermal Resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. _JA and _JB values are determined for a 4-layer board in still air, unless otherwise stated.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. V_IH (min) not lower than 1.2V.

LVPECL Outputs DC Electrical Characteristics ^(7)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C to +85^ C ; R_L = 50 to V_CC - 2V , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_OH	Output HIGH VoltageQ, /Q		V_CC-1.145		V_CC-0.895	V
V_OL	Output LOW VoltageQ, /Q		V_CC-1.945		V_CC-1.695	V
V_OUT	Output Voltage SwingQ, /Q	See Figure 1a.	500	800		mV
V_DIFF-OUT	Differential Output Voltage SwingQ, /Q	See Figure 1b.	1000	1600		mV

Note:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC Electrical Characteristics ^(8)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C to +85^ C , R_L = 50 to V_CC - 2V , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
f_MAX	Maximum Operating Frequency	V_OUT ≥ 400mV	2.0	3.0		GHz
t_PD	Propagation Delay (IN-to-Q)		180	260	380	ps
T_pd Tempco	Differential Propagation Delay Temperature Coefficient			115		fs/^
T_skew	Output-to-Output Skew	Note 9			30	ps
	Part-to-Part Skew	Note 10			150
t_Jitter	RMS Phase Jitter	Output = 25MHzIntegration Range 12kHz – 20MHz		710		fs
t_R, t_F	Output Rise/Fall Time(20% to 80%)	At full output swing.	75	130	200	ps

Notes:

1. High-frequency AC-parameters are guaranteed by design and characterization.
2. Output-to-output skew is measured between outputs under identical conditions.
3. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. Part-to-part skew includes variation in t_pd .

Typical Operating Characteristics

Functional Characteristics

Singled-Ended and Differential Swings

V_{IN}, V_{OUT} 800mV (typical)

Figure 1a. Single-Ended Voltage Swing

VDIFF_IN, VDIFF_OUT 1600mV (typical)

Figure 1b. Differential Voltage Swing

Timing Diagram

/IN IN /Q Q tpd tpd VIN VOUT

Input and Output Stages

Vcc IN 50Ω VT 50Ω /IN GND

Figure 2a. Simplified Differential Input Stage

VCC I/Q Q

Figure 2b. Simplified LVPECL Output Stage

Input Interface Applications

VCC LVPECL GND VCC 0.1μF RP NC VREF-AC IN /IN VT Note: For 3.3V, Rp = 50Ω. For 2.5V, Rp = 19Ω. SY89858U

Figure 3a. LVPECL Interface (DC-Coupled)

VCC LVPECL GND RP Rp GND VCC 0.1μF IN /IN SY89858U VT VREF-AC For 3.3V, RP = 100Ω. For 2.5V, RP = 50Ω.

Figure 3b. LVPECL Interface (AC-Coupled)

VCC CML IN /IN SY89858U GND NC □ VT NC □ VREF-AC Option: may connect VT to VCC

Figure 3c. CML Interface (DC-Coupled)

Vcc CML GND Vcc 0.01μF IN /IN VT VREF-AC SY89858U

Figure 3d. CML Interface (AC-Coupled)

VCC LVDS GND IN /IN SY89858U NC □ VT NC □ VREF-AC

Figure 3e. LVDS Interface (DC-Coupled)

VCC LVDS GND IN /IN SY89858U VCC VT VREF-AC 0.01μF

Figure 3f. LVDS Interface (AC-Coupled)

LVPECL Output Interface Applications

LVPECL has high input impedance, and very low output impedance (open emitter), and small signal swing which results in low EMI. LVPECL is ideal for driving 50Ω and 100Ω controlled impedance transmission lines. There are several techniques for terminating the LVPECL output: Parallel

Termination-Thevenin Equivalent, Parallel Termination (3-resistor), and AC-coupled Termination. Unused output pairs may be left floating. However, single-ended outputs must be terminated, or balanced.

+3.3V Z₀ = 50Ω Z₀ = 50Ω For +2.5V systems, R1 = 250Ω, R2 = 62.5Ω +3.3V R1 130Ω R1 130Ω R2 82Ω R2 82Ω VT = VCC -2V

Figure 4a. Parallel Termination-Thevenin Equivalent

+3.3V Z = 50Ω Z = 50Ω "source" 50Ω 50Ω Rb +3.3V "destination" Vcc C1 (optional) 0.01μF Notes:

Notes:

1. Power-saving alternative to Thevenin termination

2. Place termination resistors as close to destination inputs as possible.

3. R_b resistor sets the DC bias voltage, equal to V_T

4. For 2.5V systems, R_b = 19 , For 3.3V systems, R_b = 50

Figure 4b. Parallel Termination (3-Resistor)
Related Product and Support Documentation

Part Number	Function	Datasheet Link
SY58032U	Ultra-Precision 1:8 LVPECL Fanout Buffer w/Internal Termination	www.micrel.com/product-info/products/sy58032u.shtml
HBW Solutions	New Products and Applications	www.micrel.com/product-info/products/solutions.shtml

Package Information

5.0 BSC 32 1 2 PIN #1 ID 0.20 DIA TYP. 5.0 BSC

TOP VIEW

0.25±0.05 0.50 BSC 32 PIN #1 ID RO.20 0.20 MIN. 3.10±0.10 0.40±0.05 4X 3.10±0.10

BOTTOM VIEW

0.05 C 0.85±0.05 SEATING PLANE 0.00~0.05 0.20 REF

SIDE VIEW

NOTE:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. MAX. PACKAGE WARPAGE IS 0.05 nm.

3. MAXIMUM ALLOWABE BURRS IS 0.076 mm IN ALL DIRECTIONS

4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.

DIMENSION APPLIES TO METALIZED TERMINAL AND IS MEASURED BETWEEN 0.20 AND 0.25 mm FROM TERMINAL TIP.

1. APPLIED ONLY FOR TERMINALS.

APPLIED FOR EXPOSED PAD AND TERMINALS.

32-Pin (5mm x 5mm)

Package Notes:

1. Package meets Level 2 Moisture Sensitivity Classification.
2. All parts are dry-packaged before shipment.
3. Exposed pad must be soldered to a ground for proper thermal management.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL [phone] FAX [phone] WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

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