AT89LP428 - Electronic component Microchip - Free user manual and instructions

USER MANUAL AT89LP428 Microchip

• 8-bit Microcontroller Compatible with MCS ^® 51 Products
  • Enhanced 8051 Architecture

– Single-clock Cycle per Byte Fetch
- Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
- On-chip 2-cycle Hardware Multiplier
- 256 x 8 Internal RAM
- 512 x 8 Internal Extra RAM
– Dual Data Pointers
- 4-level Interrupt Priority

• Nonvolatile Program and Data Memory

• 4K/8K Bytes of In-System Programmable (ISP) Flash Program Memory
• 512/1024 Bytes of Flash Data Memory
• Endurance: Minimum 100,000 Write/Erase Cycles (for Both Program/Data Memories)
  – Serial Interface for Program Downloading
• 64-byte Fast Page Programming Mode
• 128-byte User Signature Array
• 2-level Program Memory Lock for Software Security
  – In-Application Programming of Program Memory

- Peripheral Features

– Three 16-bit Enhanced Timer/Counters
- Two 8-bit PWM Outputs
- 4-channel 16-bit Compare/Capture/PWM Array
- Enhanced UART with Automatic Address Recognition and Framing Error Detection
- Enhanced Master/Slave SPI with Double-buffered Send/Receive
- Programmable Watchdog Timer with Software Reset
– Dual Analog Comparators with Selectable Interrupts and Debouncing
- 8 General-purpose Interrupt Pins

- Special Microcontroller Features

• 2-wire On-chip Debug Interface
  – Brown-out Detection and Power-on Reset with Power-off Flag
• Active-low External Reset Pin
• Internal RC Oscillator
  – Low Power Idle and Power-down Modes
• Interrupt Recovery from Power-down Mode

- I/O and Packages

• Up to 30 Programmable I/O Lines
• 28-lead PDIP or 32-lead TQFP/PLCC/MLF
• Configurable I/O Modes

• Quasi-bidirectional (80C51 Style)
- Input-only (Tristate)
- Push-pull CMOS Output
- Open-drain

- Operating Conditions

• 2.4V to 5.5V Vcc Voltage Range
• -40°C to 85°C Temperature Range
• 0 to 20 MHz @ 2.4-5.5V
• 0 to 25 MHz @ 4.0-5.5V

ATMEL®

8-bit

Microcontroller with 4K/8K

Bytes In-System

Programmable

Flash

AT89LP428

AT89LP828

1. Pin Configurations

1.1 28P3 - 28-lead PDIP

AIN1/P2.5 1 28 P2.6/AIN2 AIN0/P2.4 2 27 P2.7/AIN3 RXD/P3.0 3 26 P1.7/SCK TXD/P3.1 4 25 P1.6/MISO XTAL2/P4.1 5 24 P1.5/MOSI XTAL1/P4.0 6 23 P1.4/SS GND 7 22 P1.3 INT0/P3.2 8 21 VCC INT1/P3.3 9 20 P1.2 T0/P3.4 10 19 P1.1/T2EX T1/P3.5 11 18 P1.0/T2 RST/P3.6 12 17 P3.7 CCD/P2.3 13 16 P2.0/CCA CCC/P2.2 14 15 P2.1/CCB

1.3 32J - 32-lead PLCC

XTAL2/P4.1 5 XTAL1/P4.0 6 P4.5 7 GND 8 P4.4 9 INT0/P3.2 10 INT1/P3.3 11 T0/P3.4 12 T1/P3.5 13 RST/P3.6 14 CCD/P2.3 15 CCC/P2.2 16 CCB/P2.1 17 CCA/P2.0 18 P3.7 19 P3.0/RXD 20 P2.4/AIN0 21 P2.5/AIN1 22 P2.6/AIN2 23 P2.7/AIN3 24 P1.7/SCK 25 P1.6/MISO 26 P1.5/MOSI 27 P1.4/SS 28 P1.3 29 P4.2 30 VCC 31 P4.3 32 P1.2 33 P1.1/T2EX 34 T2/P1.0

1.2 32A - 32-lead TQFP (Top View)

P3.1/TXD P3.0/RXD P2.4/AIN0 P2.5/AIN1 P2.6/AIN2 P2.7/AIN3 P1.7/SCK P1.6/MISO 32 31 30 29 28 27 26 25 XTAL2/P4.1 1 XTAL1/P4.0 2 P4.5 3 GND 4 P4.4 5 INT0/P3.2 6 INT1/P3.3 7 T0/P3.4 8 9 10 11 12 13 14 15 16 T1/P3.5 17 P1.1/T2EX RST/P3.6 18 P1.2 CCD/P2.3 19 P4.3 CCC/P2.2 20 VCC CCB/P2.1 21 P4.2 CCA/P2.0 22 P1.3 P3.7/T2/ P1.0

1.4 32M1-A - 32-pad MLF (Top View)

P3.1/TXD P3.0/RXD P2.4/AIN0 P2.5/AIN1 P2.6/AIN2 P2.7/AIN3 P1.7/SCK P1.6/MISO 32 31 30 29 28 27 26 25 XTAL2/P4.1 1 XTAL1/P4.0 2 P4.5 3 GND 4 P4.4 5 INT0/P4.3 6 INT1/P4.4 7 T0/P3.4 8 NOTE: Bottom pad should be soldered to ground 24 P1.5/MOSI 23 P1.4/SS 22 P1.3 21 P4.2 20 VDD 19 P4.3 18 P1.2 17 P1.1/T2EX 9 T1/P3.5 10 RST/P3.6 11 CCD/P2.3 12 CCC/P2.2 13 CCB/P2.1 14 CCA/P2.0 15 P3.7T2/ P1.0 P1.0

1.5 Pin Description

Table 1-1. AT89LP428/828 Pin Description

Pin Number			Symbol	Type Description
TQFP/MLF	PLCC PDIP
1	5	5	P	I/O04O I/O	P4.1: User-configurable I/O Port 4 bit 1.XTAL2: Output from inverting oscillator amplifier. It may be used as a port pin if the internal RC oscillator is selected as the clock source.CLKOUT: When the internal RC oscillator is selected as the clock source, may be used to output the internal clock divided by 2.DDA: Serial Data input/output for On-chip Debug Interface when OCD is enabled and the external clock is selected as the clock source.
2	6	6	P	I/O14 I/O	P4.0: User-configurable I/O Port 4 bit 0.XTAL1: Input to the inverting oscillator amplifier and internal clock generation circuits. It may be used as a port pin if the internal RC oscillator is selected as the clock source.DDA: Serial Data input/output for On-chip Debug Interface when OCD is enabled and the internal RC oscillator is selected as the clock source.
3	7	N/A	P4.5	I/O	P4.5: User-configurable I/O Port 4 bit 5.
4	8	7	GND	I	Ground
5	9	N/A	P4.4	I/O	P4.4: User-configurable I/O Port 4 bit 4.
6	10	8	P3.2	I/O1	P3.2: User-configurable I/O Port 3 bit 2.INT0: External Interrupt 0 Input or Timer 0 Gate Input.
7	11	9	P3.3	I/O1	P3.3: User-configurable I/O Port 3 bit 3.INT1: External Interrupt 1 Input or Timer 1 Gate Input
8	12	10	P3.4	I/O1/O	P3.4: User-configurable I/O Port 3 bit 4.T1: Timer/Counter 0 External input or PWM output.
9	13	11	P3.5	I/O1/O	P3.5: User-configurable I/O Port 3 bit 5.T1: Timer/Counter 1 External input or PWM output.
10 14	12	P3.6		I/O11	P3.6: User-configurable I/O Port 3 bit 6 (if Reset Fuse is disabled).RST: External Active-low Reset input (if Reset Fuse is enabled, see “External Reset” on page 26).DCL: Serial Clock input for On-chip Debug Interface when OCD is enabled.
11 15	13	P2.3		I/O1/O	P2.3: User-configurable I/O Port 2 bit 3.CCD: Timer 2 Channel D Compare Output or Capture Input.
12 16	14	P2.1		I/O1/O	P2.2: User-configurable I/O Port 2 bit 2.CCC: Timer 2 Channel C Compare Output or Capture Input.
13 17	15	P2.1		I/O1/O	P2.1: User-configurable I/O Port 2 bit 1.CCB: Timer 2 Channel B Compare Output or Capture Input.
14 18	16	P2.0		I/O1/O	P2.0: User-configurable I/O Port 2 bit 0.CCA: Timer 2 Channel A Compare Output or Capture Input.
15 19	17	P3.7		I/O1/O	P3.7: User-configurable I/O Port 3 bit 7.DDA: Serial Data input/output for On-chip Debug Interface when OCD is enabled and the Crystal oscillator is selected as the clock source.
16 20	18	P1.0		I/O1/O	P1.0: User-configurable I/O Port 1 bit 0.T2: Timer 2 External Input or Clock Output.GPI0: General-purpose Interrupt input 0.
Pin Number			Symbol	Type	Description
TQFP/MLF	PLCC	PDIP
17 21	19 P1.1			I/O|I	P1.1:User-configurable I/O Port 1 bit 1.T2EX:Timer 2 External Capture/Reload Input.GPI1:General-purpose Interrupt input 1.
18 22	20 P1.2			I/O|	P1.2:User-configurable I/O Port 1 bit 2.GPI2:General-purpose Interrupt input 2.
19	23	N/A	P4.3	I/O	P4.3:User-configurable I/O Port 4 bit 3.
20	24	21	VCC	I	Supply Voltage.
21	25	N/A	P4.2	I/O	P4.2:User-configurable I/O Port 4 bit 2.
22 26	22 P1.3			I/O|	P1.3:User-configurable I/O Port 1 bit 3.GPI3:General-purpose Interrupt input 3.
23 27	23 P1.4			I/O|I	P1.4:User-configurable I/O Port 1 bit 4.SS:SPI Slave-select.GPI6:General-purpose Interrupt input 4.
24 28	24 P1.5			I/O|I/O	P1.5:User-configurable I/O Port 1 bit 5.MOSI:SPI master-out/slave-in. When configured as master, this pin is an output.When configured as slave, this pin is an input.GPI5:General-purpose Interrupt input 5.
25 29	25 P1.6			I/O|I/O	P1.6:User-configurable I/O Port 1 bit 6.MISO:SPI master-in/slave-out. When configured as master, this pin is an input.When configured as slave, this pin is an output.GPI6:General-purpose Interrupt input 6.
26 30	26 P1.7			I/O|I/O	P1.7:User-configurable I/O Port 1 bit 7.SCK:SPI Clock. When configured as master, this pin is an output. Whenconfigured as slave, this pin is an input.GPI7:General-purpose Interrupt input 7.
27 31	27 P2.6			I/O|	P2.6:User-configurable I/O Port 2 bit 6.AIN2:Analog Input 2.
28 32	28 P2.7			I/O|	P2.7:User-configurable I/O Port 2 bit 7.AIN3:Analog Input 3.
29 1	P2.5			I/O|	P2.5:User-configurable I/O Port 2 bit 5.AIN1:Analog Input 1.
30 2	P2.4			I/O|	P2.4:User-configurable I/O Port 2 bit 5.AIN0:Analog Input 0.
31 3	P3.0			I/O|	P3.0:User-configurable I/O Port 3 bit 0.RXD:Serial Port Receiver Input.
32 4	P3.1			I/O|O	P3.1:User-configurable I/O Port 3 bit 1.TXD:Serial Port Transmitter Output.

2. Overview

The AT89LP428/828 is a low-power, high-performance CMOS 8-bit microcontroller with 4K/8K bytes of In-System Programmable Flash program memory and 512/1024 bytes of Flash data memory. The device is manufactured using Atmel ^® s high-density nonvolatile memory technology and is compatible with the industry-standard MCS51 instruction set. The AT89LP428/828 is built around an enhanced CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instructions to execute in 12, 24 or 48 clock cycles. In the AT89LP428/828 CPU, instructions need only 1 to 4 clock cycles providing 6 to 12 times more throughput than the standard 8051. Seventy percent of instructions need only as many clock cycles as they have bytes to execute, and most of the remaining instructions require only one additional clock. The enhanced CPU core is capable of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same current consumption. Conversely, at the same throughput as the classic 8051, the new CPU core runs at a much lower speed and thereby greatly reducing power consumption and EMI.

The AT89LP428/828 provides the following standard features: 4K/8K bytes of In-System Programmable Flash program memory, 512/1024 bytes of Flash data memory, 768 bytes of RAM, up to 30 I/O lines, three 16-bit timer/counters, up to six PWM outputs, a programmable watchdog timer, two analog comparators, a full-duplex serial port, a serial peripheral interface, an internal RC oscillator, on-chip crystal oscillator, and a four-level, ten-vector interrupt system. A block diagram is shown in Figure 2-1 on page 6.

Timer 0 and Timer 1 in the AT89LP428/828 are enhanced with two new modes. Mode 0 can be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit auto-reload timer/counter. In addition, the timer/counters may independently drive an 8-bit precision pulse width modulation output.

Timer 2 on the AT89LP428/828 serves as a 16-bit time base for a 4-channel Compare/Capture Array with up to four multi-phasic, variable precision PWM outputs.

The enhanced UART of the AT89LP428/828 includes Framing Error Detection and Automatic Address Recognition. In addition, enhancements to Mode 0 allow hardware accelerated emulation of half-duplex SPI or 2-wire interfaces.

The I/O ports of the AT89LP428/828 can be independently configured in one of four operating modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input-only mode, the ports are tristated. Push-pull output mode provides full CMOS drivers and open-drain mode provides just a pull-down. In addition, all 8 pins of Port 1 can be configured to generate an interrupt using the General-purpose Interrupt (GPI) interface.

2.1 Block Diagram

Figure 2-1. AT89LP428/828 Block Diagram

graph TD
    A["4K/8K Bytes Flash Code"] <--> B["8051 Single Cycle CPU"]
    C["512/1K Bytes Flash Data"] <--> B
    D["256 Bytes RAM"] <--> B
    E["512 Bytes ERAM"] <--> B
    B --> F["General-purpose Interrupt"]
    B --> G["Port 1 Configurable I/O"]
    B --> H["Port 2 Configurable I/O"]
    B --> I["Port 3 Configurable I/O"]
    B --> J["Port 4 Configurable I/O"]
    B --> K["POR BOD"]
    B --> L["Crystal or Resonator"]
    B --> M["Configurable Oscillator"]
    B --> N["Internal RC Oscillator"]
    B --> O["UART"]
    B --> P["SPI"]
    B --> Q["Timer 0 Timer 1"]
    B --> R["Timer 2"]
    B --> S["Compare/Capture Array"]
    B --> T["Dual Analog Comparators"]
    B --> U["Watchdog Timer"]
    B --> V["On-chip Debug"]

2.2 Comparison to Standard 8051

The AT89LP428/828 is part of a family of devices with enhanced features that are fully binary compatible with the MCS-51 instruction set. In addition, most SFR addresses, bit assignments, and pin alternate functions are identical to Atmel's existing standard 8051 products. However, due to the high performance nature of the device, some system behaviors are different from those of Atmel's standard 8051 products such as AT89S52 or AT89S2051. The major differences from the standard 8051 are outlined in the following paragraphs and may be useful to users migrating to the AT89LP428/828 from older devices.

2.2.1 System Clock

The maximum CPU clock frequency equals the externally supplied XTAL1 frequency. The oscillator is not divided by 2 to provide the internal clock and x2 mode is not supported.

2.2.2 Reset

The RST pin of the AT89LP428/828 is active-low as compared with the active-high reset in the standard 8051. In addition, the RST pin is sampled every clock cycle and must be held low for a minimum of two clock cycles, instead of 24 clock cycles, to be recognized as a valid reset.

2.2.3 Instruction Execution with Single-cycle Fetch

The CPU fetches one code byte from memory every clock cycle instead of every six clock cycles. This greatly increases the throughput of the CPU. As a consequence, the CPU no longer executes instructions in 12, 24 or 48 clock cycles. Each instruction executes in only 1 to 4 clock cycles. See “Instruction Set Summary” on page 107 for more details.

2.2.4 Interrupt Handling

The interrupt controller polls the interrupt flags during the last clock cycle of any instruction. In order for an interrupt to be serviced at the end of an instruction, its flag needs to have been latched as active during the next to last clock cycle of the instruction, or in the last clock cycle of the previous instruction if the current instruction executes in only a single clock cycle.

The external interrupt pins, INT0 and INT1, are sampled at every clock cycle instead of once every 12 clock cycles. Coupled with the shorter instruction timing and faster interrupt response, this leads to a higher maximum rate of incidence for the external interrupts.

The Serial Peripheral Interface (SPI) has a dedicated interrupt vector. The SPI no longer shares its interrupt with the Serial Port and the ESP (IE2.2) bit replaces SPIE (SPCR.7).

2.2.5 Timer/Counters

By default Timer 0, Timer 1 and Timer 2 are incremented at a rate of once per clock cycle. This compares to once every 12 clocks in the standard 8051. A common prescaler is available to divide the time base for all timers and reduce the increment rate. The TPS 3-0 bits in the CLKREG SFR control the prescaler (Table 6-2 on page 23). Setting TPS 3-0 = 1011B will cause the timers to count once every 12 clocks.

The external Timer/Counter pins, T0, T1, T2 and T2EX, are sampled at every clock cycle instead of once every 12 clock cycles. This increases the maximum rate at which the Counter modules may function.

There is no difference in counting rate between Timer 2's Auto-reload/Capture and Baud Rate/Clock Out modes. All modes increment the timer once per clock cycle. Timer 2 in Baud Rate or Clock Out mode increments at twice the rate of standard 8051s. Setting TPS _3-0 = 0001B will force Timer 2 to count every two clocks.

2.2.6 Serial Port

The baud rate of the UART in Mode 0 defaults to 1/4 the clock frequency, compared to 1/12 the clock frequency in the standard 8051. In should also be noted that when using Timer 1 to generate the baud rate in UART Modes 1 or 3, the timer counts at the clock frequency and not at 1/12 the clock frequency. To maintain the same baud rate in the AT89LP428/828 while running at the same frequency as a standard 8051, the time-out period must be 12 times longer. Mode 1 of Timer 1 supports 16-bit auto-reload to facilitate longer time-out periods for generating low baud rates. Timer 2 generated baud rates are twice as fast in the AT89LP428/828 than on standard 8051s when operating at the same frequency.

2.2.7 Watchdog Timer

The Watchdog Timer in AT89LP428/828 counts at a rate of once per clock cycle. This compares to once every 12 clocks in the standard 8051. A common prescaler is available to divide the time base for all timers and reduce the counting rate.

2.2.8 I/O Ports

The I/O ports of the AT89LP428/828 may be configured in four different modes. By default all the I/O ports revert to input-only (tristated) mode at power-up or reset. In the standard 8051, all ports are weakly pulled high during power-up or reset. To enable 8051-like ports, the ports must be put into quasi-bidirectional mode by clearing the P1M0, P2M0, P3M0 and P4M0 SFRs. The user can also configure the ports to start in quasi-bidirectional mode by disabling the Tristate-Port User Fuse. When this fuse is disabled, P1M0, P2M0, P3M0 and P4M0 will reset to 00H instead of FFH and the ports will be weakly pulled high.

3. Memory Organization

The AT89LP428/828 uses a Harvard Architecture with separate address spaces for program and data memory. The program memory has a regular linear address space with support for up to 64K bytes of directly addressable application code. The data memory has 256 bytes of internal RAM and 128 bytes of Special Function Register I/O space. The AT89LP428/828 does not support external data memory or external program memory; however, portions of the external data memory space are implemented on chip as Extra RAM and nonvolatile Flash data memory. The memory address spaces of the AT89LP428 and AT89LP828 are listed in Tables 3-1 and 3-2.

Table 3-1. AT89LP428 Memory Address Spaces

Name Description Range
DATA	Directly addressable internal RAM	00H - 7FH
IDATA	Indirectly addressable internal RAM and stack space	00H - FFH
SFR	Directly addressable I/O register space	80H - FFH
EDATA	On-chip Extra RAM	0000H - 01FFH
FDATA	On-chip nonvolatile Flash data memory	0200H - 03FFH
CODE	On-chip nonvolatile Flash program memory	0000H - 0FFFH
SIG	On-chip nonvolatile Flash signature array	0000H - 00FFH

Table 3-2. AT89LP828 Memory Address Spaces

Name Description Range
DATA	Directly addressable internal RAM	00H - 7FH
IDATA	Indirectly addressable internal RAM and stack space	00H - FFH
SFR	Directly addressable I/O register space	80H - FFH
EDATA	On-chip Extra RAM	0000H - 01FFH
FDATA	On-chip nonvolatile Flash data memory	0200H - 05FFH
CODE	On-chip nonvolatile Flash program memory	0000H - 1FFFH
SIG	On-chip nonvolatile Flash signature array	0000H - 00FFH

3.1 Program Memory

The AT89LP428/828 contains 4K/8K bytes of on-chip In-System Programmable Flash memory for program storage. The Flash memory has an endurance of at least 100,000 write/erase cycles and a minimum data retention time of 10 years. The reset and interrupt vectors are located within the first 83 bytes of program memory (refer to Table 9-1 on page 30). Constant tables can be allocated within the entire 4K/8K program memory address space for access by the MOVC instruction. The AT89LP428/828 does not support external program memory. A map of the AT89LP428/828 program memory is shown in Figure 3-1.

Figure 3-1. Program Memory Map

graph TD
    A["AT89LP428"] --> B["User Signature Array"]
    C["AT89LP828"] --> D["User Signature Array"]
    E["Program Memory"] --> F["Atmel Signature Array"]
    G["Program Memory"] --> H["Atmel Signature Array"]
    I["00FF"] --> J["Program Memory"]
    K["0080"] --> L["Program Memory"]
    M["003F"] --> N["Program Memory"]
    O["0000"] --> P["Program Memory"]
    Q["SIGEN = 1"] --> R["Program Memory"]
    S["SIGEN = 0"] --> T["Program Memory"]

3.1.1 SIG

In addition to the 4K/8K code space, the AT89LP428/828 also supports a 128-byte User Signature Array and a 64-byte Atmel Signature Array that are accessible by the CPU. The Atmel Signature Array is initialized with the Device ID in the factory. The second page of the User Signature Array (00C0H - 00FFH) is initialized with analog configuration data including the Internal RC Oscillator calibration byte. The User Signature Array is also available for user identification codes or constant parameter data. Data stored in the signature array is not secure. Security bits will disable writes to the array; however, reads by an external device programmer are always allowed.

In order to read from the signature arrays, the SIGEN bit (DPCF.3) must be set. While SIGEN is one, MOVC A,@A+DPTR will access the signature arrays. The User Signature Array is mapped from addresses 0080H to 00FFH and the Atmel Signature Array is mapped from addresses 0000H to 003FH. SIGEN must be cleared before using MOVC to access the code memory. The User Signature Array may also be modified by the In-Application Programming interface. When IAP = 1 and SIGEN = 1, MOVX @DPTR instructions will access the array.

3.2 Internal Data Memory

The AT89LP428/828 contains 256 bytes of general SRAM data memory plus 128 bytes of I/O memory mapped into a single 8-bit address space. Access to the internal data memory does not require any configuration. The internal data memory has three address spaces: DATA, IDATA and SFR; as shown in Figure 3-2.

Figure 3-2. Internal Data Memory Map

3.2.1 DATA

The first 128 bytes of RAM are directly addressable by an 8-bit address (00H - 7FH) included in the instruction. The lowest 32 bytes of DATA memory are grouped into 4 banks of 8 registers each. The RS0 and RS1 bits (PSW.3 and PSW.4) select which register bank is in use. Instructions using register addressing will only access the currently specified bank.

3.2.2 IDATA

The full 256 bytes of internal RAM can be indirectly addressed using the 8-bit pointers R0 and R1. The first 128 bytes of IDATA include the DATA space. The hardware stack is also located in the IDATA space.

3.2.3 SFR

The upper 128 direct addresses (80H - FFH) access the I/O registers. I/O registers on AT89LP devices are referred to as Special Function Registers. The SFRs can only be accessed through direct addressing. All SFR locations are not implemented. See “Special Function Registers” on page 15.

3.3 External Data Memory

AT89LP microcontrollers support a 16-bit external data memory address space. The external memory space is accessed with the MOVX instructions. The AT89LP428/828 does not support an external memory interface. However, some internal data memory resources are mapped into portions of the external address space as shown in Figure 3-3. These memory spaces may require configuration before the CPU can access them. The AT89LP428/828 includes 512 bytes of on-chip Extra RAM (EDATA) and 512/1024 bytes of nonvolatile Flash data memory (FDATA).

Figure 3-3. External Data Memory Map

3.3.1 EDATA

The Extra RAM is a portion of the external memory space implemented as an internal 512-byte auxiliary RAM. The Extra RAM is mapped into the EDATA space at the bottom of the external memory address space, from 0000H to 01FFH. MOVX instructions to this address range will access the internal Extra RAM. EDATA can be accessed with both 16-bit (MOVX @DPTR) and 8-bit (MOVX @Ri) addresses. When 8-bit addresses are used, the PAGE register (086H) supplies the upper address bits. The PAGE register breaks EDATA into two 256-byte pages. A page cannot be specified independently for MOVX @R0 and MOVX @R1. When 16-bit addresses are used (DPTR), the IAP bit (MEMCON.7) must be zero to access EDATA. MOVX instructions to EDATA require a minimum of 2 clock cycles.

Table 3-3. PAGE – EDATA Page Register

PAGE = 86H Reset Value = XXXX XXX0BNot Bit Addressable
	-	-	-	-	-	-	-	P A
B	i	t	7	6	5	4	3	2 1

Symbol	Function
PAGE0	Selects which 256-byte page of EDATA is currently accessible by MOVX @Ri instructions.

3.3.2 FDATA

The Flash data memory is a portion of the external memory space implemented as an internal nonvolatile data memory. Flash data memory is enabled by setting the DMEN bit (MEMCON.3) to one. When IAP = 0 and DMEN = 1, the Flash data memory is mapped into the FDATA space, directly above the EDATA space near the bottom of the external memory address space. (Addresses 0200H-03FFH on AT89LP428 and 0200H-05FFH on AT89LP828. See Figure 3-3 on page 11). MOVX instructions to this address range will access the internal nonvolatile memory. FDATA is not accessible while DMEN = 0. FDATA can be accessed only by 16-bit (MOVX @DPTR) addresses. Addresses above the FDATA range are not implemented and should not be accessed. MOVX instructions to FDATA require a minimum of 4 clock cycles.

3.3.2.1 Write Protocol

The FDATA address space accesses an internal nonvolatile data memory. This address space can be read just like EDATA by issuing a MOVX A, @DPTR; however, writes to FDATA require a more complex protocol and take several milliseconds to complete. The AT89LP428/828 uses an idle-while-write architecture where the CPU is placed in an idle state while the write occurs. When the write completes, the CPU will continue executing with the instruction after the MOVX @DPTR,A instruction that started the write. All peripherals will continue to function during the write cycle; however, interrupts will not be serviced until the write completes.

To enable write access to the nonvolatile data memory, the MWEN bit (MEMCON.4) must be set to one. When MWEN = 1 and DMEN = 1, MOVX @DPTR,A may be used to write to FDATA. FDATA uses Flash memory with a page-based programming model. Flash data memory differs from traditional EEPROM data memory in the method of writing data. EEPROM generally can update a single byte with any value. Flash memory splits programming into write and erase operations. A Flash write can only program zeroes, i.e change ones into zeroes (1 0). Any ones in the write data are ignored. A Flash erase sets an entire page of data to ones so that all bytes become FFH. Therefore after an erase, each byte in the page can be written once with any possible value. Bytes can be overwritten without an erase as long as only ones are changed into zeroes. However, if even a single bit needs updating from zero to one (0 1); then the contents of the page must first be saved, the entire page must be erased and the zero bits in all bytes (old and new data combined) must be written. Avoiding unnecessary page erases greatly improves the endurance of the memory.

The AT89LP428/828 includes 8/16 data pages of 64 bytes each. One or more bytes in a page may be written at one time. The AT89LP428/828 includes a temporary page buffer of 64 bytes, so the maximum number of bytes written at one time is 64. The LDPG bit (MEMCON.5) allows multiple data bytes to be loaded to the temporary page buffer. While LDPG = 1, MOVX @DPTR,A instructions will load data to the page buffer, but will not start a write sequence. Note that a previously loaded byte must not be reloaded prior to the write sequence. To write the page into the memory, LDPG must first be cleared and then a MOVX @DPTR,A with the final data byte is issued. The address of the final MOVX determines which page will be written. If a MOVX @DPTR,A instruction is issued while LDPG = 0 without loading any previous bytes, only a single byte will be written. The page buffer is reset after each write operation. Figures 3-4 and 3-5 show the difference between byte writes and page writes.

Figure 3-4. FDATA Byte Write

DMEN MWEN LDPG IDLE tWC tWC MOVX

Figure 3-5. FDATA Page Write

DMEN MWEN LDPG IDLE MOVX twc

The auto-erase bit AERS (MEMCON.6) can be set to one to perform a page erase automatically at the beginning of any write sequence. The page erase will erase the entire page and then the bytes in the temporary buffer will be written to the selected page.

Frequently just a few bytes within a page must be updated while maintaining the state of the other bytes. There are two options for handling this situation that allow the Flash data memory to emulate a traditional EEPROM memory. The simplest method is to copy the entire page into a buffer allocated in RAM, modify the desired byte locations in the RAM buffer, and then load and write back the page to the Flash memory. This option requires that at least one page size of RAM is available as a temporary buffer. The second option is to load the unmodified bytes of the page directly into the Flash memory's temporary load buffer before loading the updated values of the modified bytes. For example, if just one byte needs modification, the user must first read and load the unaffected bytes of into the page buffer. Then the modified byte value is stored to the page buffer before starting the auto-erase sequence. This method reduces the amount of RAM required; however, more software overhead is needed because the read-and-load-back routine must skip those bytes in the page that need to be updated in order to prevent those locations in the buffer from being loaded with the previous data, as this will block the new data from being loaded correctly.

A write sequence will not occur if the Brown-out Detector (BOD) is active, even if the BOD reset has been disabled. In cases where the BOD reset is disabled, the user should check the BOD status by reading the WRTINF bit in MEMCON. If a write currently in progress is interrupted by the BOD due to a low voltage condition, the ABORT flag will be set. FDATA can always be read regardless of the BOD state.

For more details on using the Flash Data Memory, see the application note titled "AT89LP Flash Data Memory". FDATA may also be programmed by an external device programmer (see "Programming the Flash Memory" on page 115).

Table 3-4. MEMCON – Memory Control Register

MEMCON = 96H Reset Value = 0000 00XXBNot Bit Addressable
	IAP AER	SLDPG MWEN	DMEN ABORT - WRTINH
B	i	t	7	6	5	4	3	2

Symbol Function
IAP	In-Application Programming Enable. When IAP = 1 and the IAP Fuse is enabled, programming of the CODE/SIG space is enabled and MOVX @DPTR instructions will access CODE/SIG instead of EDATA or FDATA. Clear IAP to disable programming of CODE/SIG and allow access to EDATA and FDATA.
AERS	Auto-Erase Enable. Set to perform an auto-erase of a Flash memory page (CODE, SIG or FDATA) during the next write sequence. Clear to perform write without erase.
LDPG	Load Page Enable. Set to this bit to load multiple bytes to the temporary page buffer. Byte locations may not be loaded more than once before a write. LDPG must be cleared before writing.
MWEN	Memory Write Enable. Set to enable programming of a nonvolatile memory location (CODE, SIG or FDATA). Clear to disable programming of all nonvolatile memories.
DMEN	Data Memory Enable. Set to enable nonvolatile data memory and map it into the FDATA space. Clear to disable nonvolatile data memory.
ABORT	Abort Flag. Set by hardware if an error occurred during the last programming sequence due to a brownout condition (low voltage on V_CC ). Must be cleared by software.
WRTINH	Write Inhibit Flag. Cleared by hardware when the voltage on V_CC has fallen below the minimum programming voltage. Set by hardware when the voltage on V_CC is above the minimum programming voltage.

3.4 In-Application Programming (IAP)

The AT89LP428/828 supports In-Application Programming (IAP), allowing the program memory to be modified during execution. The IAP can be used to modify the user application on-the-fly or to use program memory for nonvolatile data storage. The same write protocol for FDATA also applies to IAP (see "Write Protocol" on page 12). The CPU is always placed in idle while modifying the program memory. When the write completes, the CPU will continue executing with the instruction after the MOVX @DPTR,A instruction that started the write.

To enable access to the program memory, the IAP bit (MEMCON.7) must be set to one and the IAP User Fuse must be enabled. The IAP User Fuse can disable all IAP operations. When this fuse is disabled, the IAP bit will be forced to 0. While IAP is enabled, all MOVX @DPTR instructions will access the CODE space instead of EDATA or FDATA. The IAP also allows reprogramming of the User Signature Array when SIGEN = 1. The IAP access settings are summarized in Table 3-5.

Table 3-5. IAP Access Settings

IAP	SIGEN	DMEN	MOVX @DPTR	MOVC @DPTR
0	0	0	EDATA	CODE
0	0	1	FDATA	CODE
0	1	0	EDATA	SIG
0	1	1	FDATA	SIG
1	0	X	CODE	CODE
1	1	X	SIG	SIG

4. Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 4-1.

Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write to these unlisted locations, since they may be used in future products to invoke new features.

Table 4-1. AT89LP428/828 SFR Map and Reset Values

	8	9	A	B	C	D	E	F
0F8H 0FFH
0F0H	B0000 0000
0E8H	SPSR000x x000	SPCR0000 0000	SPDRxxxx xxxx
0E0H	ACC0000 0000
0D8H 0DFH
0D0H	PSW0000 0000	T2CCA0000 0000	T2CCL0000 0000	T2CCH0000 0000	T2CCC0000 0000	T2CCF0000 0000
0C8H T2CON0000 0000	T2MOD0000 0000	RCAP2L0000 000	RCAP2H0000 0000	TL20000 000	TH20000 0000
0C0H	P4xx11 1111		P1M0^(2)	P1M10000 0000	P2M0^(2)	P2M10000 0000	P3M0^(2)	P3M10000 0000
0B8H	IP0000 0000	SADEN0000 0000					P4M0^(2)	P4M1xx00 0000
0B0H	P31111 1111				IE2xxxx x000	IP2xxxx x000	IP2Hxxxx x000	IPH0000 0000
0A8H	IE0000 0000	SADDR0000 0000						AREF0000 0000
0A0H P21111 1111			DPCF0000 00x0				WDTRST(write-only)	WDTCON0000 x000
98H	SCON0000 0000	SBUFxxxx xxxx	GPMOD0000 0000	GPLS0000 0000	GPIEN0000 0000	GPIF0000 0000		ACSRB1100 0000
90H	P11111 1111	TCONB0010 0100	RL00000 0000	RL10000 0000	RH00000 0000	RH10000 0000	MEMCON0000 00xx	ACSRA0000 0000
88H	TCON0000 0000	TMOD0000 0000	TL00000 0000	TL10000 0000	TH00000 0000	TH10000 0000		CLKREG0000 x000
80H		SP0000 0111	DPOL0000 0000	DPOH0000 0000	DP1L0000 0000	DP1H0000 0000	PAGExxxx xxx0	PCON0000 0000
	0	1	2	3	4	5	6	7

Notes: 1. All SFRs in the left-most column are bit-addressable.
2. Reset value is 1111 1111B when Tristate-port Fuse is enabled and 0000 0000B when disabled.

5. Enhanced CPU

The AT89LP428/828 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed of standard 8051 devices (or 3 to 6 times the speed of X2 8051 devices). The increase in performance is due to two factors. First, the CPU fetches one instruction byte from the code memory every clock cycle. Second, the CPU uses a simple two-stage pipeline to fetch and execute instructions in parallel. This basic pipelining concept allows the CPU to obtain up to 1 MIPS per MHz. A simple example is shown in Figure 5-1.

Figure 5-1. Parallel Instruction Fetches and Executions

System Clock Tn Tn+1 Tn+2 nth Instruction Fetch Execute (n+1)th Instruction Fetch Execute (n+2)th Instruction Fetch

The MCS-51 instruction set allows for instructions of variable length from 1 to 3 bytes. In a single-clock-per-byte-fetch system this means each instruction takes at least as many clocks as it has bytes to execute. The majority of instructions in the AT89LP428/828 follow this rule: the instruction execution time in clock cycles equals the number of bytes per instruction with a few exceptions. Branches and Calls require an additional cycle to compute the target address and some other complex instructions require multiple cycles. See "Instruction Set Summary" on page 107 for more detailed information on individual instructions. Figures 5-2 and 5-3 show examples of 1- and 2-byte instructions.

Figure 5-2. Single-cycle ALU Operation (Example: INC R0)

graph TD
    A["System Clock"] --> B["Total Execution Time"]
    B --> C["Register Operand Fetch"]
    C --> D["ALU Operation Execute"]
    D --> E["Result Write Back"]
    E --> F["Fetch Next Instruction"]
    style A fill:#f9f,stroke:#333
    style B fill:#ccf,stroke:#333
    style C fill:#cfc,stroke:#333
    style D fill:#fcc,stroke:#333
    style E fill:#cff,stroke:#333
    style F fill:#ffc,stroke:#333

Figure 5-3. Two-cycle ALU Operation (Example: ADD A, #data)

graph TD
    A["System Clock"] --> B["Total Execution Time"]
    B --> C["Fetch Immediate Operand"]
    C --> D["ALU Operation Execute"]
    D --> E["Result Write Back"]
    E --> F["Fetch Next Instruction"]
    style A fill:#f9f,stroke:#333
    style B fill:#ccf,stroke:#333
    style C fill:#cfc,stroke:#333
    style D fill:#fcc,stroke:#333
    style E fill:#cff,stroke:#333
    style F fill:#ffc,stroke:#333

5.1 Enhanced Dual Data Pointers

The AT89LP428/828 provides two 16-bit data pointers: DPTR0 formed by the register pair DPOL and DPOH (82H an 83H), and DPTR1 formed by the register pair DP1L and DP1H (84H and 85H). The data pointers are used by several instructions to access the program or data memories. The Data Pointer Configuration Register (DPCF) controls operation of the dual data pointers (Table 5-4). The DPS bit in DPCF selects which data pointer is currently referenced by instructions including the DPTR operand. Each data pointer may be accessed at its respective SFR addresses regardless of the DPS value. The AT89LP428/828 provides two methods for fast context switching of the data pointers:

- Bit 2 of DPCF is hard-wired as a logic 0. The DPS bit may be toggled (to switch data pointers) simply by incrementing the DPCF register, without altering other bits in the register unintentionally. This is the preferred method when only a single data pointer will be used at one time.

EX: INC DPCF ; Toggle DPS 

- In some cases, both data pointers must be used simultaneously. To prevent frequent toggling of DPS, the AT89LP428/828 supports a prefix notation for selecting the opposite data pointer per instruction. All DPTR instructions, with the exception of JMP @A+DPTR, when prefixed with an 0A5H opcode will use the inverse value of DPS (DPS) to select the data pointer. Some assemblers may support this operation by using the /DPTR operand. For example, the following code performs a block copy within EDATA:

MOV DPCF, #00H ; DPS = 0
MOV DPTR, #SRC ; load source address to dptr0
MOV /DPTR, #DST ; load destination address to dptr1
MOV R7, #BLKSIZE ; number of bytes to copy
COPY: MOVX A, @DPTR ; read source (dptr0)
INC DPTR ; next src (dptr0+1)
MOVX @/DPTR, A ; write destination (dptr1)
INC /DPTR ; next dst (dptr1+1)
DJNZ R7, COPY 

For assemblers that do not support this notation, the 0A5H prefix must be declared in-line:

EX: DB 0A5H

INC DPTR ; equivalent to INC /DPTR

A summary of data pointer instructions with fast context switching is listed in Table 5-1.

Table 5-1. Data Pointer Instructions

Instruction	Operation
	DPS = 0 DPS = 1
JMP @A+DPTR JMP @A+DPTR0	JMP @A+DPTR1
MOV DPTR, #data16	MOV DPTR0, #data16	MOV DPTR1, #data16
MOV/DPTR, #data16	MOV DPTR1, #data16	MOV DPTR0, #data16
INC DPTR INC DPTR0	INC DPTR1
INC/DPTR INC DPTR1	INC DPTR0
MOVC A,@A+DPTR	MOVC A,@A+DPTR0	MOVC A,@A+DPTR1
MOVC A,@A+/DPTR	MOVC A,@A+DPTR1	MOVC A,@A+DPTR0
MOVX A,@DPTR	MOVX A,@DPTR0	MOVX A,@DPTR1
MOVX A,@/DPTR	MOVX A,@DPTR1	MOVX A,@DPTR0
MOVX @DPTR, A	MOVX @DPTR0, A	MOVX @DPTR1, A
MOVX @/DPTR, A	MOVX @DPTR1, A	MOVX @DPTR0, A

5.1.1 Data Pointer Update

The Dual Data Pointers on the AT89LP428/828 include two additional features that control how the data pointers are updated. The data pointer decrement bits, DPD1 and DPD0 in DPCF, configure the INC DPTR instruction to act as DEC DPTR. The resulting operation will depend on DPS as shown in Table 5-2.

Table 5-2. INC DPTR Behavior

DPD1	DPD0	Operation
		DPS = 0		DPS = 1
		INC DPTR	INC /DPTR	INC DPTR	INC /DPTR
0	0	INC DPTR0	INC DPTR1	INC DPTR1	INC DPTR0
0	1	DEC DPTR0	INC DPTR1	INC DPTR1	DEC DPTR0
1	0	INC DPTR0	DEC DPTR1	DEC DPTR1	INC DPTR0
1	1	DEC DPTR0	DEC DPTR1	DEC DPTR1	DEC DPTR0

The data pointer update bits, DPU1 and DPU0, allow MOVX @DPTR and MOVC @DPTR instructions to update the selected data pointer automatically in a post-increment or post-decrement fashion. The direction of update depends on the DPD1 and DPD0 bits as shown in Table 5-3.

Table 5-3. DPTR Auto-update

DPD1 DPD0	Operation for MOVX and MOVC (DPU1 = 1 & DPU0 = 1)
	DPS = 0 DPS = 1
	DPTR /DPTR	DPTR /DPTR
0 0 DPTR0++ DPTR1++ DPTR1++ DPTR0++
0 1 DPTR0-- DPTR1++ DPTR1++ DPTR0--
1 0 DPTR0++ DPTR1-- DPTR1-- DPTR0++
1 1 DPTR0-- DPTR1-- DPTR1-- DPTR0--

Table 5-4. DPCF – Data Pointer Configuration Register

DPCF = A2H Reset Value = 0000 00X0BNot Bit Addressable
	DPU1	DPU0	DPD1	DPD0	SIGEN	0	-	DPS
Bit	7	6	5	4	3	2	1	0

Symbol	Function
DPU1	Data Pointer 1 Update. When set, MOVX @DPTR and MOVC @DPTR instructions that use DPTR1 will also update DPTR1 based on DPD1. If DPD1 = 0, the operation is post-increment and if DPD1 = 1 the operation is post-decrement. When DPU1 = 0, DPTR1 is not updated.
DPU0	Data Pointer 0 Update. When set, MOVX @DPTR and MOVC @DPTR instructions that use DPTR0 will also update DPTR0 based on DPD0. If DPD0 = 0, the operation is post-increment and if DPD0 = 1, the operation is post-decrement. When DPU0 = 0, DPTR0 is not updated.
DPD1	Data Pointer 1 Decrement. When set, INC DPTR instructions targeted to DPTR1 will decrement DPTR1. When cleared, INC DPTR instructions will increment DPTR1.
DPD0	Data Pointer 0 Decrement. When set, INC DPTR instructions targeted to DPTR0 will decrement DPTR0. When cleared, INC DPTR instructions will increment DPTR0.
SIGEN	Signature Enable. When SIGEN = 1, all MOVC @DPTR instructions and all IAP accesses will target the signature array memory. When SIGEN = 0, all MOVC and IAP accesses target CODE memory.
DPS	Data Pointer Select. DPS selects the active data pointer for instructions that reference DPTR. When DPS = 0, DPTR will target DPTR0 and /DPTR will target DPTR1. When DPS = 1, DPTR will target DPTR1 and /DPTR will target DPTR0.

5.2 Restrictions on Certain Instructions

The AT89LP428/828 is an economical and cost-effective member of Atmel's growing family of microcontrollers. It contains 4K/8K bytes of Flash program memory. It is fully compatible with the MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device. All the instructions related to jumping or branching should be restricted such that the destination address falls within the physical program memory space of the device, which is 0000H–0FFFH for the AT89LP428 and 0000H–1FFFH for the AT89LP828. This should be the responsibility of the software programmer. For example, LJMP 07E0H would be a valid instruction, whereas LJMP 9000H would not. A typical 8051 assembler will still assemble instructions, even if they are written in violation of the restrictions mentioned above. It is the responsibility of the user to know the physical features and limitations of the device being used and to adjust the instructions used accordingly.

5.2.1 Branching Instructions

The LCALL, LJMP, ACALL, AJMP, SJMP, and JMP @A+DPTR unconditional branching instructions will execute correctly as long as the programmer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size. Violating the physical space limits may cause unknown program behavior. With the CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, and JNZ conditional branching instructions, the same previous rule applies. Again, violating the memory boundaries may cause erratic execution.

5.2.2 MOVX-related Instructions

The AT89LP428/828 contains 512 bytes of internal Extra RAM and 512/1024 bytes of Flash data memory mapped into the XRAM address space. MOVX accesses to addresses above 03FFH/05FFH will return invalid data.

6. System Clock

The system clock is generated directly from one of three selectable clock sources. The three sources are the on-chip crystal oscillator, external clock source, and internal RC oscillator. The on-chip crystal oscillator may also be configured for low and high speed operation. The clock source is selected by the Clock Source User Fuses as shown in Table 6-1. See "User Configuration Fuses" on page 121. By default, no internal clock division is used to generate the CPU clock from the system clock. However, the system clock divider may be used to prescale the system clock. The choice of clock source also affects the start-up time after a POR, BOD or Power-down event (see "Reset" on page 23 or "Power-down Mode" on page 27).

Table 6-1. Clock Source Settings

Clock Source Fuse 1	Clock Source Fuse 0 Selected	Clock Source
0	0	High Speed Crystal Oscillator (f > 500 kHz)
0	1	Low Speed Crystal Oscillator (f ≤100 kHz)
1	0	External Clock on XTAL1
1	1	Internal 8 MHz RC Oscillator

6.1 Crystal Oscillator

When enabled, the internal inverting oscillator amplifier is connected between XTAL1 and XTAL2 for connection to an external quartz crystal or ceramic resonator. The oscillator may operate in either high-speed or low-speed mode. Low-speed mode is intended for 32.768 kHz watch crystals and consumes less power than high-speed mode. The configuration as shown in Figure 6-1 applies for both high and low speed oscillators. Note that the internal structure of the device adds about 10 pF of capacitance to both XTAL1 and XTAL2, so that in some cases an external capacitor may NOT be required. It is recommended that a resistor R1 be connected to XTAL1, instead of load capacitor C1, for improved startup performance. The total capacitance on XTAL1 or XTAL2, including the external load capacitor plus internal device load, board trace and crystal loadings, should not exceed 20 pF. When using the crystal oscillator, P4.0 and P4.1 will have their inputs and outputs disabled. Also, XTAL2 in crystal oscillator mode should not be used to directly drive a board-level clock without a buffer.

Figure 6-1. Crystal Oscillator Connections

C2 R1 XTAL2 ~10 pF XTAL1 ~10 pF GND

Note: 1. C2 = 0–10 pF for Crystals = 0–10 pF for Ceramic Resonators R1 = 4–5 MΩ

6.2 External Clock Source

The external clock option disables the oscillator amplifier and allows XTAL1 to be driven directly by an external clock source as shown in Figure 6-2. XTAL2 may be left unconnected, used as general-purpose I/O P4.1, or configured to output a divided version of the system clock.

Figure 6-2. External Clock Drive Configuration

NC, GPIO, or CLKOUT External Oscillator Signal XTAL2 (P4.1) XTAL1 (P4.0) GND

6.3 Internal RC Oscillator

The AT89LP428/828 has an Internal RC oscillator (IRC) tuned to 8.0 MHz ±1.0% at 5.0V and 25°C. When enabled as the clock source, XTAL1 and XTAL2 may be used as P4.0 and P4.1, respectively. XTAL2 may also be configured to output a divided version of the system clock. The frequency of the oscillator may be adjusted within limits by changing the RC Calibration Byte stored at byte 64 of the User Signature Array. This location may be updated using the IAP interface (location 00C0H in SIG space) or by an external device programmer (UROW location 0040H). See “User Signature and Analog Configuration” on page 122.

6.4 System Clock Out

When the AT89LP428/828 is configured to use either an external clock or the internal RC oscillator, the system clock divided by 2 may be output on XTAL2 (P4.1). The clock out feature is enabled by setting the COE bit in CLKREG. For example, setting COE = "1" when using the internal oscillator will result in a 4.0 MHz clock output on P4.1. P4.1 must be configured as an output in order to use the clock out feature.

6.5 System Clock Divider

The CDV_2-0 bits in CLKREG allow the system clock to be divided down from the selected clock source by powers of 2. The clock divider provides users with a greater frequency range when using the Internal RC Oscillator. For example, to achieve a 1 MHz system frequency when using the IRC, CDV_2-0 should be set to 011B for divide-by-8 operation. The divider can also be used to reduce power consumption by decreasing the operational frequency during non-critical periods. The resulting system frequency is given by the following equation:

$$ f _ {\mathrm{SYS}} \frac {f _ {\mathrm{OSC}}}{2 ^ {\mathrm{CDV}}} = $$

where f_OSC is the frequency of the selected clock source. The clock divider will prescale the clock for the CPU and all peripherals. The value of CDV may be changed at any time without interrupting normal execution. Changes to CDV are synchronized such that the system clock will not pass through intermediate frequencies. When CDV is updated, the new frequency will take affect within a maximum period of 32 × t_OSC .

Table 6-2. CLKREG – Clock Control Register

CLKREG = 8FH Reset Value = 0000 0000BNot Bit Addressable
	TPS3	TPS2	TPS1	TPS0	CDV2	CDV1	CDV0	COE
B	i	t	7	6	5	4	3	2

Symbol Function
TPS [3 - 0]	Timer Prescaler. The Timer Prescaler selects the time base for Timer 0, Timer 1, Timer 2 and the Watchdog Timer. The prescaler is implemented as a 4-bit binary down counter. When the counter reaches zero it is reloaded with the value stored in the TPS bits to give a division ratio between 1 and 16. By default the timers will count every clock cycle (TPS = 0000B). To configure the timers to count at a standard 8051 rate of once every 12 clock cycles, TPS should be set to 1011B.
CDV [2 - 0]	System Clock Division. Determines the frequency of the system clock relative to the oscillator clock source.CDIV2 CDIV1 CDIV0 System Clock Frequency0 0 0 f_osc/1 0 0 1 f_osc/2 0 1 0 f_osc/4 0 1 1 f_osc/8 1 0 0 f_osc/16 1 0 1 f_osc/32 1 1 0 reserved1 1 1 reserved
COE	Clock Out Enable. Set COE to output the system clock divided by 2 on XTAL2 (P4.1). The internal RC oscillator or external clock source must be selected in order to use this feature and P4.1 must be configured as an output.

7. Reset

During reset, all I/O Registers are set to their initial values, the port pins are tristated, and the program starts execution from the Reset Vector, 0000H. The AT89LP428/828 has five sources of reset: power-on reset, brown-out reset, external reset, watchdog reset, and software reset.

7.1 Power-on Reset

A Power-on Reset (POR) is generated by an on-chip detection circuit. The detection level V_POR is nominally 1.4V. The POR is activated whenever V_CC is below the detection level. The POR circuit can be used to trigger the start-up reset or to detect a supply voltage failure in devices without a brown-out detector. The POR circuit ensures that the device is reset from power-on. A power-on sequence is shown in Figure 7-1 on page 24. When V_CC reaches the Power-on Reset threshold voltage V_POR , an initialization sequence lasting t_POR is started. When the initialization sequence completes, the start-up timer determines how long the device is kept in POR after V_CC rise. The POR signal is activated again, without any delay, when V_CC falls below the POR threshold level. A Power-on Reset (i.e. a cold reset) will set the POF flag in PCON. The internally generated reset can be extended beyond the power-on period by holding the RST pin low longer than the time-out.

Figure 7-1. Power-on Reset Sequence (BOD Disabled)

VCC Time-out VPOR tPOR + tSUT VPOR RST Internal Reset (RST Tied to VCC) Internal Reset (RST Controlled Externally) tRHD VIH

Note: t POR is approximately 92 μs ± 5%.

If the Brown-out Detector (BOD) is also enabled, the start-up timer does not begin counting until after V_CC reaches the BOD threshold voltage V_BOD as shown in Figure 7-2. However, if this event occurs prior to the end of the initialization sequence, the timer must first wait for that sequence to complete before counting.

The start-up timer delay is user-configurable with the Start-up Time User Fuses and depends on the clock source (Table 7-1). The Start-up Time fuses also control the length of the start-up time after a Brown-out Reset or when waking up from Power-down during internally timed mode. The start-up delay should be selected to provide enough settling time for V_CC and the selected clock source. The device operating environment (supply voltage, frequency, temperature, etc.) must meet the minimum system requirements before the device exits reset and starts normal operation. The RST pin may be held low externally until these conditions are met.

Figure 7-2. Power-on Reset Sequence (BOD Enabled)

VCC VPOR VBOD Time-out tPOR tSUT RST (RST Tied to VCC) Internal Reset RST (RST Controlled Externally) VIH Internal Reset tRHD

Table 7-1. Start-up Timer Settings

SUT Fuse 1 SUT Fuse 0 Clock Source t			_SUT(± 5%) μs
0	0	Internal RC/External Clock	16
		Crystal Oscillator	1024
0	1	Internal RC/External Clock	N/A
		Crystal Oscillator	2048
1	0	Internal RC/External Clock	1024
		Crystal Oscillator	4096
1	1	Internal RC/External Clock	N/A
		Crystal Oscillator	16384

7.2 Brown-out Reset

The AT89LP428/828 has an on-chip Brown-out Detector (BOD) circuit for monitoring the V_CC level during operation by comparing it to a fixed trigger level. The trigger level V_BOD for the BOD is nominally 2.2V. The purpose of the BOD is to ensure that if V_CC fails or dips while executing at speed, the system will gracefully enter reset without the possibility of errors induced by incorrect execution. A BOD sequence is shown in Figure 7-3. When V_CC decreases to a value below the trigger level V_BOD , the internal reset is immediately activated. When V_CC increases above the trigger level, the start-up timer releases the internal reset after the specified time-out period has expired (Table 7-1). Note that there is approximately 200 mV of hysteresis between the rising and falling V_BOD thresholds. The Brown-out Detector must be enabled by setting the BOD Enable Fuse. (See “User Configuration Fuses” on page 121.)

The AT89LP428/828 allows for a wide V_CC operating range. The on-chip BOD may not be sufficient to prevent incorrect execution if V_BOD is lower than the minimum required V_CC range, such as when a 5V supply is coupled with high frequency operation. In such cases an external Brownout Reset circuit connected to the RST pin may be required.

Figure 7-3. Brown-out Detector Reset

VCC VPOR VBOD Time-out tSUT Internal Reset

7.3 External Reset

The P3.6/RST pin can function as either an active-low reset input or as a digital general-purpose I/O, P3.6. The Reset Pin Enable Fuse, when set to "1", enables the external reset input function on P3.6. (see "User Configuration Fuses" on page 121). When cleared, P3.6 may be used as an input or output pin. When configured as a reset input, the pin must be held low for at least two clock cycles to trigger the internal reset. The RST pin includes an on-chip pull-up resistor tied to V_CC . The pull-up is disabled when the pin is configured as P3.6.

Note: During a power-up sequence, the fuse selection is always overridden and therefore the pin will always function as a reset input. An external circuit connected to this pin should not hold this pin LOW during a power-on sequence if the pin is configured as a general I/O, as this will keep the device in reset until the pin transitions high. After the power-up delay, this input will function either as an external reset input or as a digital input as defined by the fuse bit. Only a power-up reset will temporarily override the selection defined by the reset fuse bit. Other sources of reset will not override the reset fuse bit. P3.6/RST also serves as the In-System Programming (ISP) enable. ISP is enabled when the external reset pin is held low. When the reset pin is disabled by the fuse, ISP may only be entered by pulling P3.6 low during power-up.

7.4 Watchdog Reset

When the Watchdog times out, it will generate an internal reset pulse lasting 16 clock cycles. Watchdog reset will also set the WDTOVF flag in WDTCON. To prevent a Watchdog reset, the watchdog reset sequence 1EH/E1H must be written to WDTRST before the Watchdog times out. See “Programmable Watchdog Timer” on page 105 for details on the operation of the Watchdog.

7.5 Software Reset

The CPU may generate an internal 16-clock cycle reset pulse by writing the software reset sequence 5AH/A5H to the WDRST register. A software reset will set the SWRST bit in WDT-CON. See "Software Reset" on page 106 for more information on software reset. Writing any sequences other than 5AH/A5H or 1EH/E1H to WDTRST will generate an immediate reset and set both WDTOVF and SWRST to flag an error.

8. Power Saving Modes

The AT89LP428/828 supports two different power-reducing modes: Idle and Power-down. These modes are accessed through the PCON register.

8.1 Idle Mode

Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU state is preserved in its entirety, including the RAM, stack pointer, program counter, program status word, and accumulator. The Port pins hold the logic states they had at the time that Idle was activated. Idle mode leaves the peripherals running in order to allow them to wake up the CPU when an interrupt is generated. The timers, UART, SPI, comparators, GPI and CCA peripherals continue to function during Idle. If these functions are not needed during idle, they should be explicitly disabled by clearing the appropriate bits in their respective SFRs. The watchdog may be selectively enabled or disabled during Idle by setting/clearing the WDIDLE bit. Any enabled interrupt source or reset may terminate Idle mode. When exiting Idle mode with an interrupt, the interrupt will immediately be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into Idle.

8.2 Power-down Mode

Setting the Power-down (PD) bit in PCON enters Power-down mode. Power-down mode stops the oscillator, disables the BOD and powers down the Flash memory in order to minimize power consumption. Only the power-on circuitry will continue to draw power during Power-down. During Power-down, the power supply voltage may be reduced to the RAM keep-alive voltage. The RAM contents will be retained, but the SFR contents are not guaranteed once V_CC has been reduced. Power-down may be exited by external reset, power-on reset, or certain enabled interrupts.

8.2.1 Interrupt Recovery from Power-down

Three external interrupt sources may be configured to terminate Power-down mode: external interrupts INT0 (P3.2) and INT1 (P3.3); and the GPI. To wake up by external interrupt INT0 or INT1, that interrupt must be enabled by setting EX0 or EX1 in IE and must be configured for level-sensitive operation by clearing IT0 or IT1. Any GPI on Port 1 (GPI _7-0 ) can also wake up the device. The GPI pin must be enabled in GPIEN and configured for level-sensitive detection, and EGP in IE2 must be set in order to terminate Power-down.

When terminating Power-down by an interrupt, two different wake-up modes are available. When PWDEX in PCON is zero, the wake-up period is internally timed as shown in Figure 8-1. At the falling edge on the interrupt pin, Power-down is exited, the oscillator is restarted, and an internal timer begins counting. The internal clock will not be allowed to propagate to the CPU until after the timer has timed out. After the time-out period, the interrupt service routine will begin. The time-out period is controlled by the Start-up Timer Fuses (see Table 7-1 on page 25). The interrupt pin need not remain low for the entire time-out period.

Figure 8-1. Interrupt Recovery from Power-down (PWDEX = 0)

PWD XTAL1 INT1 Internal Clock tSUT

When PWDEX = "1", the wake-up period is controlled externally by the interrupt. Again, at the falling edge on the interrupt pin, power-down is exited and the oscillator is restarted. However, the internal clock will not propagate until the rising edge of the interrupt pin as shown in Figure 8-2. The interrupt pin should be held low long enough for the selected clock source to stabilize. After the rising edge on the pin the interrupt service routine will be executed.

Figure 8-2. Interrupt Recovery from Power-down (PWDEX = 1)

PWD XTAL1 INT1 Internal Clock

8.2.2 Reset Recovery from Power-down

The wake-up from Power-down through an external reset is similar to the interrupt with PWDEX = "0". At the falling edge of , Power-down is exited, the oscillator is restarted, and an internal timer begins counting as shown in Figure 8-3. The internal clock will not be allowed to propagate to the CPU until after the timer has timed out. The time-out period is controlled by the Start-up Timer Fuses. (See Table 7-1 on page 25). If returns high before the time-out, a two clock cycle internal reset is generated when the internal clock restarts. Otherwise, the device will remain in reset until is brought high.

Figure 8-3. Reset Recovery from Power-down

PWD XTAL1 RST Internal Clock Internal Reset tSUT

Table 8-1. PCON – Power Control Register

PCON = 87H Reset Value = 000X 0000BNot Bit Addressable
	SMOD1 SMOD0 PWDEX		POF GF1 GF0 PD IDL
B	i	t	7	6	5	4	3	2

Symbol Function
SMOD1	Double Baud Rate Bit. Doubles the baud rate of the UART in Modes 1, 2, or 3.
SMOD0	Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after a frame error regardless of the state of SMOD0.
PWDEX	Power-down Exit Mode. When PWDEX = 1, wake up from Power-down is externally controlled. When PWDEX = 1, wake up from Power-down is internally timed.
POF	Power Off Flag. POF is set to “1” during power up (i.e. cold reset). It can be set or reset under software control and is not affected by RST or BOD (i.e. warm resets).
GF1, GF0	General-purpose Flags.
PD	Power-down Bit. Setting this bit activates power-down operation.
IDL	Idle Mode Bit. Setting this bit activates Idle mode operation

9. Interrupts

The AT89LP428/828 provides 10 interrupt sources: two external interrupts, three timer interrupts, a serial port interrupt, an analog comparator interrupt, a GPI, a compare/capture interrupt and an SPI interrupt. These interrupts and the system reset each have a separate program vector at the start of the program memory space. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IE and IE2. The IE register also contains a global disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP, IPH, IP2 and IP2H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the end of an instruction, the request of higher priority level is serviced. If requests of the same priority level are pending at the end of an instruction, an internal polling sequence determines which request is serviced. The polling sequence is based on the vector address; an interrupt with a lower vector address has higher priority than an interrupt with a higher vector address. Note that the polling sequence is only used to resolve pending requests of the same priority level.

The IPxD bits located at the seventh bit of IP, IPH, IP2 and IP2H can be used to disable all interrupts of a given priority level, allowing software implementations of more complex interrupt priority handling schemes.

The External Interrupts INT0 and INT1 can each be either level-activated or edge-activated, depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these interrupts are the IE0 and IE1 bits in TCON. When the service routine is vectored to, hardware clears the flag that generated an external interrupt only if the interrupt was edge-activated. If the interrupt was level activated, then the external requesting source (rather than the on-chip hardware) controls the request flag.

The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective Timer/Counter registers (except for Timer 0 in Mode 3). When a timer interrupt is generated, the on-chip hardware clears the flag that generated it when the service routine is vectored to. The Timer 2 Interrupt is generated by a logic OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the CPU vectors to the service routine. The service routine normally must determine whether TF2 or EXF2 generated the interrupt and that bit must be cleared by software.

The Serial Port Interrupt is generated by the logic OR of RI and TI in SCON. Neither of these flags is cleared by hardware when the CPU vectors to the service routine. The service routine normally must determine whether RI or TI generated the interrupt and that bit must be cleared by software. The Serial Peripheral Interface Interrupt is generated by the logic OR of SPIF, MODF and TXE in SPSR. None of these flags is cleared by hardware when the CPU vectors to the service routine. The service routine normally must determine which bit generated the interrupt and that bit must be cleared by software.

A logic OR of all eight flags in the GPIF register causes the GPI. None of these flags is cleared by hardware when the service routine is vectored to. The service routine must determine which bit generated the interrupt and that bit must be cleared in software. If the interrupt was level activated, then the external requesting source must de-assert the interrupt before the flag may be cleared by software.

The CFA and CFB bits in ACSRA and ACSRB respectively generate the Comparator Interrupt. The service routine must normally determine whether CFA or CFB generated the interrupt, and the bit must be cleared by software.

A logic OR of the four least significant bits in the T2CCF register causes the Compare/Capture Array Interrupt. None of these flags is cleared by hardware when the service routine is vectored to. The service routine must determine which bit generated the interrupt and that bit must be cleared in software.

All of the bits that generate interrupts can be set or cleared by software, with the same result as though they had been set or cleared by hardware. That is, interrupts can be generated and pending interrupts can be canceled in software.

Table 9-1. Interru pt Vector Addresses

Interrupt Source Vector Address
System Reset	RST or POR or BOD	0000H
External Interrupt 0	IE0	0003H
Timer 0 Overflow TF0 000BH
External Interrupt 1	IE1	0013H
Timer 1 Overflow TF1 001BH
Serial Port Interrupt	RI or TI	0023H
Timer 2 Interrupt TF2 or EXF2 002BH
Analog Comparator Interrupt	CFA or CFB	0033H
General-purpose Interrupt	GPIF_7-0	003BH
Compare/Capture Array Interrupt	T2CCF_3-0	0043H
Serial Peripheral Interface Interrupt	SPIF or MODF or TXE	004BH

9.1 Interrupt Response Time

The interrupt flags may be set by their hardware in any clock cycle. The interrupt controller polls the flags in the last clock cycle of the instruction in progress. If one of the flags was set in the preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine as the next instruction, provided that the interrupt is not blocked by any of the following conditions: an interrupt of equal or higher priority level is already in progress; the instruction in progress is RETI or any write to the IE, IP, IPH, IE2, IP2 or IP2H registers; the CPU is currently forced into idle by an IAP or FDATA write. Each of these conditions will block the generation of the LCALL to the interrupt service routine. The second condition ensures that if the instruction in progress is RETI or any access to IE, IP, IPH, IE2, IP2 or IP2H, then at least one more instruction will be executed before any interrupt is vectored to. The polling cycle is repeated at the last cycle of each instruction, and the values polled are the values that were present at the previous clock cycle. If an active interrupt flag is not being serviced because of one of the above conditions and is no longer active when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle is new.

If a request is active and conditions are met for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction executed. The call itself takes four cycles. Thus, a minimum of five complete clock cycles elapsed between activation of an interrupt request and the beginning of execution of the first instruction of the service routine. A longer response time results if the request is blocked by one of the previously listed conditions. If an interrupt of equal or higher priority level is already in progress, the additional wait time depends on the nature of the other interrupt's service routine. If the instruction in progress is not in its final clock cycle, the additional wait time cannot be more than 4 cycles, since the longest are only 5 cycles long. If the instruction in progress is RETI or an access to IE or IP, the additional wait time cannot be more than 9 cycles (a maximum of four more cycles to complete the instruction in progress, plus a maximum of 5 cycles to complete the next instruction). Thus, in a single-interrupt system, the response time is always more than 5 clock cycles and less than 14 clock cycles. See Figure 9-1 and Figure 9-2.

Figure 9-1. Minimum Interrupt Response Time

Clock Cycles INT0 IE0 Acknowledgment Instruction Cur. Instr. LCALL 1st ISR Instr. 1↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↓ Ack.

Figure 9-2. Maximum Interrupt Response Time

Clock Cycles INT0 IE0 Instruction 1 14 5 Cyc. Instr. L CALL 1st ISR Instr. Ack.

9.2 Interrupt Registers

Table 9-2. IE – Interrupt Enable Register

IE = A8H Reset Value = 0000 0000B Bit Addressable
	EA EC	ET2 ESET1 EX1	ET0 EX0
B	i	t	7	6	5	4	3	2
Symbol Function
EA	Global enable/disable. All interrupts are disabled when EA = 0. When EA = 1, each interrupt source is enabled/disabled by setting/clearing its own enable bit.
EC	Comparator Interrupt Enable
ET2	Timer 2 Interrupt Enable
ES	Serial Port Interrupt Enable
ET1	Timer 1 Interrupt Enable
EX1	External Interrupt 1 Enable
ET0	Timer 0 Interrupt Enable
EX0 Externa	I Interrupt 0 Enable

Table 9-3. IP – Interrupt Priority Register

IP = B8H Reset Value = 0000 0000B Bit Addressable
	IP0D	PC	PT2 PSPT1 PX1 PT0 PX0
B	i	t	7	6	5	4	3	2
Symbol Function
IP0D	Interrupt Priority 0 Disable. Set IP0D to 1 to disable all interrupts with priority level zero. Clear to 0 to enable all interrupts with priority level zero when EA = 1.
PC	Comparator Interrupt Priority Low
PT2 Timer 2	Interrupt Priority Low
PS	Serial Port Interrupt Priority Low
PT1 Timer 1	Interrupt Priority Low
PX1	External Interrupt 1 Priority Low
PT0 Timer 0	Interrupt Priority Low
PX0	External Interrupt 0 Priority Low

Table 9-4. IPH – Interrupt Priority High Register

IPH = B7H Reset Value = 0000 0000BNot Bit Addressable
	IP1D PCH		PT2H PSH	PT1H PX1H	PT0H PX0H
B	i	t	7	6	5	4	3	2

Symbol Function
IP1D	Interrupt Priority 1 Disable. Set IP1D to 1 to disable all interrupts with priority level one. Clear to 0 to enable all interrupts with priority level one when EA = 1.
PCH	Comparator Interrupt Priority High
PT2H Timer	2 Interrupt Priority High
PSH	Serial Port Interrupt Priority High
PT1H Timer	1 Interrupt Priority High
PX1H	External Interrupt 1 Priority High
PT0H Timer	0 Interrupt Priority High
PX0H	External Interrupt 0 Priority High

Table 9-5. IE2 – Interrupt Enable 2 Register

IE = B4H Reset Value = xxxx x000BNot Bit Addressable
	-	-	-	-	-	ESP	ECC	EGP
B	i	t	7	6	5	4	3	2

Symbol Function
ESP	Serial Peripheral Interface Interrupt Enable
ECC	Compare/Capture Array Interrupt Enable
EGP	General-purpose Interrupt Enable

Table 9-6. IP2 – Interrupt Priority 2 Register

IP = B5H Reset Value = 0xxx x000BNo Bit Addressable
	I	P	2	D	-	-PSPPCCPGP-		-
B	i	t	7	6	5	4	3	2

Symbol Function
IP2D	Interrupt Priority 2 Disable. Set IP2D to 1 to disable all interrupts with priority level two. Clear to 0 to enable all interrupts with priority level two when EA = 1.
PSP	Serial Peripheral Interface Interrupt Priority Low
PCC	Compare/Capture Array Interrupt Priority Low
PGP	General-purpose Interrupt 0 Priority Low

Table 9-7. IP2H – Interrupt Priority 2 High Register

IP2H = B6H Reset Value = 0xxx x000BNot Bit Addressable
	I	P	3D	-	-	PSPH	PGCH	PGPH
B	i	t	7	6	5	4	3	2

Symbol Function
IP3D	Interrupt Priority 3 Disable. Set IP3D to 1 to disable all interrupts with priority level three. Clear to 0 to enable all interrupts with priority level three when EA = 1.
PSPH	Serial Peripheral Interface Interrupt Priority High
PCCH	Compare/Capture Array Interrupt Priority High
PGPH	General-purpose Interrupt 0 Priority High

10. I/O Ports

The AT89LP428/828 can be configured for between 23 and 30 I/O pins. The exact number of I/O pins available depends on the package type and the clock and reset options as shown in Table 10-1.

Table 10-1. I/O Pin Configurations

Clock Source Reset Option Package Number of I/O Pins
External Crystal or Resonator	External RST Pin	PDIP 23
		TQFP or PLCC 27
	No external reset	PDIP 24
		TQFP or PLCC 28
External Clock	External RST Pin	PDIP 24
		TQFP or PLCC 28
	No external reset	PDIP 25
		TQFP or PLCC 29
Internal RC Oscillator	External RST Pin	PDIP 25
		TQFP or PLCC 29
	No external reset	PDIP 26
		TQFP or PLCC 30

10.1 Port Configuration

All port pins on the AT89LP428/828 may be configured to one of four modes: quasi-bidirectional (standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port modes may be assigned in software on a pin-by-pin basis as shown in Table 10-2 using the registers listed in Table 10-3. The Tristate-Port User Fuse determines the default state of the port pins. When the fuse is enabled, all port pins default to input-only mode after reset. When the fuse is disabled, all port pins, with the exception of the analog inputs, P2.4, P2.5, P2.6 and P2.7, default to quasi-bidirectional mode after reset and are weakly pulled high. The analog input pins always reset to input-only (tristate) mode. Each port pin also has a Schmitt-triggered input for improved input noise rejection. During Power-down all the Schmitt-triggered inputs are disabled with the exception of P3.2 (INT0), P3.3 (INT1), P3.6 (RST), P4.0 (XTAL1) and P4.1 (XTAL2) which may be used to wake up the device. Therefore, P3.2, P3.3, P3.6, P4.0 and P4.1 should not be left floating during Power-down. In addition any pin of Port 1 configured as a GPI input will also remain active during Power-down to wake-up the device. These interrupt pins should either be disabled before entering Power-down or they should not be left floating.

Table 10-2. Configuration Modes for Port x, Bit y

PxM0.y PxM	1.y Port Mode
0	0	Quasi-bidirectional
0	1	Push-pull Output
1	0	Input Only (High Impedance)
1	1	Open-drain Output

Table 10-3. Port Configuration Registers

Port Port Data Port Configuration
1 P1 (90H)	P1M0 (C2H), P1M1 (C3H)
2 P2 (A0H)	P2M0 (C4H), P2M1 (C5H)
3 P3 (B0H)	P3M0 (C6H), P3M1 (C7H)
4 P4 (C0H)	P4M0 (BEH), P4M1 (BFH)

10.1.1 Quasi-bidirectional Output

Port pins in quasi-bidirectional output mode function similar to standard 8051 port pins. A Quasi-bidirectional port can be used both as an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin is driven low, it is driven strongly and able to sink a large current. There are three pull-up transistors in the quasi-bidirectional output that serve different purposes.

One of these pull-ups, called the “very weak” pull-up, is turned on whenever the port latch for the pin contains a logic “1”. This very weak pull-up sources a very small current that will pull the pin high if it is left floating.

A second pull-up, called the “weak” pull-up, is turned on when the port latch for the pin contains a logic “1” and the pin itself is also at a logic “1” level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a “1”. If this pin is pulled low by an external device, this weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and pull the port pin below its input threshold voltage.

The third pull-up is referred to as the “strong” pull-up. This pull-up is used to speed up low-to-high transitions on a quasi-bidirectional port pin when the port latch changes from a logic “0” to a logic “1”. When this occurs, the strong pull-up turns on for two CPU clocks quickly pulling the port pin high. The quasi-bidirectional port configuration is shown in Figure 10-1.

Figure 10-1. Quasi-bidirectional Output

graph TD
    A["From Port Register"] --> B["Q"]
    B --> C["NOT"]
    C --> D["1 Clock Delay (D Flip-Flop)"]
    D --> E["AND Gate"]
    E --> F["Strong Gate"]
    F --> G["Vcc"]
    F --> H["Vcc"]
    F --> I["Vcc"]
    F --> J["Very Weak"]
    F --> K["Weak"]
    J --> L["Port Pin"]
    K --> L
    L --> M["Input Data"]
    M --> N["PWD"]
    N --> O["AND Gate"]
    O --> P["NOT"]
    P --> Q["Port Pin"]

10.1.2 Input-only Mode

The input only port configuration is shown in Figure 10-2. The output drivers are tristated. The input includes a Schmitt-triggered input for improved input noise rejection. The input circuitry of P3.2, P3.3, P3.6, P4.0 and P4.1 is not disabled during Power-down (see Figure 10-3) and therefore these pins should not be left floating during Power-down when configured in this mode.

Figure 10-2. Input Only

graph LR
    A["Input Data"] --> B["NOT"]
    B --> C["AND Gate"]
    C --> D["AND Gate"]
    D --> E["Port Pin"]
    F["PWD"] --> G["Ground"]

Figure 10-3. Input Circuit for P3.2, P3.3 and P3.6

graph LR
    A["Input Data"] --> B["Inverter"]
    B --> C["Inverter"]
    C --> D["Port Pin"]

10.1.3 Open-drain Output

The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port latch contains a logic "0". To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to V_CC . The pull-down for this mode is the same as for the quasi-bidirectional mode. The open-drain port configuration is shown in Figure 10-4. The input circuitry of P3.2, P3.3 and P3.6 is not disabled during Power-down (see Figure 10-3) and therefore these pins should not be left floating during Power-down when configured in this mode.

Figure 10-4. Open-drain Output

graph TD
    A["From Port Register"] --> B["Transistor"]
    B --> C["AND Gate"]
    C --> D["Output to Port Pin"]
    D --> E["PWD"]
    F["Input Data"] --> G["NOT"]
    G --> H["AND Gate"]
    H --> I["Output to Port Pin"]

10.1.4 Push-pull Output

The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic "1". The push-pull mode may be used when more source current is needed from a port output. The push-pull port configuration is shown in Figure 10-5.

Figure 10-5. Push-pull Output

From Port Register Input Data PWD Vcc Port Pin

10.2 Port 2 Analog Functions

The AT89LP428/828 incorporates two analog comparators. In order to give the best analog performance and minimize power consumption, pins that are being used for analog functions must have both their digital outputs and inputs disabled. Digital outputs are disabled by putting the port pins into the input-only mode as described in "Port Configuration" on page 35. Digital inputs on P2.4, P2.5, P2.6 and P2.7 are disabled whenever an analog comparator is enabled by setting the CENA or CENB bits in ACSRA and ACSRB and that pin is configured for input-only mode. To use an analog input pin as a high-impedance digital input while a comparator is enabled, that pin should be configured in open-drain mode and the corresponding port register bit should be set to 1. The analog input pins will always default to input-only mode after reset regardless of the state of the Tristate-Port User Fuse.

If analog noise immunity is a concern, the P2.4–7 pins should not be used as high speed digital inputs or outputs while the comparators are enabled.

10.3 Port Read-Modify-Write

A read from a port will read either the state of the pins or the state of the port register depending on which instruction is used. Simple read instructions will always access the port pins directly. Read-modify-write instructions, which read a value, possibly modify it, and then write it back, will always access the port register. This includes bit write instructions such as CLR or SETB as they actually read the entire port, modify a single bit, then write the data back to the entire port. See Table 10-4 for a complete list of Read-modify-write instructions which may access the ports.

Table 10-4. Port Read-Modify-Write Instructions

Mnemonic Instruction	Example
ANL Logical AND ANL P1, A
ORL Logical OR ORL P1, A
XRL Logical EX-OR XRL P1, A
JBC	Jump if bit set and clear bit	JBC P3.0, LABEL
CPL Complement bit	CPL P3.1
INC	Increment	INC P1
DEC	Decrement	DEC P3
DJNZ	Decrement and jump if not zero	DJNZ P3, LABEL
MOV PX.Y, C	Move carry to bit Y of Port X	MOV P1.0, C
CLR PX.Y	Clear bit Y of Port X	CLR P1.1
SETB PX.Y	Set bit Y of Port X	SETB P3.2

10.4 Port Alternate Functions

Most general-purpose digital I/O pins of the AT89LP428/828 share functionality with the various I/Os needed for the peripheral units. Table 10-6 lists the alternate functions of the port pins. Alternate functions are connected to the pins in a logic AND fashion. In order to enable the alternate function on a port pin, that pin must have a "1" in its corresponding port register bit, otherwise the input/output will always be "0". However, alternate functions may be temporarily forced to "0" by clearing the associated port bit, provided that the pin is not in input-only mode. Furthermore, each pin must be configured for the correct input/output mode as required by its peripheral before it may be used as such. Table 10-5 shows how to configure a generic pin for use with an alternate function.

Table 10-5. Alternate Function Configurations for Pin y of Port x

PxM0.y	PxM1.y	Px.y	I/O Mode
0	0	1	Bidirectional (internal pull-up)
0	1	1	Output
1	0	X	Input
1	1	1	Bidirectional (external pull-up)

Table 10-6. Port Pin Alternate Functions

Port Pin	Configuration Bits		Alternate Function Notes	PxM0.y PxM1.y
P1.0 P1M0.0 P1M1.0			T2
			GPIO
P1.1 P1M0.1 P1M1.1			T2EX
			GPI1
P1.2 P1M0.2 P1M1.2 GPI2
P1.3 P1M0.3 P1M1.3 GPI3
P1.4 P1M0.4 P1M1.4			SS
			GPI4
P1.5 P1M0.5 P1M1.5			MOSI
			GPI5
P1.6 P1M0.6 P1M1.6			MISO
			GPI6
P1.7 P1M0.7 P1M1.7			SCK
			GPI7
P2.0 P2M0.0 P2M1.0 CCA
P2.1 P2M0.1 P2M1.1 CCB
P2.2 P2M0.2 P2M1.2 CCC
P2.3 P2M0.3 P2M1.3 CCD
P2.4 P2M0.4 P2M1.4 AIN0	Input-only
P2.5 P2M0.5 P2M1.5 AIN1	Input-only
P2.6 P2M0.6 P2M1.6 AIN2	Input-only
P2.7 P2M0.7 P2M1.7 AIN3	Input-only
P3.0 P3M0.0 P3M1.0 RXD
P3.1 P3M0.1 P3M1.1 TXD
P3.2 P3M0.2 P3M1.2 INT0
P3.3 P3M0.3 P3M1.3 INT1
P3.4 P3M0.4 P3M1.4 T0
P3.5 P3M0.5 P3M1.5 T1
P3.6	P3M0.5	P3M1.5	RST	RST must be disabled to use P3.6
P4.6	Not configurable		CMPA	Pin is tied to comparator output
P4.7	Not configurable		CMPB	Pin is tied to comparator output

11. Enhanced Timer 0 and Timer 1 with PWM

The AT89LP428/828 has two 16-bit Timer/Counters, Timer 0 and Timer 1, with the following features:

• Two 16-bit timer/counters with 16-bit reload registers
• Two independent 8-bit precision PWM outputs with 8-bit prescalers
• UART or SPI baud rate generation using Timer 1
• Output pin toggle on timer overflow
• Split timer mode allows for three separate timers (two 8-bit, one 16-bit)
• Gated modes allow timers to run/halt based on an external input

Timer 0 and Timer 1 have similar modes of operation. As timers, they increase every clock cycle by default. Thus, the registers count clock cycles. Since a clock cycle consists of one oscillator period, the count rate is equal to the oscillator frequency. The timer rate can be prescaled by a value between 1 and 16 using the Timer Prescaler (see Table 6-2 on page 23). Both Timers share the same prescaler.

As counters, the timer registers are incremented in response to a 1-to-0 transition at the corresponding input pins, T0 or T1. The external input is sampled every clock cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during the cycle following the one in which the transition was detected. Since 2 clock cycles are required to recognize a 1-to-0 transition, the maximum count rate is 1/2 of the oscillator frequency. There are no restrictions on the duty cycle of the input signal, but it should be held for at least one full clock cycle to ensure that a given level is sampled at least once before it changes.

Furthermore, the Timer or Counter functions for Timer 0 and Timer 1 have four operating modes: variable width timer, 16-bit auto-reload timer, 8-bit auto-reload timer, and split timer. The control bits C/T in the Special Function Register TMOD select the Timer or Counter function. The bit pairs (M1, M0) in TMOD select the operating modes.

Table 11-1. Timer 0/1 Register Summary

Name Address Purpose Bit-Addressable
TCON 88H	Control	Y
TMOD	89H	Mode	N
TL0	8AH	Timer 0 low-byte	N
TL1	8BH	Timer 1 low-byte	N
TH0	8CH	Timer 0 high-byte	N
TH1	8DH	Timer 1 high-byte	N
TCONB	91H	Mode	N
RL0	92H	Timer 0 reload low-byte	N
RL1	93H	Timer 1 reload low-byte	N
RH0	94H	Timer 0 reload high-byte	N
RH1	95H	Timer 1 reload high-byte	N

11.1 Mode 0 - Variable Width Timer/Counter

Both Timers in Mode 0 are 8-bit Counters with a variable prescaler. The prescaler may vary from 1 to 8 bits depending on the PSC bits in TCONB, giving the timer a range of 9 to 16 bits. By default the timer is configured as a 13-bit timer compatible to Mode 0 in the standard 8051. Figure 11-1 shows the Mode 0 operation as it applies to Timer 1 in 13-bit mode. As the count rolls over from all "1"s to all "0"s, it sets the Timer interrupt flag TF1. The counter input is enabled to the Timer when TR1 = 1 and either GATE = 0 or INT1 = 1. Setting GATE = 1 allows the Timer to be controlled by external input INT1, to facilitate pulse width measurements. TR1 is a control bit in the Special Function Register TCON. GATE is in TMOD. The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should be ignored. Setting the run flag (TR1) does not clear the registers.

$$ \text { Mode 0: Time - out Period } = \frac {2 5 6 \Omega^ {\text { PSC01+ }}}{\text { Oscillator Frequency }} \times (\text { TPS } + 1) $$

Note: RH1/RL1 are not required by Timer 1 during Mode 0 and may be used as temporary storage registers.

Figure 11-1. Timer/Counter 1 Mode 0: Variable Width Counter

graph TD
    OSC --> |÷TPS| A["Control"]
    A --> TL1["TL1 (8 Bits)"]
    TL1 --> PSC1["PSC1"]
    PSC1 --> TH1["TH1 (8 Bits)"]
    TH1 --> TF1["TF1"]
    TF1 --> Interrupt["Interrupt"]
    T1Pin["T1 Pin"] --> A
    GATE["GATE"] --> OR1["OR"]
    INT1Pin["INT1 Pin"] --> OR1
    OR1 --> GATE
    C/T̅ = 0["C/T̅ = 0"] --> A
    C/T̅ = 1["C/T̅ = 1"] --> A

Mode 0 operation is the same for Timer 0 as for Timer 1, except that TR0, TF0 and INTO replace the corresponding Timer 1 signals in Figure 11-1. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

11.2 Mode 1 - 16-bit Auto-Reload Timer/Counter

In Mode 1 the Timers are configured for 16-bit auto-reload. The Timer register is run with all 16 bits. The 16-bit reload value is stored in the high and low reload registers (RH1/RL1). The clock is applied to the combined high and low timer registers (TH1/TL1). As clock pulses are received, the timer counts up: 0000H, 0001H, 0002H, etc. An overflow occurs on the FFFFH-to-0000H transition, upon which the timer register is reloaded with the value from RH1/RL1 and the overflow flag bit in TCON is set. See Figure 11-2. The reload registers default to 0000H, which gives the full 16-bit timer period compatible with the standard 8051. Mode 1 operation is the same for Timer/Counter 0.

$$ \text { Mode 1: Time - out Period } = \frac {(6 5 5 3 6 - {\mathrm{RH0} , \mathrm{RL0} })}{\text { Oscillator Frequency }} \times (\mathrm{TPS} + 1) $$

Figure 11-2. Timer/Counter 1 Mode 1: 16-bit Auto-reload

graph TD
    OSC --> ÷TPS
    ÷TPS --> C/T = 0
    C/T = 0 --> Control
    C/T = 1 --> Control
    Control --> TL1["TL1 (8 Bits)"]
    Control --> TH1["TH1 (8 Bits)"]
    TL1 --> RL1["RL1 (8 Bits)"]
    TH1 --> RH1["RH1 (8 Bits)"]
    RL1 -->|Recall| TF1["TF1"]
    RH1 -->|Recall| TF1
    TF1 --> Interrupt
    GATE --> OR1["OR"]
    INT1 Pin --> OR1
    OR1 --> GATE
    Control --> TR1["TR1"]
    TR1 --> OR1
    OR1 --> C/T = 0

11.3 Mode 2 - 8-bit Auto-Reload Timer/Counter

Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure 11-3. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 2 operation is the same for Timer/Counter 0.

$$ \text { Mode 2: Time - out Period } = \frac {2 5 6 \mathrm{TH0} - (\text { Oscillator Frequency })}{(\mathrm{TPS} + 1)} \times (\text { TPS } + 1) $$

Figure 11-3. Timer/Counter 1 Mode 2: 8-bit Auto-reload

graph TD
    OSC --> ÷TPS
    ÷TPS --> C/T = 0
    C/T = 0 --> Control
    C/T = 1 --> Control
    T1 Pin --> Control
    Control --> TL1["TL1 (8 Bits)"]
    TL1 --> TF1["TF1"]
    TF1 --> Interrupt
    TR1 --> GATE
    GATE --> AND1["AND"]
    AND1 --> Control
    TH1["TH1 (8 Bits)"] --> TH1
    TH1 --> Reload
    INT0 Pin --> GATE

Note: RH1/RL1 are not required by Timer 1 during Mode 2 and may be used as temporary storage registers.

11.4 Mode 3 - 8-bit Split Timer

Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in Figure 11-4. TL0 uses the Timer 0 control bits: C/T, GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting clock cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the Timer 1 interrupt. While Timer 0 is in Mode 3, Timer 1 will still obey its settings in TMOD but cannot generate an interrupt.

Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the AT89LP428/828 can appear to have three Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt.

Figure 11-4. Timer/Counter 0 Mode 3: Two 8-bit Counters

graph TD
    A["OSC"] --> B["÷TPS"]
    C["T0 Pin"] --> B
    B --> D["C/T = 0"]
    D --> E["Control"]
    E --> F["TL0 (8 Bits)"]
    F --> G["TF0"]
    G --> H["Interrupt"]
    I["GATE"] --> J["NOT"]
    K["INT0 Pin"] --> L["AND"]
    M["TR0"] --> L
    L --> E
    N["OSC"] --> O["÷TPS"]
    P["TR1"] --> Q["Control"]
    Q --> R["TH0 (8 Bits)"]
    R --> S["TF1"]
    S --> T["Interrupt"]

Note: RH0/RL0 are not required by Timer 0 during Mode 3 and may be used as temporary storage registers.

Table 11-2. TCON – Timer/Counter Control Register

TCON = 88H Reset Value = 0000 0000B Bit Addressable
	TF1 TR1	TF0 TR0 IE1	IT1 IE0 IT0
B	i	t	7	6	5	4	3	2

Symbol Function
TF1	Timer 1 Overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to interrupt routine.
TR1	Timer 1 Run Control Bit. Set/cleared by software to turn Timer/Counter on/off.
TF0	Timer 0 Overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to interrupt routine.
TR0	Timer 0 Run Control Bit. Set/cleared by software to turn Timer/Counter on/off.
IE1 Interrupt	1 Edge Fla g. Set by hardware when external interrupt edge detected. Cleared when interrupt processed.
IT1	Interrupt 1 Type Control Bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.
IE0	Interrupt 0 Edge Flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed.
IT0	Interrupt 0 Type Control Bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.

Table 11-3. TMOD – Timer/Counter Mode Control Register

TMOD Address = 089H Reset Value = 0000 0000BNot Bit Addressable
	GATE1 C/T1	—	T1M1 T1M0 GATE0 C/T0	T0M0 T0M1	—
B	i	t	7	6	5	4	3	2

Symbol Function
GATE1	Timer 1 Gating Control. When set. Timer/Counter 1 is enabled only while INT1 pin is high and TR1 control pin is set.When cleared, Timer 1 is enabled whenever TR1 control bit is set.
C/T1	Timer or Counter Selector 1. Cleared for Timer operation (input from internal system clock). Set for Counter operation(input from T1 input pin). C/T1 must be zero when using Timer 1 in PWM mode.
T1M1T1M0	Mode T1M1 T1M0 Timer 1 Operation0 0 0 Variable 9 – 16-bit Timer mode. 8-bit Timer/Counter TH1 with TL1 as 1- to 8-bit prescaler.1 0 1 16-bit Auto-reload mode. TH1 and TL1 are cascaded to form a 16-bit Timer/Counter that isreloaded with RH1 and RL1 each time it overflows.2 1 0 8-bit Auto-reload mode. 8-bit Timer/Counter TL1 is reloaded from TH1 each time it overflows.3 1 1 Timer/Counter 1 is stopped
GATE0	Timer 0 Gating Control. When set. Timer/Counter 0 is enabled only while INT0 pin is high and TR0 control pin is set.When cleared, Timer 0 is enabled whenever TR0 control bit is set.
C/T0	Timer or Counter Selector 0. Cleared for Timer operation (input from internal system clock). Set for Counter operation(input from T0 input pin). C/T0 must be zero when using Timer 0 in PWM mode.
T0M1T0M0	Mode T0M1 T0M0 Timer 0 Operation0 0 0 Variable 9 – 16-bit Timer Mode. 8-bit Timer/Counter TH0 with TL0 as 1- to 8-bit prescaler.1 0 1 16-bit Auto-reload mode. TH0 and TL0 are cascaded to form a 16-bit Timer/Counter that isreloaded with RH0 and RL0 each time it overflows.2 1 0 8-bit Auto-reload mode. 8-bit Timer/Counter TL0 is reloaded from TH0 each time it overflows.3 1 1 Split Timer Mode. TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 controlbits. TH0 is an 8-bit timer only controlled by Timer 1 control bits.

Table 11-4. TCONB – Timer/Counter Control Register B

TCONB = 91H Reset Value = 0010 0100BNot Bit Addressable
	PWM1EN	PWM0EN	PSC12	PSC11	PSC10	PSC02	PSC01	PSC00
B	i	t	7	6	5	4	3	2

Symbol Function
PWM1EN	Configures Timer 1 for Pulse Width Modulation output on T1 (P3.5).
PWM0EN	Configures Timer 0 for Pulse Width Modulation output on T0 (P3.4).
PSC1_2-0	Prescaler for Timer 1 Mode 0. The number of active bits in TL1 equals PSC1 + 1 . After reset PSC1 = 100B which enables 5 bits of TL1 for compatibility with the 13-bit Mode 0 in AT89S2051.
PSCO_2-0	Prescaler for Timer 0 Mode 0. The number of active bits in TL0 equals PSC0 + 1 . After reset PSC0 = 100B which enables 5 bits of TL0 for compatibility with the 13-bit Mode 0 in AT89C52.

11.5 Pulse Width Modulation

On the AT89LP428/828, Timer 0 and Timer 1 may be independently configured as 8-bit asymmetrical (edge-aligned) pulse width modulators (PWM) by setting the PWM0EN or PWM1EN bits in TCONB, respectively. In PWM mode the generated waveform is output on the timer's input pin, T0 or T1. Therefore, C/Tx must be set to "0" when in PWM mode and the T0 (P3.4) and T1 (P3.5) must be configured in an output mode. The Timer Overflow Flags and Interrupts will continue to function while in PWM mode and Timer 1 may still generate the baud rate for the UART. The timer GATE function also works in PWM mode, allowing the output to be halted by an external input. Each PWM channel has four modes selected by the mode bits in TMOD.

An example waveform for Timer 0 in PWM mode 0 is shown in Figure 11-5. TH0 acts as an 8-bit counter while RH0 stores the 8-bit compare value. When TH0 is 00H the PWM output is set high. When the TH0 count reaches the value stored in RH0 the PWM output is set low. Therefore, the pulse width is proportional to the value in RH0. To prevent glitches, writes to RH0 only take effect on the FFH to 00H overflow of TH0. Setting RH0 to 00H will keep the PWM output low.

Figure 11-5. 8-bit Asymmetrical Pulse Width Modulation

11.5.1 Mode 0 - 8-bit PWM with 8-bit Logarithmic Prescaler

In Mode 0, TLx acts as a logarithmic prescaler driving 8-bit counter THx (see Figure 11-6). The PSCx bits in TCONB control the prescaler value. On THx overflow, the duty cycle value in RHx is transferred to OCRx and the output pin is set high. When the count in THx matches OCRx, the output pin is cleared low. The following formulas give the output frequency and duty cycle for Timer 0 in PWM mode 0. Timer 1 in PWM mode 0 is identical to Timer 0.

$$ \text { Mode 0: } \quad f _ {\text { OUT }} = \frac {\text { Oscillator Frequency }}{2 5 6 2 ^ {\text { PSC01+ }}} \times \frac {1}{\text { TPS1+ }} \text { Duty Cycle \% 100 } \times \frac {\text { RH0 }}{2 5 6} $$

Figure 11-6. Timer/Counter 1 PWM Mode 0

graph TD
    A["OSC"] --> B["÷TPS"]
    B --> C["Control"]
    C --> D["TL1 (8 Bits)"]
    D --> E["PSC1"]
    E --> F["TH1 (8 Bits)"]
    F --> G["T1"]
    H["GATE"] --> I["OR"]
    J["INT1 Pin"] --> K["AND"]
    L["TR1"] --> M["AND"]
    M --> N["AND"]
    O["RH1 (8 Bits)"] --> P["OCR1"]
    P --> Q["="]
    Q --> R["TH1 (8 Bits)"]
    R --> S["T1"]
    T["Control"] --> U["TL1 (8 Bits)"]
    U --> V["PSC1"]
    V --> W["TH1 (8 Bits)"]
    W --> X["T1"]

11.5.2 Mode 1 - 8-bit PWM with 8-bit Linear Prescaler

In Mode 1, TLx provides linear prescaling with an 8-bit auto-reload from RLx (see Figure 11-7 on page 49). On TLx overflow, TLx is loaded with the value of RLx. THx acts as an 8-bit counter. On THx overflow, the duty cycle value in RHx is transferred to OCRx and the output pin is set high. When the count in THx matches OCRx, the output pin is cleared low. The following formulas give the output frequency and duty cycle for Timer 0 in PWM mode 1. Timer 1 in PWM mode 1 is identical to Timer 0.

$$ \text { Mode 1: } \quad f _ {\text { OUT }} = \frac {\text { Oscillator Frequency }}{2 5 6 \times (2 5 6 - \text { RL0 })} \times = \frac {1}{\text { TPS1+ }} \text { Duty Cycle } \% 1 0 0 \times = \frac {\text { RH0 }}{2 5 6} $$

Figure 11-7. Timer/Counter 1 PWM Mode 1

graph TD
    A["OSC"] --> B["÷TPS"]
    B --> C["Control"]
    C --> D["TL1 (8 Bits)"]
    D --> E["TH1 (8 Bits)"]
    E --> F["T1"]
    G["GATE"] --> H["OR"]
    I["INT1 Pin"] --> H
    H --> J["TR1"]
    J --> K["AND"]
    K --> C
    L["RL1 (8 Bits)"] --> M["NOT"]
    M --> D
    N["OCR1"] --> O["="]
    O --> P["T1"]
    Q["RH1 (8 Bits)"] --> R["NOT"]
    R --> O
    S["Ground"] --> T["T1"]

11.5.3 Mode 2 - 8-bit Frequency Generator

Timer 0 in PWM mode 2 functions as an 8-bit Auto-reload timer, the same as normal Mode 2, with the exception that the output pin T0 is toggled at every TL0 overflow (see Figure 11-8 and Figure 11-9 on page 50). Timer 1 in PWM mode 2 is identical to Timer 0. PWM mode 2 can be used to output a square wave of varying frequency. THx acts as an 8-bit counter. The following formula gives the output frequency for Timer 0 in PWM mode 2.

$$ \text { Mode 2: } f \quad \text { OUT } \quad \frac {\text { Oscillator Frequency }}{2 2 5 6} \times \frac {1}{\text { TTPSII } + 0} - ( $$

Figure 11-8. Timer/Counter 1 PWM Mode 2

graph LR
    OSC --> ÷TPS
    ÷TPS --> TL1["TL1 (8 Bits)"]
    TL1 --> X((X))
    X --> T1["T1"]
    TH1["TH1 (8 Bits)"] --> TL1
    TL1 --> Control
    Control --> GATE["GATE"]
    Control --> INT1_Pin["INT1 Pin"]
    TR1["TR1"] --> AND((AND))
    AND --> Control

Note: {RH0 & RL0}/{RH1 & RL1} are not required by Timer 0/Timer 1 during PWM mode 2 and may be used as temporary storage registers.

Figure 11-9. PWM Mode 2 Waveform

FFh THx Tx

11.5.4 Mode 3 – Split 8-bit PWM

Timer 1 in PWM mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in PWM mode 3 establishes TL0 and TH0 as two separate PWM counters in a manner similar to normal mode 3. PWM mode 3 on Timer 0 is shown in Figure 11-10. Only the Timer Prescaler is available to change the output frequency during PWM mode 3. TL0 can use the Timer 0 control bits: GATE, TR0, INT0, PWM0EN and TF0. TH0 is locked into a timer function and uses TR1, PWM1EN and TF1. RL0 provides the duty cycle for TL0 and RH0 provides the duty cycle for TH0.

PWM mode 3 is for applications requiring a single PWM channel and two timers, or two PWM channels and an extra timer or counter. With Timer 0 in PWM mode 3, the AT89LP428/828 can appear to have three Timer/Counters. When Timer 0 is in PWM mode 3, Timer 1 can be turned on and off by switching it out of and into its own mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt. The following formulas give the output frequency and duty cycle for Timer 0 in PWM mode 3.

$$ \text { Mode 3: } f \quad \text { OUT } \quad \frac {\text { Oscillator Frequency }}{2 5 6} \times \frac {1}{\text { TPS1+ }} $$

$$ \text { Mode 3, T0: Duty Cycle } \% 1 0 0 \quad \times \frac {\mathrm{RL0}}{2 5 6} $$

$$ \text { Mode 3, T1: Duty Cycle } \% 1 0 0 \quad \times \frac {\mathrm{RH0}}{2 5 6} $$

Figure 11-10. Timer/Counter 0 PWM Mode 3

graph TD
    A["OSC"] --> B["÷TPS"]
    B --> C{Control}
    C --> D["TL0 (8 Bits)"]
    D --> E["T0"]
    F["GATE"] --> G["OR"]
    H["INT0 Pin"] --> I["AND"]
    I --> J["AND"]
    J --> C
    K["TR0"] --> L["AND"]
    M["RL0 (8 Bits)"] --> N["OCR0"]
    N --> O["="]
    O --> P["T0"]
    Q["TH0 (8 Bits)"] --> R["OCR1"]
    R --> S["="]
    S --> T["T1"]
    U["OSC"] --> V["÷TPS"]
    V --> W{Control}
    W --> X["TH0 (8 Bits)"]
    X --> Y["T1"]

12. Enhanced Timer 2

The AT89LP428/828 includes a 16-bit Timer/Counter 2 with the following features:

• 16-bit timer/counter with one 16-bit reload/capture register
  • One external reload/capture input
• Up/Down counting mode with external direction control
• UART baud rate generation
• Output-pin toggle on timer overflow
• Dual slope symmetric operating modes

Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON and T2MOD, as shown in Table 12-3. Timer 2 also serves as the time base for the Compare/Capture Array (see "Compare/Capture Array" on page 61).

Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the register is incremented every clock cycle. Since a clock cycle consists of one oscillator period, the count rate is equal to the oscillator frequency. The timer rate can be prescaled by a value between 1 and 16 using the Timer Prescaler (see Table 6-2 on page 23).

In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled every clock cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during the cycle following the one in which the transition was detected. Since two clock cycles are required to recognize a 1-to-0 transition, the maximum count rate is 1/2 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full clock cycle.

Table 12-1. Timer 2 Operating Modes

RCLK + TCLK CP/RL2 DC EN T2OE TR2 Mode
0	0	0	0	1	16-bit Auto-reload
0	0	1	0	1	16-bit Auto-reload Up-down
0	1	X	0	1	16-bit Capture
1	X	X	X	1	Baud Rate Generator
X	X	X	1	1	Frequency Generator
X	X	X	X	0	(Off)

The following definitions for Timer 2 are used in the subsequent paragraphs:

Table 12-2. Timer 2 Definitions

Symbol	Definition
MIN	0000H
MAX	FFFFH
BOTTOM	16-bit value of {RCAP2H,RCAP2L} (standard modes)
TOP	16-bit value of {RCAP2H,RCAP2L} (enhanced modes)

12.1 Timer 2 Registers

Control and status bits for Timer 2 are contained in registers T2CON (see Table 12-3) and T2MOD (see Table 12-4). The register pair {TH2, TL2} at addresses 0CDH and 0CCH are the 16-bit timer register for Timer 2. The register pair {RCAP2H, RCAP2L} at addresses 0CBH and 0CAH are the 16-bit Capture/Reload register for Timer 2 in capture and auto-reload modes.

Table 12-3. T2CON – Timer/Counter 2 Control Register

T2CON Address = 0C8H Reset Value = 0000 0000BBit Addressable
	TF2 EXF2	RCLK TCLK	EXEN2 TR2 C/T2 CP/RL2			—	—
B	i	t	7	6	5	4	3	2

Symbol Function
TF2	Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1.
EXF2	Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1) or dual-slope mode.
RCLK	Receive Clock Enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock.
TCLK	Transmit Clock Enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2	Timer 2 External Enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2	Start/Stop Control for Timer 2. TR2 = 1 starts the timer.
C/T2	Timer or Counter Select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).
CP/RL2	Capture/Reload Select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

Table 12-4. T2MOD – Timer 2 Mode Control Register

T2MOD Address = 0C9H Reset Value = 0000 0000BNot Bit Addressable
	PHSD	PHS2	PHS1	PHS0	T2CM1	T2CM0	T2OE	DCEN
B	i	t	7	6	5	4	3	2
Symbol Function
PHSD	CCA Phase Direction. For phase modes with 3 or 4 channels, PHSD determines the direction that the channels are cycled through. PHSD also determines the initial phase relationship for 2 phase modes.PHSD Direction0 A→B→A→B or A→B→C→A→B→C or A→B→C→D→A→B→C→D1 B→A→B→A or C→B→A→C→B→A or D→C→B→A→D→C→B→A
PHS[2 - 0]	CCA Phase Mode. PWM channels may be grouped by 2, 3 or 4 such that only one channel in a group produces a pulse in any one period. The PHS [2 - 0] bits may only be written when the timer is not active, i.e. TR2 = 0.PHS2 PHS1 PHS0 Phase Mode0 0 0 Disabled, all channels active0 0 1 2-phase output on channels A & B0 1 0 3-phase output on channels A, B & C0 1 1 4-phase output on channels A, B, C & D1 0 0 Dual 2-phase output on channels A & B and C & D1 0 1 reserved1 1 0 reserved1 1 1 reserved
T2CM[1 - 0]	Timer 2 Count Mode.T2CM1 T2CM0 Count Mode0 0 Standard Timer 2 (up count: BOTTOM→MAX)0 1 Clear on RCAP compare (up count: MIN→TOP)1 0 Dual-slope with single update (up-down count: MIN→TOP→MIN)1 1 Dual-slope with double update (up-down count: MIN→TOP→MIN)
T2OE	Timer 2 Output Enable. When T2OE = 1 and C/T2 = 0, the T2 pin will toggle after every Timer 2 overflow.
DCEN	Timer 2 Down Count Enable. When Timer 2 operates in Auto-reload mode and EXEN2 = 1, setting DCEN = 1 will cause Timer 2 to count up or down depending on the state of T2EX.

12.2 Capture Mode

In the Capture mode, Timer 2 is a fixed 16-bit timer or counter that counts up from MIN to MAX. An overflow from MAX to MIN sets bit TF2 in T2CON. If EXEN2 = 1, a 1-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 and TF2 bits can generate an interrupt. Capture mode is illustrated in Figure 12-1. The Timer 2 overflow rate in Capture mode is given by the following equation:

$$ \text { Capture Mode: } \quad \text { Time - out Period } = \frac {6 5 5 3 6}{\text { Oscillator Frequency }} \times (\text { TPS } + 1) $$

Figure 12-1. Timer 2 Diagram: Capture Mode

graph TD
    A["OSC"] --> B["÷TPS"]
    B --> C["C/T2 = 0"]
    C --> D["TR2"]
    D --> E["TL2 TH2"]
    E --> F["TF2"]
    F --> G["TIMER 2 INTERRUPT"]
    H["T2 PIN"] --> I["TRANSITION DETECTOR"]
    I --> J["EXEN2"]
    J --> K["EXF2"]
    K --> L["RCAP2HRCAP2L"]
    L --> M["OVERFLOW"]
    M --> N["T2 EX PIN"]
    style A fill:#f9f,stroke:#333
    style H fill:#ccf,stroke:#333
    style I fill:#cfc,stroke:#333
    style J fill:#fcc,stroke:#333
    style K fill:#cff,stroke:#333
    style L fill:#ffc,stroke:#333
    style M fill:#fcf,stroke:#333
    style N fill:#cff,stroke:#333

12.3 Auto-Reload Mode

Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 12-4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin. The overflow and reload values depend on the Timer 2 Count Mode bits, T2CM_1 - 0 in T2MOD. A summary of the Auto-reload behaviors is listed in Table 12-5.

Table 12-5. Summary of Auto-reload Modes

T2CM _1-0	DCEN T2EX Direction Behavior
00	0	X	Up	BOTTOM →MAX reload to BOTTOM
00	1	0	Down	MAX →BOTTOM underflow to MAX
00	1	1	Up	BOTTOM →MAX overflow to BOTTOM
01	0	X	Up	MIN →TOP reload to MIN
01	1	0	Down	TOP →MIN underflow to TOP
01	1	1	Up	MIN →TOP overflow to MIN
10	X	X	Up-down	MIN →TOP →MIN and repeat
11	X	X	Up-down	MIN →TOP →MIN and repeat

12.3.1 Up Counter

Figure 12-2 shows Timer 2 automatically counting up when DCEN = 0 and T2CM _1-0 = 00B. In this mode Timer 2 counts up to MAX and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with BOTTOM, the 16-bit value in RCAP2H and RCAP2L. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt. The Timer 2 overflow rate for this mode is given in the following equation:

$$ \begin{array}{l} \text {Auto - Reload Mode:} \ \mathrm{DCEN} = 0, \mathrm{T2CM} = 0 0 \mathrm{B} \end{array} \quad \text {Time - out Period} = \frac {6 5 5 3 6 _ \text {RCAP2H} _ \text {RCAP2L} {}}{\text {Oscillator Frequency}} \times (\mathrm{TPS} + 1) $$

Timer 2 may also be configured to count from MIN to TOP instead of BOTTOM to MAX by setting T2CM _1-0 = 01B. In this mode Timer 2 counts up to TOP, the 16-bit value in RCAP2H and RCAP2L and then overflows. The overflow sets TF2 and causes the timer registers to be reloaded with MIN. If EXEN2 = 1, a 1-to-0 transition on T2EX will clear the timer and set EXF2. The Timer 2 overflow rate for this mode is given in the following equation:

$$ \begin{array}{l} \text {Auto - Reload Mode:} \ \mathrm{DCEN=0,T2CM=01B} \end{array} \quad \text {Time - out Period} = \frac {\mathrm{RCAP2HRCAP2L} {\text {Oscillator Frequency}}{\times (\mathrm{TPS+1})} \tag {1} $$

Timer 2 Count Mode 1 is provided to support variable precision asymmetrical PWM in the CCA. The value of TOP stored in RCAP2H and RCAP2L is double-buffered such that a new TOP value takes affect only after an overflow. The behavior of Count Mode 0 versus Count Mode 1 is shown in Figure 12-3.

Figure 12-2. Timer 2 Diagram: Auto-reload Mode (DCEN = 0)

graph TD
    A["OSC"] --> B["÷TPS"]
    B --> C["C/T2 = 0"]
    C --> D["TR2"]
    D --> E["TL2"]
    D --> F["TH2"]
    E --> G["RCAP2L"]
    E --> H["RCAP2H"]
    F --> I["Overflow"]
    G --> J["RELOAD"]
    H --> K["TF2"]
    H --> L["EXF2"]
    M["T2 PIN"] --> N["T2EX PIN"]
    O["C/T2 = 1"] --> P["Transition Detector"]
    P --> Q["EXEN2"]
    Q --> R["Timer 2 Interrupt"]

Figure 12-3. Timer 2 Waveform: Auto-reload Mode (DCEN = 0)

12.3.2 Up or Down Counter

Setting DCEN = 1 enables Timer 2 to count up or down, as shown in Figure 12-4. In this mode, the T2EX pin controls the direction of the count (if EXEN2 = 1). A logic 1 at T2EX makes Timer 2 count up. When T2CM _1-0 = 00B, the timer will overflow at MAX and set the TF2 bit. This overflow also causes BOTTOM, the 16-bit value in RCAP2H and RCAP2L, to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal BOTTOM, the 16-bit value stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes MAX to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.

When T2EX = 1 and T2CM _1-0 = 01B, the timer will overflow at TOP and set the TF2 bit. This overflow also causes MIN to be reloaded into the timer registers. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal MIN. The underflow sets the TF2 bit and causes TOP to be reloaded into the timer registers. The behavior of Count Mode 0 versus Count Mode 0 when DCEN is enabled is shown in Figure 12-5. EXF2 is not toggle in this mode.

Figure 12-4. Timer 2 Diagram: Auto-reload Mode (T2CM _1-0 = 00B, DCEN = 1)

graph TD
    A["OSC"] --> B["÷TPS"]
    B --> C["C/T2 = 0"]
    C --> D["TR2"]
    D --> E["TL2"]
    E --> F["TH2"]
    F --> G["Overflow"]
    G --> H["TF2"]
    H --> I["Timer 2 Interrupt"]
    J["OSC"] --> K["T2 PIN"]
    K --> L["C/T2 = 1"]
    L --> M["TR2"]
    M --> N["TL2"]
    N --> O["TH2"]
    O --> P["Overflow"]
    P --> Q["TF2"]
    Q --> R["Timer 2 Interrupt"]
    S["(Down Counting Reload Value)"] --> T["0FFH"]
    S --> U["0FFH"]
    T --> V["RCAP2L"]
    T --> W["RCAP2H"]
    V --> X["Count Direction 1 = Up 0 = Down"]
    W --> X
    X --> Y["T2EX PIN"]
    Z["Toggle"] --> AA["EXF2"]

The timer overflow/underflow rate for up-down counting mode is the same as for up counting mode, provided that the count direction does not change. Changes to the count direction may result in longer or shorter periods between time-outs.

Figure 12-5. Timer 2 Waveform: Auto-reload Mode (DCEN = 1)

12.3.3 Dual Slope Counter

When Timer 2 Auto-reload mode uses Count Mode 2 (T2CM 1-0 = 10B) or Count Mode 3 (T2CM 1-0 = 11B), the timer operates in a dual slope fashion. The timer counts up from MIN to TOP and then counts down from TOP to MIN, following a sawtooth waveform as shown in Figure 12-6. The EXF2 bit is set/cleared by hardware to reflect the current count direction (Up = 0 and Down = 1). The value of TOP stored in RCAP2H and RCAP2L is double-buffered such that a new TOP value takes affect only after an underflow. The only difference between Mode 2 and Mode 3 is when the interrupt flag is set. In Mode 2, TF2 is set once per count period when the timer underflows at MIN. In Mode 3, TF2 is set twice per count period, once when the timer overflows at TOP and once when the timer underflows at MIN. The interrupt service routine can check the EXF2 bit to determine if TF2 was set at TOP or MIN. These count modes are provided to support variable precision symmetrical PWM in the CCA. DCEN has no effect when using dual slope operation. The Timer 2 overflow rate for this mode is given in the following equation:

$$ \begin{array}{l} \text {Auto - Reload Mode:} \ \mathrm{DCEN} = 0, \mathrm{T2CM} = 1 0 \mathrm{B} \end{array} \quad \text {Time - out Period} = \frac {\text {RCAP2H RCAP2L}}{\text {Oscillator Frequency}} \times (\mathrm{TPS} + 1) \quad } $$

Figure 12-6. Timer 2 Waveform: Dual Slope Modes

12.4 Baud Rate Generator

Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 12-3 on page 53). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 12-7.

The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software.

The baud rates in UART modes 1 and 3 are determined by Timer 2's overflow rate according to the following equation.

$$ \text { Modes 1 and 3 Baud Rates } \quad \frac {\text { Timer 2 Overflow Rate }}{1 6} = $$

The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (CP/T2 = 0). The baud rate formulas are given below

$$ \mathrm{T2CM} = 0 0 \mathrm{B} \quad \begin{array}{l} \text { Modes 1,3 } \ \text { Baud Rate } \end{array} = \frac {\text { Oscillator Frequency }}{1 6 \times (\mathrm{TPS} + 1) \times [ 6 5 5 3 6 - (\mathrm{RCAP2H} , \mathrm{RCAP2L}) ]} $$

$$ \mathrm{T2CM} = 0 1 \mathrm{B} \quad \begin{array}{l} \text { Modes 1,3 } \ \text { Baud Rate } \end{array} = \frac {\text { Oscillator Frequency }}{1 6 \times (\mathrm{TPS} + 1) \times [ (\mathrm{RCAP2H} , \mathrm{RCAP2L}) + 1 ]} $$

where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.

Timer 2 as a baud rate generator is shown in Figure 12-7. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Also note that the Baud Rate and Frequency Generator modes may be used simultaneously.

Figure 12-7. Timer 2 in Baud Rate Generator Mode

graph TD
    A["OSC"] --> B["÷TPS"]
    B --> C["C/T2 = 0"]
    C --> D["TR2"]
    D --> E["TL2 TH2"]
    E --> F["RCAP2HRCAP2L"]
    F --> G["TCLK"]
    G --> H["Tx Clock"]
    I["T2 PIN"] --> J["Transition Detector"]
    J --> K["EXEN2"]
    K --> L["EXF2"]
    L --> M["Timer 2 Interrupt"]
    N["T2EX PIN"] --> O["Transition Detector"]
    O --> P["EXEN2"]
    P --> Q["EXF2"]
    Q --> R["Timer 2 Interrupt"]
    S["Timer 1 Overflow"] --> T["÷2"]
    T --> U["0"] & V["1"]
    U --> W["SMOD1"]
    X["RCLK"] --> Y["÷16"]
    Y --> Z["Rx Clock"]
    AA["TCLK"] --> AB["÷16"]
    AB --> AC["Tx Clock"]

12.5 Frequency Generator (Programmable Clock Out)

Timer 2 can generate a 50% duty cycle clock on T2 (P1.0), as shown in Figure 12-8. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to toggle its output at every timer overflow. To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer.

The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equations.

$$ \mathrm{T2CM} = 0 0 \mathrm{B} \quad \text { Clock Out Frequency } = \frac {\text { Oscillator Frequency }}{2 \times [ 6 5 5 3 6 - (\mathrm{RCAP2H} , \mathrm{RCAP2L}) ]} \times \frac {1}{\mathrm{TPS1}} $$

$$ \mathrm{T2CM} = 0 1 \mathrm{B} \quad \text { Clock Out Frequency } = \frac {\text { Oscillator Frequency }}{2 \times [ (\mathrm{RCAP2H} , \mathrm{RCAP2L}) + 1 ]} \times \frac {1}{\mathrm{TPS1}} $$

In the frequency generator mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L.

Figure 12-8. Timer 2 in Clock-out Mode

graph TD
    OSC --> ÷TPS
    ÷TPS --> A["Amplifier"]
    A --> TR2
    TR2 --> TL2_TH2
    TL2_TH2 --> RCAP2HRCAP2L
    RCAP2HRCAP2L --> T2OE
    T2OE --> ÷2
    ÷2 --> EXF2
    EXF2 --> Timer2_Interrupt
    T2EX_PIN --> TransitionDetector
    TransitionDetector --> EXEN2
    EXEN2 --> EXF2
    C/T2 --> A
    T2_PIN --> ÷TPS

13. Compare/Capture Array

The AT89LP428/828 includes a four channel Compare/Capture Array (CCA) that performs a variety of timing operations including input event capture, output compare waveform generation and pulse width modulation (PWM). Timer 2 serves as the time base for the four 16-bit compare/capture modules. The CCA has the following features:

• Four 16-bit Compare/Capture channels
• Common time base provided by Timer 2
- Selectable external and internal capture events including pin change, timer overflow and comparator output change

- Symmetric/Asymmetric PWM with selectable polarity

• Multi-phasic PWM outputs

- One interrupt flag per channel with a common interrupt vector

The block diagram of the CCA is given in Figure 13-1. Each channel consists of an 8-bit control register and a 16-bit data register. The channel registers are not directly accessible. The CCA address register T2CCA provides an index into the array. The control, data low and data high bytes of the currently indexed channel are accessed through the T2CCC, T2CCL and T2CCH registers, respectively.

Each channel can be individually configured for capture or compare mode. Capture mode is the default setting. During capture mode, the current value of the time base is copied into the channel's data register when the specified external or internal event occurs. An interrupt flag is set at the same time and the time base may be optionally cleared. To enable compare mode, the CCMx bit in the channel's control register (CCCx) should be set to 1. In compare mode an interrupt flag is set and an output pin is optionally toggled when the value of the time base matches the value of the channel's data register. The time base may also be optionally cleared on a compare match.

Timer 2 must be running (TR2 = 1) in order to perform captures or compares with the CCA. However, when TR2 = 0 the external capture events will still set their associated flags and may be used as additional external interrupts.

Figure 13-1. Compare/Capture Array Block Diagram

graph TD
    OSC --> ÷TPS
    ÷TPS --> C/T2 = 0
    C/T2 = 0 --> TF2
    TF2 --> Timer2 Interrupt
    TF2 --> T2CCF
    TF2 --> T2CCA
    TF2 --> T2CCC
    TF2 --> T2CCL
    TF2 --> T2CCH
    TF2 --> CCAL
    TF2 --> CCBL
    TF2 --> CCCL
    TF2 --> CCDL
    TF2 --> CCCH
    TF2 --> CCDD
    TF2 --> CCCH
    TF2 --> CCDD
    TF2 --> CCCH
    TF2 --> CCDD
    TF2 --> CCCH
    TF2 --> CCDD
    TF2 --> CCCH
    TF2 --> CCDD
    TF2 --> CCCH
    TF2 --> CCDD
    TF2 --> CCCH
    TF2 --> CCDD
    TF2 --> CCCH
    TF2 --> CCDD

13.1 CCA Registers

The Compare/Capture Array has five Special Function Registers: T2CCA, T2CCC, T2CCL, T2CCH and T2CCF. The T2CCF register contains the interrupt flags for each CCA channel. The CCA interrupt is a logic OR of the bits in T2CCF. The flags are set by hardware when a compare/capture event occurs on the relevant channel and must be cleared by software. The T2CCF bits will only generate an interrupt when the ECC bit (IE2.1) is set and the CIENx bit in the associated channel's CCCx register is set.

The T2CCC, T2CCL and T2CCH register locations are not true SFRs. These locations represent access points to the contents of the array. Writes/reads to/from the T2CCC, T2CCL and T2CCH locations will access the control, data low and data high bytes of the CCA channel currently selected by the index in T2CCA. Channels currently not indexed by T2CCA are not accessible.

When writing to T2CCH, the value is stored in a shadow register. When T2CCL is written, the 16-bit value formed by the contents of T2CCL and the T2CCH shadow is written into the array. Therefore, T2CCH must be written prior to writing T2CCL. All four channels use the same T2CCH shadow register. If the value of T2CCH remains constant for multiple writes, there is no need to update T2CCH between T2CCL writes. Every write to T2CCL will use the last value of T2CCH for the upper data byte. It is not possible to write to the data register of a channel configured for capture mode.

The configuration bits for each channel are stored in the CCCx registers accessible through T2CCC. See Table 13-4 on page 64 for a description of the CCCx register.

Table 13-1. T2CCA – Timer/Counter 2 Compare/Capture Address

T2CCA Address = 0D1H Reset Value = xxxx xx00BNot Bit Addressable
	- - - - -	- T2CCA.1	T2CCA.0
B	i	t	7	6	5	4	3	2
Symbol Function
T2CCA[1 - 0]	Compare/Capture Address. Selects which CCA channel is currently accessible through the T2CCH, T2CCL and T2CCC registers. Only one channel may be accessed at a time.T2CCA1 T2CCA0 Channel
	0	0	A – T2CCH, T2CCL and T2CCC access data and control for Channel A
	0	1	B – T2CCH, T2CCL and T2CCC access data and control for Channel B
	1	0	C – T2CCH, T2CCL and T2CCC access data and control for Channel C
	1	1	D – T2CCH, T2CCL and T2CCC access data and control for Channel D

Table 13-2. T2CCH – Timer/Counter 2 Compare/Capture Data High

T2CCH Address = 0D2H Reset Value = 0000 0000BNot Bit Addressable
	T2CCD.15	T2CCD.14	T2CCD.13	T2CCD.12	T2CCD.11	T2CCD.10	T2CCD.9	T2CCD.8
B	i	t	7	6	5	4	3	2
Symbol Function
T2CCD[15 - 8]	Compare/Capture Data (High Byte). Reads from T2CCH will return the high byte from the CCA channel currently selected by T2CCA. The high byte of the selected CCA channel will be updated with the contents of T2CCH when T2CCL is written. When writing multiple channels with the same high byte, T2CCH need not be updated between writes to T2CCL.

Note: All writes/reads to/from T2CCH will access channel X as currently selected by T2CCA. The data registers for the remaining unselected channels are not accessible.

Table 13-3. T2CCL – Timer/Counter 2 Compare/Capture Data Low

T2CCC Address = 0D3H Reset Value = 0000 0000BNot Bit Addressable
	T2CCD.7	T2CCD.6	T2CCD.5	T2CCD.4	T2CCD.3	T2CCD.2	T2CCD.1	T2CCD.0
B	i	t	7	6	5	4	3	2
Symbol Function
T2CCD[7 - 0]	Compare/Capture Data (Low Byte). Reads from T2CCL will return the low byte from the CCA channel currently selected by T2CCA. Writes to T2CCL will update the selected CCA channel with the 16-bit contents of T2CCH and T2CCL.

Note: All writes/reads to/from T2CCL will access channel X as currently selected by T2CCA. The data registers for the remaining unselected channels are not accessible.

Table 13-4. T2CCC – Timer/Counter 2 Compare/Capture Control

T2CCC Address = 0D4H Reset Value = 00X0 0000BNot Bit Addressable
	CIENx	CDIRx	-	CTCx	CCMx	CxM2	CxM1	CxM0
B	i	t	7	6	5	4	3	2
Symbol	Function
CIENx	Channel X Interrupt Enable. When set, channel X's interrupt flag, CCFx in T2CCF, will generate an interrupt when ECC = 1. Clear to disable interrupts from channel X.
CDIRx	Channel X Capture Direction. In dual-slope modes, a compare/capture event on channel X will store the current count direction into CDIRx. Up-counting = 0 and down-counting = 1. Modifying this bit has no effect.
CTCx	Clear Timer on Compare/Capture of Channel X. When set, the Timer 2 registers TL2 and TH2 will be cleared by a compare/capture event on channel X. When cleared, Timer 2 is unaffected by channel X events.
CCMx	Channel X Compare/Capture Mode. When CCMx = 1, channel X operates in compare mode. When CCMx = 0, channel X operates in capture mode.
CxM[2 - 0]	Channel X Mode. Selects the output/input events for compare/capture channel X.CxM2 CxM1 CxM0 Capture Event (CCMx = 0)0 0 0 Disabled0 0 1 Trigger on negative edge of CCx pin0 1 0 Trigger on positive edge of CCx pin0 1 1 Trigger on either edge of CCx pin1 0 0 Trigger on Timer 0 overflow1 0 1 Trigger on Timer 1 overflow1 1 0 Trigger on Analog Comparator A Event(2)1 1 1 Trigger on Analog Comparator B Event(3)
	CxM2	CxM1	CxM0	Compare Action (CCMx = 1)0 0 0 Output disabled (interrupt only)0 0 1 Set CCx pin on compare match0 1 0 Clear CCx pin on compare match0 1 1 Toggle CCx pin on compare match1 0 0 Inverting Pulse Width Modulation(4)1 0 1 Non-inverting Pulse Width Modulation(4)1 1 0 Reserved1 1 1 Reserved

Notes: 1. All writes/reads to/from T2CCC will access channel X as currently selected by T2CCA. The control registers for the remaining unselected channels are not accessible.

1. Analog Comparator A events are determined by the CMA _2-0 bits in ACSRA. See Table 18-1 on page 102.

2. Analog Comparator B events are determined by the CMB_2-0 bits in ACSRB. See Table 18-2 on page 103.

3. Asymmetrical versus Symmetrical PWM is determined by the Timer 2 Count Mode. See "Pulse Width Modulation Mode" on page 68.

Table 13-5. T2CCF – Timer/Counter 2 Compare/Capture Flags

T2CCF Address = 0D5H Reset Value = XXXX 0000BNot Bit Addressable
	- - - -	CCFD CCFC C	CFB CCFA
B	i	t	7	6	5	4	3	2

Symbol Function
CCFD	Channel D Compare/Capture Interrupt Flag. Set by a compare/capture event on channel D. Must be cleared by software. CCFD will generate an interrupt when CIEND = 1 and ECC = 1.
CCFC	Channel C Compare/Capture Interrupt Flag. Set by a compare/capture event on channel C. Must be cleared by software. CCFC will generate an interrupt when CIENC = 1 and ECC = 1.
CCFB	Channel B Compare/Capture Interrupt Flag. Set by a compare/capture event on channel B. Must be cleared by software. CCFB will generate an interrupt when CIENB = 1 and ECC = 1.
CCFA	Channel A Compare/Capture Interrupt Flag. Set by a compare/capture event on channel A. Must be cleared by software. CCFA will generate an interrupt when CIENA = 1 and ECC = 1.

13.2 Input Capture Mode

The Compare/Capture Array provides a variety of capture modes suitable for time-stamping events or performing measurements of pulse width, frequency, slope, etc. The CCA channels are configured for capture mode by clearing the CCMx bit in the associated CCCx register to 0. Each time a capture event occurs, the contents of Timer 2 (TH2 and TL2) are transferred to the 16-bit data register of the corresponding channel, and the channel's interrupt flag CCFx is set in T2CCF. Optionally, the capture event may also clear Timer 2 to 0000H by setting the CTCx bit in CCCx. The capture event is defined by the CxM_2 - 0 bits in CCCx and may be either externally or internally generated. A diagram of a CCA channel in capture mode is shown in Figure 13-2.

Figure 13-2. CCA Capture Mode Diagram

graph TD
    A["(P2.x) CCx"] --> B["Flip-Flop 0"]
    A --> C["Flip-Flop 1"]
    A --> D["Flip-Flop 2"]
    A --> E["Flip-Flop 3"]
    B --> F["Comparator A"]
    C --> G["Comparator B"]
    D --> H["Comparator C"]
    E --> I["Comparator D"]
    F --> J["CCxL"]
    G --> K["CCxH"]
    H --> L["T2CCL"]
    I --> M["T2CCH"]
    J --> N["CCFx"]
    K --> O["CCCx"]
    L --> P["T2CCC"]
    M --> Q["Interrupt"]
    N --> R["CIENx"]
    O --> S["CxM2-0"]
    P --> T["CTCx"]
    Q --> U["CTCx"]
    R --> V["TL2"]
    S --> W["TH2"]
    T --> X["00H"]
    U --> Y["00H"]

Each CCA channel has an associated external capture input pin: CCA (P2.0), CCB (P2.1), CCC (P2.2) and CCD (P2.3). External capture events are always edge-triggered and can be selected to occur at a negative edge, positive edge, or both (toggle). Capture inputs are sampled every clock cycle and a new value must be held for at least 2 clock cycles to be correctly sampled by the device. The maximum achievable capture rate will be determined by how fast the software can retrieve the captured data. There is no protection against capture events overrunning the data register.

Capture events may also be triggered internally by the overflows of Timer 0 or Timer 1, or by an event from the dual analog comparators. Any comparator event which can generate a comparator interrupt may also be used as a capture event. However, Timer 2 should not be selected as the comparator clock source when using the comparator as the capture trigger.

13.2.1 Timer 2 Operation for Capture Mode

Capture channels are intended to work with Timer 2 in capture mode CP/RL2 = 1. Captures can still occur when Timer 2 operates in other modes; however, the full 16-bit count range may not be available. The TF2 flag can be used to determine if the timer overflowed before the capture occurred. If the timer is operating in dual-slope mode (CP/RL2 = 0, T2G.M=1xB), the count direction (Up = 0 and Down = 1) at the time of the event will be captured into the channel's CDIRx bit in CCCx. CTCx must be cleared to 0 for all channels if Timer 2 is operating in Baud Rate mode or errors may occur in the serial communication.

13.3 Output Compare Mode

The Compare/Capture Array provides a variety of compare modes suitable for event timing or waveform generation. The CCA channels are configured for compare mode by setting the CCMx bit in the associated CCCx register to 1. A compare event occurs when the 16-bit contents of a channel's data register match the contents of Timer 2 (TH2 and TL2). The compare event also sets the channel's interrupt flag CCFx in T2CCF and may optionally clear Timer 2 to 0000H if the CTCx bit in CCCx is set. A diagram of a CCA channel in compare mode is shown in Figure 13-3.

Figure 13-3. CCA Compare Mode Diagram

graph TD
    A["00H 00H"] --> B["TL2 TH2"]
    B --> C["="]
    C --> D["CCxL CCxH CCCx"]
    C --> E["T2CCCT2CCL Shadow"]
    F["CCxL CCxH CCCx"] --> C
    G["T2CCCT2CCL Shadow"] --> C
    H["TCX"] --> I["AND"]
    I --> J["CCFx"]
    J --> K["Interrupt"]
    L["CxM2-0"] --> M["×"]
    N["CIENx"] --> O["÷"]
    P["CCx (P2.x)"] --> Q["□"]
    R["T2CCH"] --> S["↔"]
    T["TCX"] --> U["↔"]
    V["TCX"] --> W["↔"]
    X["TCX"] --> Y["↔"]
    Z["TCX"] --> AA["↔"]
    AB["TCX"] --> AC["↔"]
    AD["TCX"] --> AE["↔"]
    AF["TCX"] --> AG["↔"]
    AH["TCX"] --> AI["↔"]
    AJ["TCX"] --> AK["↔"]
    AL["TCX"] --> AM["↔"]
    AN["TCX"] --> AO["↔"]
    AP["TCX"] --> AQ["↔"]
    AR["TCX"] --> AS["↔"]
    AT["TCX"] --> AU["↔"]
    AV["TCX"] --> AW["↔"]
    AX["TCX"] --> AY["↔"]
    AZ["TCX"] --> BA["↔"]
    BB["TCX"] --> BC["↔"]
    BD["TCX"] --> BE["↔"]
    BF["TCX"] --> BG["↔"]
    BH["TCX"] --> BI["↔"]
    BJ["TCX"] --> BK["↔"]
    BL["TCX"] --> BM["↔"]
    BN["TCX"] --> BO["↔"]
    BP["TCX"] --> BQ["↔"]
    BR["TCX"] --> BS["↔"]
    BT["TCX"] --> BU["↔"]
    BV["TCX"] --> BW["↔"]
    BX["TCX"] --> BY["↔"]
    BZ["TCX"] --> CA["↔"]
    CB["TCX"] --> CC["↔"]
    DD["TCX"] --> EE["↔"]
    FF["TCX"] --> DG["↔"]
    DH["TCX"] --> DI["↔"]
    DJ["TCX"] --> DK["↔"]
    DL["TCX"] --> DM["↔"]
    DN["TCX"] --> DE["↔"]
    DF["TCX"] --> DG
    DG --> DG

13.3.1 Waveform Generation

Each CCA channel has an associated external compare output pin: CCA (P2.0), CCB (P2.1), CCC (P2.2) and CCD (P2.3). The CxM_2-0 bits in CCCx determine what action is taken when a compare event occurs. The output pin may be set to 1, cleared to 0 or toggled. Output actions take place even if the interrupt is disabled; however, the associated I/O pin must be set to the desired output mode before the compare event occurs. The state of the compare outputs are initialized to 1 by reset.

Multiple compare events per channel can occur within a single time period, provided that the software has time to update the compare value before the timer reaches the next compare point. In this case other interrupts should be disabled or the CCA interrupt given a higher priority in order to ensure that the interrupt is serviced in time.

A wide range of waveform generation configurations are possible using the various operating modes of Timer 2 and the CCA. Some example configurations are detailed below. Pulse width modulation is a special case of output compare. See “Pulse Width Modulation Mode” on page 68 for more details of PWM operation.

13.3.1.1 Normal Mode

The simplest waveform mode is when CP/RL2 = 0 and T2CM1-0 = 01B. In this mode the frequency of the output is determined by the TOP value stored in RCAP2L and RCAP2H and output edges occur at fractions of the timer period. Figure 13-4 shows an example of outputting two waveforms of the same frequency but different phase by using the toggle on match action. More complex waveforms are achieved by changing the TOP value and the compare values more frequently.

Figure 13-4. Normal Mode Waveform Example

13.3.1.2 Clear-Timer-on-Compare Mode

Clear-Timer-on-Compare (CTC) mode occurs when the CTCx bit of a compare channel is set to one. CTC mode works best when Timer 2 is in capture mode (CP/RL2 = 1) to allow the full range of compare values. In CTC mode, the compare value defines the interval between output events because the timer is cleared after every compare match. Figure 13-5 shows an example waveform using the toggle on match action in CTC mode.

Figure 13-5. CTC Mode Waveform Example

13.3.1.3 Dual-Slope Mode

The dual-slope mode occurs when CP/RL2 = 0 and T2CM _0 = 1xB. In this mode the frequency of the output is determined by the TOP value stored in RCAP2L and RCAP2H and output edges occur at fractions of the timer period on both the up and down count. Figure 13-6 shows an example of outputting two symmetrical waveforms using the toggle on match action. More complex waveforms are achieved by changing the TOP value and the compare values more frequently.

Figure 13-6. Dual-slope Waveform Example

13.3.2 Timer 2 Operation for Compare Mode

Compare channels will work with any Timer 2 operating mode. The full 16-bit compare range may not be available in all modes. In order for a compare output action to take place, the compare values must be within the counting range of Timer 2. CTCx must be cleared to 0 for all channels if Timer 2 is operating in Baud Rate mode or errors may occur in the serial communication.

13.4 Pulse Width Modulation Mode

In Pulse Width Modulation (PWM) mode, a compare channel can output a square wave with programmable frequency and duty cycle. Setting CCMx = 1 and CxM _2-0 = 10xB enables PWM mode. PWM mode is similar to Output Compare mode except that the compare value is double-buffered. A diagram of a CCA channel in PWM mode is shown in Figure 13-7. The PWM polarity is selectable between inverting and non-inverting modes. PWM is intended for use with Timer 2 in Auto-reload mode (CP/RL2 = 0, DCEN = 0) using count modes 1, 2 or 3. The PWM can operate in asymmetric (edge-aligned) or symmetric (center-aligned) mode depending on the T2CM selection. The CCA PWM has variable precision from 2 to 16 bits. A trade-off between frequency

and precision is made by changing the TOP value of the timer. The CCA PWM always uses the greatest precision allowable for the selected output frequency, as compared to Timer 0 and 1 whose PWMs are fixed at 8-bit precision regardless of frequency.

Figure 13-7. CCA PWM Mode Diagram

graph TD
    A["TL2 TH2"] --> B["="]
    B --> C["AND"]
    C --> D["CCx (P2.x)"]
    E["CCxL CCxH CCCx"] --> F["AND"]
    F --> G["CCFx"]
    G --> H["AND"]
    H --> I["Interrupt"]
    J["T2CCCT2CCL"] --> K["AND"]
    K --> L["CCx (P2.x)"]
    M["Shadow"] --> N["CCx (P2.x)"]
    O["Shadow"] --> P["CCx (P2.x)"]
    Q["T2CCH"] --> R["CCx (P2.x)"]
    S["CxM2-0"] --> T["AND"]
    U["CIENx"] --> V["AND"]
    W["T2CCCT2CCL"] --> X["AND"]
    Y["T2CCCT2CCL"] --> Z["AND"]
    style A fill:#f9f,stroke:#333
    style E fill:#f9f,stroke:#333
    style F fill:#f9f,stroke:#333
    style G fill:#f9f,stroke:#333
    style H fill:#f9f,stroke:#333
    style I fill:#f9f,stroke:#333
    style J fill:#f9f,stroke:#333
    style K fill:#f9f,stroke:#333
    style L fill:#f9f,stroke:#333
    style M fill:#f9f,stroke:#333
    style N fill:#f9f,stroke:#333
    style O fill:#f9f,stroke:#333
    style P fill:#f9f,stroke:#333
    style Q fill:#f9f,stroke:#333
    style R fill:#f9f,stroke:#333
    style S fill:#f9f,stroke:#333
    style T fill:#f9f,stroke:#333
    style U fill:#f9f,stroke:#333
    style V fill:#f9f,stroke:#333

13.4.1 Asymmetrical PWM

For Asymmetrical PWM, Timer 2 should be configured for Auto-reload mode and Count Mode 1 (CP/RL2 = 0, DCEN = 0, T2CM1-0 = 01B). Asymmetrical PWM uses single slope operation as shown in Figure 13-8. The timer counts up from BOTTOM to TOP and then restarts from BOTTOM. In non-inverting mode, the output CCx is set on the compare match between Timer 2 (TL2, TH2) and the channel data register (CCxL, CCxH), and cleared at BOTTOM. In inverting mode, the output CCx is cleared on the compare match between Timer 2 and the data register, and set at BOTTOM. The resulting asymmetrical output waveform is left-edge aligned.

The TOP value in RCAP2L and RCAP2H is double buffered such that the output frequency is only updated at the TOP to BOTTOM overflow. The channel data register (CCxL, CCxH) is also double-buffered such that the duty cycle is only updated at the TOP to BOTTOM overflow to prevent glitches. The output frequency and duty cycle for asymmetrical PWM are given by the following equations:

$$ f _ {O U T} = \frac {\text { Oscillator Frequency }}{{\text { RCAP2H } , \text { RCAP2L } } + 1} \times \frac {1}{\text { TPS } - 1 +} $$

$$ \text {Inverting:} \quad \text {Duty Cycle} = 100 \% \times \frac {{\mathrm{CCxH}, \mathrm{CCxL} }}{{\mathrm{RCAP2H}, \mathrm{RCAP2L} } + 1} $$

$$ \text {Non - Inverting:} \quad \text {Duty Cycle} = 100 \% \times \frac {{\text {RCAP2H, RCAP2L} } - {\text {CCxH, CCxL} } + 1}{{\text {RCAP2H, RCAP2L} } + 1} $$

The extreme compare values represent special cases when generating a PWM waveform. If the compare value is set equal to (or greater than) TOP, the output will remain low or high for non-inverting and inverting modes, respectively. If the compare value is set to BOTTOM (0000H), the output will remain high or low for non-inverting and inverting modes, respectively.

Figure 13-8. Asymmetrical (Edge-Aligned) PWM

13.4.2 Symmetrical PWM

For Symmetrical PWM, Timer 2 should be configured for Auto-reload mode and Count Mode 2 or 3 (CP/RL2 = 0, DCEN = 0, T2CM1-0 = 1xB). Symmetrical PWM uses dual-slope operation as shown in Figure 13-9. The timer counts up from MIN to TOP and then counts down from TOP to MIN. The timer is equal to TOP for exactly one clock cycle. In non-inverting mode, the output CCx is cleared on the up-count compare match between Timer 2 (TL2, TH2) and the channel data register (CCxL, CCxH), and set at the down-count compare match. In inverting mode, the output CCx is set on the up-count compare match between Timer 2 and the data register, and cleared at the down-count compare match. The resulting symmetrical PWM output waveform is center-aligned around the timer equal to TOP point. Symmetrical PWM may be used to generate non-overlapping waveforms.

The TOP value in RCAP2L and RCAP2H is double buffered such that the output frequency is only updated at the underflow. The channel data register (CCxL, CCxH) is also double-buffered to prevent glitches. The output frequency and duty cycle for symmetrical PWM are given by the following equations:

$$ \begin{array}{l} f _ {O U T} \quad \frac {\text { Oscillator Frequency }}{2 \text { RCAP2H RCAP2L } {\times \frac {1}{\text { TPS1+ }} \quad }} \ \text { Non - Inverting: Duty Cycle 100\% = } \quad \times \frac {\text { CCxH CCxL } {\quad , \quad }}{\text { RCAP2H RCAP2L } {\quad , \quad }} \ \text { Inverting: Duty Cycle 100\% = } \quad \times \frac {{\text { RCAP2H RCAP2L } } - {\text { CCxH CCxL } }}{\text { RCAP2H RCAP2L } {\quad , \quad }} \end{array} $$

The extreme compare values represent special cases when generating a PWM waveform. If the compare value is set equal to (or greater than) TOP, the output will remain high or low for non-inverting and inverting modes, respectively. If the compare value is set to MIN (0000H), the output will remain low or high for non-inverting and inverting modes, respectively.

Figure 13-9. Non-overlapping Waveforms Using Symmetrical PWM

13.4.2.1 Phase and Frequency Correct PWM

When T2CM_1 - 0 = 10B , the Symmetrical PWM operates in phase and frequency correct mode. In this mode the compare value double buffer is only updated when the timer equals MIN (underflow). This guarantees that the resulting waveform is always symmetrical around the TOP value as shown in Figure 13-10 because the up and down count compare values are identical. The TF2 interrupt flag is only set at underflow.

When T2CM_1-0 = 11B , the Symmetrical PWM operates in phase correct mode. In this mode the compare value double buffer is updated when the timer equals MIN (underflow) and TOP (overflow). The resulting waveform may not be completely symmetrical around the TOP value as shown in Figure 13-11 because the up and down count compare values may not be identical. However, this allows the pulses to be weighted toward one edge or another. The TF2 interrupt flag is set at both underflow and overflow.

Figure 13-10. Phase and Frequency Correct Symmetrical (Center-Aligned) PWM

Figure 13-11. Phase Correct Symmetrical (Center-Aligned) PWM

13.4.3 Multi-Phasic PWM

The PWM channels may be configured to provide multi-phasic alternating outputs by the PHS_2-0 bits in T2MOD. The AT89LP428/828 provides 1 out of 2, 1 out of 3, 1 out of 4 and 2 out of 4 phase modes (see Table 13-6). In Multi-phasic mode, the PWM outputs on CCA, CCB, CCC and CCD are connected to a one-hot shift register that selectively enables and disables the outputs (see Figure 13-12). Compare points on disabled channels are blocked from toggling the output as if the compare value was set equal to TOP. The PHSD bit in T2MOD controls the direction of the shift register. Example waveforms are shown in Figure 13-13 on page 73. In order to use multi-phasic PWM, the associated channels must be configured for PWM operation. Non-PWM channels are not affected by multi-phasic operation. However, their locations in the shift register are maintained such that some periods in the PWM outputs may not have any pulses as shown in Figure 13-14.

The PHS_2 - 0 bits may only be modified when the timer is not operational (TR2 = 0). Updates to PHSD are allowed at any time. Note that channels C and D in 1:2 phase mode and channel D in 1:3 phase mode operate normally.

Table 13-6. Summary of Multi-Phasic Modes

PHS _2-0	Mode	Behavior
		PHSD = 0 PHSD = 1
000	Off	Normal Operation (all channels active at all times)
001 1:2		A B A B	B A B A
010 1:3		A B C A B C	C B A C B A
011 1:4		A B C D A B C D -	D C B A D C B A -
100 2:4		A B A B	B A B A
		C D C D	D C D C

Figure 13-12. Multi-Phasic PWM Output Stage

graph TD
    subgraph PHS = 001B
        A["PHSD"] --> B["1"]
        B --> C["EN"]
        C --> D["□ CCA"]
        E["PHSD"] --> F["0"]
        F --> G["EN"]
        G --> H["□ CCB"]
        I["PHSD"] --> J["1"]
        J --> K["EN"]
        K --> L["□ CCC"]
        M["PHSD"] --> N["1"]
        N --> O["EN"]
        O --> P["□ CCD"]
    end

    subgraph PHS = 010B
        Q["PHSD"] --> R["1"]
        R --> S["EN"]
        S --> T["□ CCA"]
        U["PHSD"] --> V["0"]
        V --> W["EN"]
        W --> X["□ CCB"]
        Y["PHSD"] --> Z["1"]
        Z --> AA["EN"]
        AA --> AB["□ CCC"]
        AC["PHSD"] --> AD["1"]
        AD --> AE["EN"]
        AE --> AF["□ CCD"]
    end

    subgraph PHS = 011B
        AG["PHSD"] --> AH["1"]
        AH --> AI["EN"]
        AI --> AJ["□ CCA"]
        AK["PHSD"] --> AL["0"]
        AL --> AM["EN"]
        AM --> AN["□ CCB"]
        AO["PHSD"] --> AP["0"]
        AP --> AQ["EN"]
        AQ --> AR["□ CCC"]
        AS["PHSD"] --> AT["0"]
        AT --> AU["EN"]
        AU --> AV["□ CCD"]
    end

    subgraph PHS = 100B
        AW["PHSD"] --> AX["1"]
        AX --> AY["EN"]
        AY --> AZ["□ CCA"]
        BA["PHSD"] --> BB["0"]
        BB --> BC["EN"]
        BC --> BD["□ CCB"]
        BE["PHSD"] --> BF["1"]
        BF --> BG["EN"]
        BG --> BH["□ CCC"]
        BI["PHSD"] --> BJ["0"]
        BJ --> BK["EN"]
        BK --> BL["□ CCD"]
    end

Figure 13-13. Multi-Phasic PWM Modes

Figure 13-14. Three-Phase Mode with Channel B Disabled

PHS = 010B, CCB Disabled CCA CCB CCC PHSD

14. External Interrupts

The INT0 (P3.2) and INT1 (P3.3) pins of the AT89LP428/828 may be used as external interrupt sources. The external interrupts can be programmed to be level-activated or transition-activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at the INTx pin. If ITx = 1, external interrupt x is edge-triggered. In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt request flag IEx in TCON is set. Flag bit IEx then requests the interrupt. Since the external interrupt pins are sampled once each clock cycle, an input high or low should hold for at least 2 oscillator periods to ensure sampling. If the external interrupt is transition-activated, the external source has to hold the request pin high for at least two clock cycles, and then hold it low for at least two clock cycles to ensure that the transition is seen so that interrupt request flag IEx will be set. IEx will be automatically cleared by the CPU when the service routine is called if generated in edge-triggered mode. If the external interrupt is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. Then the external source must deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. Both INT0 and INT1 may wake up the device from the Power-down state.

15. General-purpose Interrupts

The GPI function provides 8 configurable external interrupts on Port 1. Each port pin can detect high/low levels or positive/negative edges. The GPIEN register select which bits of Port 1 are enabled to generate an interrupt. The GPMOD and GPLS registers determine the mode for each individual pin. GPMOD selects between level-sensitive and edge-triggered mode. GPLS selects between high/low in level mode and positive/negative in edge mode. A block diagram is shown in Figure 15-1. The pins of Port 1 are sampled every clock cycle. In level-sensitive mode, a valid level must appear in two successive samples before generating the interrupt. In edge-triggered mode, a transition will be detected if the value changes from one sample to the next. When an interrupt condition on a pin is detected, and that pin is enabled, the appropriate flag in the GPIF register is set. The flags in GPIF must be cleared by software. Any GPI interrupt may wake up the device from the Power-down state.

Figure 15-1. GPI Block Diagram

graph TD
    subgraph Inputs
        P1.7[" (P1.7) GPI7 "] --> A1["7"] --> B1["×"] --> C1["1"] --> D1["7"] --> E1["AND"] --> F1["D Q"] --> G1["7"]
        P1.6[" (P1.6) GPI6 "] --> A2["6"] --> B2["×"] --> C2["1"] --> D2["6"] --> E2["AND"] --> F2["D Q"] --> G2["6"]
        P1.5[" (P1.5) GPI5 "] --> A3["5"] --> B3["×"] --> C3["1"] --> D3["5"] --> E3["AND"] --> F3["D Q"] --> G3["5"]
        P1.4[" (P1.4) GPI4 "] --> A4["4"] --> B4["×"] --> C4["1"] --> D4["4"] --> E4["AND"] --> F4["D Q"] --> G4["4"]
        P1.3[" (P1.3) GPI3 "] --> A5["3"] --> B5["×"] --> C5["1"] --> D5["3"] --> E5["AND"] --> F5["D Q"] --> G5["3"]
        P1.2[" (P1.2) GPI2 "] --> A6["2"] --> B6["×"] --> C6["1"] --> D6["2"] --> E6["AND"] --> F6["D Q"] --> G6["2"]
        P1.1[" (P1.1) GPI1 "] --> A7["1"] --> B7["×"] --> C7["1"] --> D7["1"] --> E7["AND"] --> F7["D Q"] --> G7["1"]
        P1.0[" (P1.0) GPI0 "] --> A8["0"] --> B8["×"] --> C8["1"] --> D8["0"] --> E8["AND"] --> F8["D Q"] --> G8["0"]
    end
    CLK --> AND1
    CLK --> AND2
    CLK --> AND3
    CLK --> AND4
    AND1 --> OR1
    AND2 --> OR2
    AND3 --> OR3
    AND4 --> OR4
    OR1 --> OR5
    OR2 --> OR6
    OR3 --> OR7
    OR4 --> OR8
    OR5 --> OR9
    OR6 --> OR10
    OR7 --> OR11
    OR8 --> OR12
    OR9 --> OR13
    OR10 --> OR14
    OR11 --> OR15
    OR12 --> OR16
    OR13 --> OR17
    OR14 --> OR18
    OR15 --> OR19
    OR16 --> OR20
    OR17 --> OR21
    OR18 --> OR22
    OR19 --> OR23
    OR20 --> OR24
    OR21 --> OR25
    OR22 --> OR26
    OR23 --> OR27
    OR24 --> OR28
    OR25 --> OR29
    OR26 --> OR30
    OR27 --> OR31
    OR28 --> OR32
    OR29 --> OR33
    OR30 & OR31 & OR32 & OR33 & OR34 & OR35 & OR36 & OR37 & OR38 & OR39 & OR40 & OR41 & OR42 & OR43 & OR44 & OR45 & OR46 & OR47 & OR48 & OR49 & OR50 & OR51 & OR52 & OR53 & OR54 & OR55 & OR56 & OR57 & OR58 & OR59 & OR60 & OR61 & OR62 & OR63 & OR64 & OR65 & OR66 & OR67 & OR68 & OR69 & OR70 & OR71 & OR72 & OR73 & OR74 & OR75 & OR76 & OR77 & OR78 & OR79 & OR80 & OR81 & OR82 & OR83 & OR84 & OR85 & OR86 & OR87 & OR88 & OR89 & OR90 & IRnterrupt
    end

Table 15-1. GPMOD – General-purpose Interrupt Mode Register

GPMOD7 GPMOD6 GPMOD5 GPMOD4			GPMOD3 GPMOD2 GPMOD1 GPMOD0
B	i	t	7	6	5	4	3
GPMOD.x 0 = level-sensitive interrupt for P1.x1 = edge-triggered interrupt for P1.x

Table 15-2. GPLS – General-purpose Interrupt Level Select Register

GPLS7	GPLS6	GPLS5	GPLS4	GPLS3	GPLS2	GPLS1	GPLS0
B	i	t	7	6	5	4	3

Table 15-3. GPIEN – General-purpose Interrupt Enable Register

GPIEN = 9CH Reset Value = 0000 0000BNot Bit Addressable
B	GPIEN7 GPIEN6 GPIEN5	GPIEN4 GPIEN3 GPIEN2 GPIEN1 GPIEN0
	i	t	7	6	5	4	3
GPIEN.x 0 = interrupt for P1.x disabled1 = interrupt for P1.x enabled

Table 15-4. GPIF – General-purpose Interrupt Flag Register

GPIF = 9DH Reset Value = 0000 0000BNot Bit Addressable
	GPIF7 GPI	IF6 GPIF5 GPI	IF4 GPIF3 GPI	F2 GPIF1 GPI	F0
B	i	t	7	6	5	4	3	2
GPIF.x 0 = interrupt on P1.x inactive1 = interrupt on P1.x active. Must be cleared by software.

16. Serial Interface (UART)

The serial interface on the AT89LP428/828 implements a Universal Asynchronous Receiver/Transmitter (UART). The UART has the following features:

• Full-duplex Operation
- 8 or 9 Data Bits
- Framing Error Detection
- Multiprocessor Communication Mode with Automatic Address Recognition
- Baud Rate Generator Using Timer 1 or Timer 2
- Interrupt on Receive Buffer Full or Transmission Complete

The serial interface is full-duplex, which means it can transmit and receive simultaneously. It is also receive-buffered, which means it can begin receiving a second byte before a previously received byte has been read from the receive register. (However, if the first byte still has not been read when reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and transmit registers are both accessed at the Special Function Register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The serial port can operate in the following four modes.

• Mode 0: Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted/received, with the LSB first. The baud rate is programmable to 1/2 or 1/4 the oscillator frequency, or variable based on Time 1.
• Mode 1: 10 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in the Special Function Register SCON. The baud rate is variable based on Timer 1 or Timer 2.
• Mode 2: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8 in SCON) can be assigned the value of "0" or "1". For example, the parity bit (P, in the PSW) can be moved into TB8. On receive, the 9th data bit goes into RB8 in the Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/16 or 1/32 the oscillator frequency.
• Mode 3: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except the baud rate, which is variable based on Timer 1 or Timer 3 in Mode 3.

In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1.

16.1 Multiprocessor Communications

Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received, followed by a stop bit. The 9th bit goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt is activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON.

The following example shows how to use the serial interrupt for multiprocessor communications. When the master processor must transmit a block of data to one of several slaves, it first sends out an address byte that identifies the target slave. An address byte differs from a data byte in that the 9th bit is "1" in an address byte and "0" in a data byte. With SM2 = 1, no slave is

interrupted by a data byte. An address byte, however, interrupts all slaves. Each slave can examine the received byte and see if it is being addressed. The addressed slave clears its SM2 bit and prepares to receive the data bytes that follows. The slaves that are not addressed set their SM2 bits and ignore the data bytes.

The SM2 bit can be used to check the validity of the stop bit in Mode 1. In a Mode 1 reception, if SM2 = 1, the receive interrupt is not activated unless a valid stop bit is received.

Table 16-1. SCON – Serial Port Control Register

SCON Address = 98H Reset Value = 0000 0000B
Bit Addressable
	SM0/FE	SM1	SM2	REN	TB8	RB8	T1	RI
B	i	t	7		6	5	4	3
(SMOD0 = 0/1)^(1)

SM0/FE	SM1	SM2	REN	TB8	RB8	T1	RI
i	t	7		6	5	4	3

Symbol	Function
FE	Framing error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames and must be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. FE will be set regardless of the state of SMOD0.
SM0	Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
SM1	Serial Port Mode Bit 1
	SM0	SM1	Mode	Description	Baud Rate(2)
	0	0	0	shift register	fosc/2 or fosc/4 or Timer 1
	0	1	1	8-bit UART	variable (Timer 1 or Timer 2)
	1	0	2	9-bit UART	fosc/32 or fosc/16
	1	1	3	9-bit UART	variable (Timer 1 or Timer 2)
SM2	Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then RI will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then RI will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 determines the idle state of the shift clock such that the clock is the inverse of SM2, i.e. when SM2 = 0 the clock idles high and when SM2 = 1 the clock idles low.
REN	Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
TB8	The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. In Mode 0, setting TB8 enables Timer 1 as the shift clock generator.
RB8	In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used.
TI	Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software.
RI	Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software.

Notes: 1. SMOD0 is located at PCON.6.
2. f_osc = oscillator frequency. The baud rate depends on SMOD1 (PCON.7).

16.2 Baud Rates

The baud rate in Mode 0 depends on the value of the SMOD1 bit in Special Function Register PCON.7. If SMOD1 = 0 (the value on reset) and TB8 = 0, the baud rate is 1/4 of the oscillator frequency. If SMOD1 = 1 and TB8 = 0, the baud rate is 1/2 of the oscillator frequency, as shown in the following equation:

$$ \begin{array}{l} \text { Mode 0 Baud Rate } \ \mathrm{TB8=0} \end{array} = \frac {2 ^ {\mathrm{SMOD1}}}{4} \times \text { Oscillator Frequency } $$

The baud rate in Mode 2 also depends on the value of the SMOD1 bit. If SMOD1 = 0, the baud rate is 1/32 of the oscillator frequency. If SMOD1 = 1, the baud rate is 1/16 of the oscillator frequency, as shown in the following equation:

$$ \text { Mode 2 Baud Rate } = \frac {2 ^ {\text { SMOD1 }}}{3 2} \times \text { Oscillator Frequency } $$

16.2.1 Using Timer 1 to Generate Baud Rates

Setting TB8 = 1 in Mode 0 enables Timer 1 as the baud rate generator. When Timer 1 is the baud rate generator for Mode 0, the baud rates are determined by the Timer 1 overflow rate and the value of SMOD1 according to the following equation:

$$ \begin{array}{l} \text { Mode 0 Baud Rate } \ \mathrm{TB8=1} \end{array} = \frac {2 ^ {\mathrm{SMOD1}}}{4} \times (\text { Timer 1 Overflow Rate }) $$

The Timer 1 overflow rate normally determines the baud rates in Modes 1 and 3. When Timer 1 is the baud rate generator, the baud rates are determined by the Timer 1 overflow rate and the value of SMOD1 according to the following equation:

$$ \begin{array}{l} \text { Modes 1,3 } \ \text { Baud Rate } \end{array} = \frac {2 ^ {\text { SMOD1 }}}{3 2} \times (\text { Timer 1 Overflow Rate }) $$

The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either timer or counter operation in any of its 3 running modes. In the most typical applications, it is configured for timer operation in auto-reload mode (high nibble of TMOD = 0010B). In this case, the baud rate is given by the following formula:

$$ \begin{array}{l} \text {Modes 1,3} \ \text {Baud Rate} \end{array} \quad \frac {2 ^ {\mathrm{SMOD1}}}{3 2} \times = \frac {\text {Oscillator Frequency}}{2 5 6 \mathrm{TH1(})} \times \frac {1}{\text {TPS1+}} ] $$

Programmers can achieve very low baud rates with Timer 1 by configuring the Timer to run as a 16-bit auto-reload timer (high nibble of TMOD = 0001B). In this case, the baud rate is given by the following formula.

$$ \frac {\text { Modes } 1 , 3}{\text { Baud Rate }} = \frac {2 ^ {\text { SMOD1 }}}{3 2} \times \frac {\text { Oscillator Frequency }}{[ 6 5 5 3 6 - (R H 1 , R L 1) ]} \times \frac {1}{T P S + 1} $$

Table 16-2 lists commonly used baud rates and how they can be obtained from Timer 1.

Table 16-2. Commonly Used Baud Rates Generated by Timer 1 (TPS = 0000B)

Baud Rate f	_osc (MHz) SMOD1		Timer 1
			C/T Mode	Reload Value
Mode 0: 1 MHz 4 0	X X X
Mode 2: 750K 12 1	X X X
62.5K	12 1 0 2	F4H
38.4K	11.059	0 0 2	F7H
19.2K	11.059	1 0 2	DCH
9.6K 11.059	0 0 2	DCH
4.8K 11.059	0 0 2	B8H
2.4K 11.059	0 0 2	70H
1.2K 11.059	0 0 1 FEE0H
137.5	11.986	0 0 1 F55CH
110	6 0 0 1 F958H
110	12 0 0 1 F304H

16.2.2 Using Timer 2 to Generate Baud Rates

Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON. Under these conditions, the baud rates for transmit and receive can be simultaneously different by using Timer 1 for transmit and Timer 2 for receive, or vice versa. The baud rate generator mode is similar to the auto-reload mode, in that a rollover causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. In this case, the baud rates in Modes 1 and 3 are determined by Timer 2's overflow rate according to the following equation:.

$$ \begin{array}{c} \text {Modes 1 and 3} \ \text {Baud Rate} \end{array} = \frac {1}{1 6} \times \frac {\text {Oscillator Frequency}}{\left[ 6 5 5 3 6 - (\text {RCAP2H,RCAP2L}) \right]} \times \frac {1}{\text {TPS} + 1} $$

Table 16-3 lists commonly used baud rates and how they can be obtained from Timer 2.

Table 16-3. Commonly Used Baud Rates Generated by Timer 2 (TPS = 0000B)

Baud Rate f	_osc (MHz)	Timer 2
		CP/ 2 C	T2 TCLK or	RCLK Reload Value
62.5K 12 0 0 1	FFF4H
19.2K 11.059	0 0 1	FFDCH
9.6K	11.059	0 0 1		FFB8H
4.8K	11.059	0 0 1 FF70H
2.4K	11.059	0 0 1		FEE0H
1.2K	11.059	0 0 1		FDC0H
137.5	11.986	0 0 1		EAB8H
110	6	0 0 1		F2AFH
110	12 0 0 1		E55EH

16.3 More About Mode 0

In Mode 0, the UART is configured as a 2-wire half-duplex synchronous serial interface. Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted/received, with the LSB first. Figure 16-1 on page 83 shows a simplified functional diagram of the serial port in Mode 0 and associated timing. The baud rate is programmable to 1/2 or 1/4 the oscillator frequency by setting/clearing the SMOD1 bit. However, changing SMOD1 has an effect on the relationship between the clock and data as described below. The baud rate can also be generated by Timer 1 by setting TB8. Table 16-4 lists the baud rate options for Mode 0.

Table 16-4. Mode 0 Baud Rates

TB8	SMOD1	Baud Rate
0	0	f_SYS/4
0	1	f_SYS/2
1	0	(Timer 1 Overflow)/4
1	1	(Timer 1 Overflow)/2

Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF” signal also loads a “1” into the 9th position of the transmit shift register and tells the TX Control Block to begin a transmission. The internal timing is such that one full bit slot may elapse between “write to SBUF” and activation of SEND.

SEND transfers the output of the shift register to the alternate output function line of P3.0, and also transfers Shift Clock to the alternate output function line of P3.1. As data bits shift out to the right, "0"s come in from the left. When the MSB of the data byte is at the output position of the shift register, the "1" that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain "0"s. This condition flags the TX Control block to do one last shift, then deactivate SEND and set TI.

Reception is initiated by the condition REN = 1 and R1 = 0. At the next clock cycle, the RX Control unit writes the bits 11111110 to the receive shift register and activates RECEIVE in the next clock phase. RECEIVE enables Shift Clock to alternate output function line of P3.1. As data bits come in from the right, "1"s shift out to the left. When the "0" that was initially loaded into the right-most position arrives at the left-most position in the shift register, it flags the RX Control block to do one last shift and load SBUF. Then RECEIVE is cleared and RI is set.

The relationship between the shift clock and data is determined by the combination of the SM2 and SMOD1 bits as listed in Table 16-5 and shown in Figure 16-2. The SM2 bit determines the idle state of the clock when not currently transmitting/receiving. The SMOD1 bit determines if the output data is stable for both edges of the clock, or just one.

Table 16-5. Mode 0 Clock and Data Modes

SM2 SMOD1 Clock Idle Data Changed Data Sampled
0	0	High	While clock is high	Positive edge of clock
0	1	High	Negative edge of clock	Positive edge of clock
1	0	Low	While clock is low	Negative edge of clock
1	1	Low	Negative edge of clock	Positive edge of clock

Figure 16-1. Serial Port Mode 0

graph TD
    subgraph Top_Layer
        direction_TB8["TB8 ---"]
        Top1["Timer 1 OVERFLOW fosc"] --> Top2["÷2"]
        Top3["SMOD1 ---"] --> Top4["÷2"]
        Top5["WRITE TO SBUF"] --> Top6["SBUF"]
        Top7["WRITE TO SBUF"] --> Top8["SBUF"]
        Top9["INTERNAL BUS"] --> Top10[""1"]
        Top10 --> SBUF["D S Q CL"]
        SBUF --> SBUFb["ZERO DETECT OR"]
        SBUFb --> SBUFb
        SBUFb --> SBUFb
        SBUFb --> SBUFb
        SBUFb --> SBUFb
        SBUFb --> SBUFb
        SBUFb --> SBUFb
        SBUFb --> SBUFb
    end

    subgraph Bottom_Layer
        direction_LR1["REN RI"] --> Bottom2["RRX CLOCK"]
        Bottom2 --> Bottom3["RI", "RECEIVE", "LOAD SBUF"]
        Bottom3 --> Bottom4["INPUT SHIFT REG."]
        Bottom4 --> Bottom5["SBUF"]
        Bottom5 --> Bottom6["READ SBUF"]
        Bottom6 --> Bottom7["INTERNAL BUS"]
        Bottom7 --> Bottom8["INTERNAL BUS"]
        Bottom8 --> Bottom9["RXD P3.0 ALT OUTPUT FUNCTION"]
        Bottom9 --> Bottom10["SM2"]
        Bottom10 --> Bottom11["INTP INPUT FUNCTION"]
        Bottom11 --> Bottom12["RXD P3.1 ALT OUTPUT FUNCTION"]
    end

    style Top_Layer fill:#f9f,stroke:#333
    style Bottom_Layer fill:#ccf,stroke:#333
    style Bottom_1 fill:#fff,stroke:#333
    style Bottom_2 fill:#fff,stroke:#333
    style Bottom_3 fill:#fff,stroke:#333
    style Bottom_4 fill:#fff,stroke:#333
    style Bottom_5 fill:#fff,stroke:#333
    style Bottom_6 fill:#fff,stroke:#333
    style Bottom_7 fill:#fff,stroke:#333
    style Bottom_8 fill:#fff,stroke:#333
    style Bottom_9 fill:#fff,stroke:#333
    style Bottom_10 fill:#fff,stroke:#333
    style Bottom_11 fill:#fff,stroke:#333
    style Bottom_12 fill:#fff,stroke:#333
    style Bottom_13 fill:#fff,stroke:#333
    style Bottom_14 fill:#fff,stroke:#333
    style Bottom_15 fill:#fff,stroke:#333
    style Bottom_16 fill:#fff,stroke:#333
    style Bottom_17 fill:#fff,stroke:#333
    style Bottom_18 fill:#fff,stroke:#333
    style Bottom_19 fill:#fff,stroke:#333
    style Bottom_20 fill:#fff,stroke:#333
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    style Bottom_22 fill:#fff,stroke:#333
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    style Bottom_24 fill:#fff,stroke:#333
    style Bottom_25 fill:#fff,stroke:#333
    style Bottom_26 fill:#fff,stroke:#333
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    style Bottom_30 fill:#fff,stroke:#333
    style Bottom_31 fill:#fff,stroke:#333
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    style Bottom_33 fill:#fff,stroke:#333
    style Bottom_34 fill:#fff,stroke:#333
    style Bottom_35 fill:#fff,stroke:#333
    style Bottom_36 fill:#fff,stroke:#333
    style Bottom_37 fill:#fff,stroke:#333
    style Bottom_38 fill:#fff,stroke:#333
    style Bottom_39 fill:#fff,stroke:#333
    style Bottom_40 fill:#fff,stroke:#333
    style Bottom_41 fill:#fff,stroke:#333
    style Bottom_42 fill:#fff,stroke:#333
    style Bottom_43 fill:#fff,stroke:#333
    style Bottom_44 fill:#fff,stroke:#333
    style Bottom_45 fill:#fff,stroke:#333
    style Bottom_46 fill:#fff,stroke:#333
    style Bottom_47 fill:#fff,stroke:#333
    style Bottom_48 fill:#fff,stroke:#333
    style Bottom_49 fill:#fff,stroke:#333
    style Bottom_50 fill:#fff,stroke:#333
    style Bottom_51 fill:#fff,stroke:#333
    style Bottom_52 fill:#fff,stroke:#333
    style Bottom_53 fill:#fff,stroke:#333
    style Bottom_54 fill:#fff,stroke:#333
    style Bottom_55 fill:#fff,stroke:#333
    style Bottom_56 fill:#fff,stroke:#333
    style Bottom_57 fill:#fff,stroke:#333
    style Bottom_58 fill:#fff,stroke:#�4e6f4
    style Bottom_59 fill:#fff,stroke:#f6e6e6

Figure 16-2. Mode 0 Waveforms

SMOD1 = 0 SM2 = 0 TXD RXD (TX) RXD (RX) 0 1 2 3 4 5 6 7 6543210 7 SMOD1 = 1 SM2 = 0 TXD RXD (TX) RXD (RX) 0 1 2 3 4 5 6 7 6543210 7 SMOD1 = 0 SM2 = 1 TXD RXD (TX) RXD (RX) 0 1 2 3 4 5 6 7 6543210 7 SMOD1 = 1 SM2 = 1 TXD RXD (TX) RXD (RX) 0 1 2 3 4 5 6 7 6543210 7 SMOD1 = 1 SM2 = 1

Mode 0 may be used as a hardware accelerator for software emulation of serial interfaces such as a half-duplex Serial Peripheral Interface (SPI) in mode (0,0) or (1,1) or a Two-wire Interface (TWI) in master mode. An example of Mode 0 emulating a TWI master device is shown in Figure 16-3. In this example, the start, stop, and acknowledge are handled in software while the byte transmission is done in hardware. Falling/rising edges on TXD are created by setting/clearing SM2. Rising/falling edges on RXD are forced by setting/clearing the P3.0 register bit. SM2 and P3.0 must be 1 while the byte is being transferred.

Figure 16-3. UART Mode 0 TWI Emulation (SMOD1 = 1)

(SCL) TXD (SDA) RXD 65432/0 ACK SM2 P3.0 Sample ACK Write to SBUF TI

Mode 0 transfers data LSB first whereas SPI or TWI are generally MSB first. Emulation of these interfaces may require bit reversal of the transferred data bytes. The following code example reverses the bits in the accumulator:

EX: MOV R7, #8
REVRS: RLC A ; C << msb(ACC)
XCH A, R6
RRC A ; msb(ACC) >> B
XCH A, R6
DJNZ R7, REVRS 

16.4 More About Mode 1

Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the AT89LP428/828, the baud rate is determined either by the Timer 1 overflow rate, the Tlmer 2 overflow rate, or both. In this case one timer is for transmit and the other is for receive. Figure 16-4 shows a simplified functional diagram of the serial port in Mode 1 and associated timings for transmit and receive.

Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF” signal also loads a “1” into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. Thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SBUF” signal.

The transmission begins when SEND is activated, which puts the start bit at TXD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit time after that.

As data bits shift out to the right, "0"s are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, the "1" that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain "0"s. This condition flags the TX Control unit to do one last shift, then deactivate SEND and set TI. This occurs at the tenth divide-by-16 rollover after "write to SBUF."

Reception is initiated by a 1-to-0 transition detected at RXD. For this purpose, RXD is sampled at a rate of 16 times the established baud rate. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its roll-overs with the boundaries of the incoming bit times.

The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RXD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done to reject noise. In order to reject false bits, if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit continues looking for another 1-to-0 transition. If the start bit is valid, it is shifted into the input shift register, and reception of the rest of the frame proceeds.

As data bits come in from the right, "1"s shift out to the left. When the start bit arrives at the left-most position in the shift register, (which is a 9-bit register in Mode 1), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8 and to set RI is generated if, and only if, the following conditions are met at the time the final shift pulse is generated.

• R I = 0 and
- Either SM2 = 0, or the received stop bit = 1

If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whether or not the above conditions are met, the unit continues looking for a 1-to-0 transition in RXD.

Figure 16-4. Serial Port Mode 1

graph TD
    A["TIMER 1 OVERFLOW"] --> B["÷2"]
    B --> C["0"]
    C --> D["1"]
    D --> E["0"]
    E --> F["TCLK"]
    F --> G["0"]
    G --> H["1"]
    H --> I["RCLK"]
    I --> J["0"]
    J --> K["1"]
    K --> L["÷16"]
    L --> M["START RX CLOCK TI"]
    M --> N["SERIAL PORT INTERRUPT"]
    N --> O["÷16"]
    O --> P["1-TO-0 TRANSITION DETECTOR"]
    P --> Q["RXD"]
    Q --> R["INPUT SHIFT REG. (9 BITS)"]
    R --> S["SBUF"]
    S --> T["INTERNAL BUS"]
    U["TIMER 2 OVERFLOW"] --> V["WRITE TO SBUF"]
    V --> W["SMOD1"]
    W --> X["0"]
    X --> Y["1"]
    Y --> Z["TCLK"]
    Z --> AA["0"]
    AA --> AB["1"]
    AB --> AC["RCLK"]
    AC --> AD["÷16 RESET"]
    AD --> AE["INTERNAL BUS"]
    AF["INTERNAL BUS"] --> AG["1"]
    AG --> AH["SBUF"]
    AH --> AI["ZERO DETECTOR"]
    AI --> AJ["DATA SEND"]
    AJ --> AK["TXD DATA"]
    AL["TX Clock"] --> AM["WRITE TO SBUF"]
    AM --> AN["SEND"]
    AO["DATA SHIFT"] --> AP["TXD START BIT"]
    AP --> AQ["STOP BIT"]
    AR["INTERNAL BUS"] --> AS["SBUF"]
    AS --> AT["INTERNAL BUS"]

16.5 More About Modes 2 and 3

Eleven bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of "0" or "1". On receive, the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/16 or 1/32 of the oscillator frequency in Mode 2. Mode 3 may have a variable baud rate generated from either Timer 1 or Timer 2, depending on the state of RCLK and TCLK.

Figures 16-5 and 16-6 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register.

Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF” signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. Thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SBUF” signal.

The transmission begins when SEND is activated, which puts the start bit at TXD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit time after that. The first shift clocks a "1" (the stop bit) into the 9th bit position of the shift register. Thereafter, only "0"s are clocked in. Thus, as data bits shift out to the right, "0"s are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contain "0"s. This condition flags the TX Control unit to do one last shift, then deactivate SEND and set TI. This occurs at the 11th divide-by-16 rollover after "write to SBUF."

Reception is initiated by a 1-to-0 transition detected at RXD. For this purpose, RXD is sampled at a rate of 16 times the established baud rate. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift register.

At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RXD. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit continues looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame proceeds.

As data bits come in from the right, "1"s shift out to the left. When the start bit arrives at the left-most position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8 and to set RI is generated if, and only if, the following conditions are met at the time the final shift pulse is generated:

• RI = 0, and
- Either SM2 = 0 or the received 9th data bit = 1

If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit continues looking for a 1-to-0 transition at the RXD input.

Note that the value of the received stop bit is irrelevant to SBUF, RB8, or RI.

Figure 16-5. Serial Port Mode 2

graph TD
    subgraph Inputs
        direction TB
        A["CPU CLOCK"] --> B["SMOD1 1"]
        B --> C["÷2"]
        C --> D["SMOD1 0"]
        D --> E["(SMOD IS PCON. 7)"]
        F["WRITE TO SBUF"] --> G["SBUF"]
        H["RESET"] --> I["D^S Q CL"]
        J["RESET"] --> K["ZERO DETECTOR"]
        L["RESET"] --> M["START STOP BIT GEN. TX CONTROL TI"]
        N["RESET"] --> O["SEND DATA"]
        P["RESET"] --> Q["+16"]
        R["RESET"] --> S["+16"]
        T["RESET"] --> U["SERIAL PORT INTERRUPT"]
        V["RESET"] --> W["1-TO-0 TRANSITION DETECTOR"]
        X["RESET"] --> Y["START RX CLOCK RX CONTROL"]
        Z["RESET"] --> AA["BIT DETECTOR"]
        AB["RESET"] --> AC["INPUT SHIFT REG. (9 BITS)"]
        AD["RESET"] --> AE["LOAD SBUF SHIFT 1FFH"]
        AF["RESET"] --> AG["SBUF"]
        AH["RESET"] --> AI["SBUF"]
        AJ["RESET"] --> AK["INTERNAL BUS"]
    end

    subgraph Outputs
        L --> AL["DATA SHIFT"]
        AM["DATA SHIFT"] --> AN["TXD TI START BIT"]
        AO["DATA SHIFT"] --> AP["TB8 STOP BIT"]
        AQ["DATA SHIFT"] --> AR["TB8 STOP BIT"]
        AS["DATA SHIFT"] --> AT["TB8 STOP BIT"]
        AU["DATA SHIFT"] --> AV["TB8 STOP BIT"]
        AW["DATA SHIFT"] --> AX["TB8 STOP BIT"]
        AY["DATA SHIFT"] --> AZ["TB8 STOP BIT"]
        BA["DATA SHIFT"] --> BB["TB8 STOP BIT"]
        BC["DATA SHIFT"] --> BD["TB8 STOP BIT"]
        BE["DATA SHIFT"] --> BF["TB8 STOP BIT"]
        BG["DATA SHIFT"] --> BH["TB8 STOP BIT"]
        BI["DATA SHIFT"] --> BJ["TB8 STOP BIT"]
        BK["DATA SHIFT"] --> BL["TB8 STOP BIT"]
        BM["DATA SHIFT"] --> BN["TB8 STOP BIT"]
        BO["DATA SHIFT"] --> BP["TB8 STOP BIT"]
        BQ["DATA SHIFT"] --> BR["TB8 STOP BIT"]
        BS["DATA SHIFT"] --> BT["TB8 STOP BIT"]
        BU["DATA SHIFT"] --> BV["TB8 STOP BIT"]
        BW["DATA SHIFT"] --> BX["TB8 STOP BIT"]
        BY["DATA SHIFT"] --> BZ["TB8 STOP BIT"]
        CA["DATA SHIFT"] --> CB["TB8 STOP BIT"]
        CC["DATA SHIFT"] --> CD["TB8 STOP BIT"]
        DE["DATA SHIFT"] --> DF["TB8 STOP BIT"]
        DG["DATA SHIFT"] --> DH["TB8 STOP BIT"]
        DI["DATA SHIFT"] --> DJ["TB8 STOP BIT"]
        DK["DATA SHIFT"] --> DL["TB8 STOP BIT"]
        DM["DATA SHIFT"] --> DN["TB8 STOP BIT"]
        DO["DATA SHIFT"] --> DOA["TB8 STOP BIT"]
        DOA --> DOB["TB8 STOP BIT"]
        DOB --> DOC["TB8 STOP BIT"]
        DOC --> DOE["TB8 STOP BIT"]
        DOE --> DOF["TB8 STOP BIT"]
    end

    style Inputs fill:#f9f,stroke:#333
    style Outputs fill:#ccf,stroke:#333

Figure 16-6. Serial Port Mode 3

graph TD
    A["TIMER 1 OVERFLOW"] --> B["÷2"]
    B --> C["0"]
    C --> D["1"]
    D --> E["TCLK"]
    E --> F["0"]
    F --> G["1"]
    G --> H["RCLK"]
    H --> I["÷16"]
    I --> J["START STOP BIT TX CONTROL RX CLOCK TI SEND"]
    J --> K["SBUF"]
    K --> L["INTERNAL BUS"]
    M["TIME 2 OVERFLOW"] --> N["WRITE TO SBUF"]
    N --> O["SBUF"]
    O --> P["TLB8"]
    P --> Q["INTERNA BUS"]
    Q --> R["TXD"]
    S["SAMPLE"] --> T["1-TO-0 TRANSITION DETECTOR"]
    T --> U["RXD"]
    V["SAMPLE"] --> W["1-TO-0 TRANSITION DETECTOR"]
    W --> X["RX CLOCK RI START RX CONTROL"]
    X --> Y["LOAD SBUF SHIFT 1FFH"]
    Y --> Z["INPUT SHIFT REG. (9 BITS)"]
    Z --> AA["SBUF"]
    AA --> AB["INTERNAL BUS"]
    AC["DATA"] --> AD["TXD TI START BIT D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP BIT"]
    AD --> AE["STOP BIT GEN"]
    AF["READ SBUF"] --> AG["SBUF"]
    AG --> AH["INTERNAL BUS"]
    AI["TRANSMIT"] --> AJ["TX CLOCK WRITE TO SBUF SEND DATA SHIFT TXD TI STOP BIT GEN"]
    AK["RECEIVE"] --> AL["RX CLOCK +÷16 RESET"]
    AL --> AM["RXD START BIT D0 D1 D2 D3 D4 D5 D6 D7 MB8 STOP BIT"]
    AM --> AN["BIT DETECTOR SAMPLE TIMES SHIFT RI"]

16.6 Framing Error Detection

In addition to all of its usual modes, the UART can perform framing error detection by looking for missing stop bits, and automatic address recognition. When used for framing error detect, the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE, SCON.7 can only be cleared by software.

16.7 Automatic Address Recognition

Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON for Modes 1, 2 or 3. In the 9-bit UART modes, Mode 2 and Mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the "Given" address or the "Broadcast" address. The 9-bit mode requires that the 9th information bit be a "1" to indicate that the received information is an address and not data.

In Mode 1 (8-bit) the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8th address bits and the information is either a Given or Broadcast address.

Automatic Address Recognition is not available during Mode 0.

Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave's address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are "don't care". The SADEN mask can be logically ANDed with the SADDR to create the "Given" address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples show the versatility of this scheme:

$$ \begin{array}{l l} \text {Slave 0} & \text {SADDR = 1100 0000} \ & \text {SADEN = 1111 1101} \ & \text {Given = 1100 00X0} \end{array} $$

$$ \begin{array}{l l} \text { Slave 1 } & \text { SADDR } = 1 1 0 0 0 0 0 0 \ & \text { SADEN } = \underline {{1 1 1 1 1 1 1 0}} \ & \text { Given } = 1 1 0 0 0 0 0 X \end{array} $$

In the previous example, SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a "0" in bit 0 and it ignores bit 1. Slave 1 requires a "0" in bit 1 and bit 0 is ignored. A unique address for slave 0 would be 1100 0010 since slave 1 requires a "0" in bit 1. A unique address for slave 1 would be 1100 0001 since a "1" in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000.

In a more complex system, the following could be used to select slaves 1 and 2 while excluding slave 0:

Slave 0 SADDR = 1100 0000

$$ \text { SADEN } = 1 1 1 1 1 0 0 1 $$

$$ \text { Given } = 1 1 0 0 0 \times 0 $$

Slave 1 SADDR = 1110 0000

$$ S A D E N = 1 1 1 1 1 0 1 0 $$

$$ \text { Given } = 1 1 1 0 \quad 0 X 0 X $$

Slave 2 SADDR = 1110 0000

$$ \text { SADEN } = 1 1 1 1 1 1 0 0 $$

$$ \text { Given } = 1 1 1 0 0 0 \mathrm{XX} $$

In the above example, the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2, use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2.

The Broadcast Address for each slave is created by taking the logic OR of SADDR and SADEN. Zeros in this result are treated as don't cares. In most cases, interpreting the don't cares as ones, the broadcast address will be FF hexadecimal.

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are loaded with "0"s. This produces a given address of all "don't cares" as well as a Broadcast address of all "don't cares". This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51-type UART drivers which do not make use of this feature.

17. Enhanced Serial Peripheral Interface

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT89LP428/828 and peripheral devices or between multiple AT89LP428/828 devices, including multiple masters and slaves on a single bus. The SPI includes the following features:

• Full-duplex, 3-wire or 4-wire Synchronous Data Transfer
• Master or Slave Operation
• Maximum Bit Frequency = f_OSC/4
• LSB First or MSB First Data Transfer
- Four Programmable Bit Rates or Timer 1-based Baud Generation (Master Mode)
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
- Double-buffered Receive and Transmit
- Transmit Buffer Empty Interrupt Flag
- Mode Fault (Master Collision) Detection and Interrupt
- Wake up from Idle Mode

A block diagram of the SPI is shown in Figure 17-1.

Figure 17-1. SPI Block Diagram

graph TD
    A["Oscillator"] --> B["T1 OVF"]
    B --> C["TSCK"]
    C --> D["Divider ÷4/÷8/÷32/÷64"]
    D --> E["Select"]
    E --> F["SPI Clock (Master)"]
    F --> G["Clock Logic"]
    G --> H["Pin Control Logic"]
    H --> I["S M S"]
    I --> J["MISO P1.6"]
    I --> K["MOSI P1.5"]
    H --> L["SCK 1.7"]
    H --> M["SS P1.4"]
    N["SPI Interrupt Request"] --> O["Internal Data Bus"]
    P["SPI Status Register"] --> Q["SPI Control Register"]
    R["MSB"] --> S["8-bit Shift Register"]
    R --> T["Read Data Buffer"]
    R --> U["Write Data Buffer"]
    V["SPR1"] --> W["SPI Control"]
    X["SPR0"] --> Y["SPI Control"]
    Z["SPI Control"] --> AA["SPI Control Register"]
    AB["TSCK"] --> AC["SPI Control Register"]
    AD["DORD"] --> AE["SPI Control Register"]
    AF["MSTR"] --> AG["SPI Control Register"]
    AH["CPEA"] --> AI["SPI Control Register"]
    AJ["SPR1"] --> AK["SPI Control Register"]
    AL["SPR0"] --> AM["SPI Control Register"]
    AN["MSTR"] --> AO["SPI Control Register"]
    AP["DORD"] --> AQ["SPI Control Register"]
    AR["SPE"] --> AS["SPI Control Register"]
    AT["DORD"] --> AU["SPI Control Register"]
    AV["MSTR"] --> AW["SPI Control Register"]
    AX["CPEA"] --> AY["SPI Control Register"]
    AZ["SPE"] --> BA["SPI Control Register"]
    BB["DORD"] --> BC["SPI Control Register"]
    BD["MSTR"] --> BE["SPI Control Register"]
    BF["CPEA"] --> BG["SPI Control Register"]
    BH["SPE"] --> BI["SPI Control Register"]
    BJ["DORD"] --> BK["SPI Control Register"]
    BL["MSTR"] --> BM["SPI Control Register"]
    BN["CPEA"] --> BO["SPI Control Register"]
    BP["SPE"] --> BQ["SPI Control Register"]
    BR["DORD"] --> BS["SPI Control Register"]
    BT["MSTR"] --> BU["SPI Control Register"]
    BV["DORD"] --> BW["SPI Control Register"]
    BX["SPE"] --> BY["SPI Control Register"]
    BZ["DORD"] --> CA["SPI Control Register"]
    CB["MSTR"] --> CC["SPI Control Register"]
    CD["CPEA"] --> CE["SPI Control Register"]
    CF["SPE"] --> CG["SPI Control Register"]
    CH["DORD"] --> CI["SPI Control Register"]
    CJ["MSTR"] --> CK["SPI Control Register"]
    CL["DORD"] --> CM["SPI Control Register"]
    CN["SPE"] --> CO["SPI Control Register"]
    CP["DORD"] --> CS["SPI Control Register"]
    CT["MSTR"] --> CU["SPI Control Register"]
    CV["DORD"] --> CW["SPI Control Register"]
    CX["SPE"] --> CY["SPI Control Register"]
    CZ["DORD"] --> DA["SPI Control Register"]

The interconnection between master and slave CPUs with SPI is shown in Figure 17-2. The four pins in the interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock (SCK), and Slave Select (SS). The SCK pin is the clock output in master mode, but is the clock input in slave mode. The MSTR bit in SPCR determines the directions of MISO and MOSI. Also notice that MOSI connects to MOSI and MISO to MISO. By default SS/P1.4 is an input to both master and slave devices.

In slave mode, SS must be driven low to select an individual device as a slave. When SS is held low, the SPI is activated, and MISO becomes an output if configured by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the Shift Register. The slave may ignore SS by setting its SSIG bit in SPSR. When SSIG = 1, the slave is always enabled and operates in 3-wire mode. However, the slave output on MISO may still be disabled by setting DISSO = 1.

Figure 17-2. SPI Master-Slave Interconnection

graph TD
    A["Master Slave"] --> B["8-Bit Shift Register"]
    B --> C["MISO MISO"]
    B --> D["MOSI MOSI"]
    B --> E["8-Bit Shift Register"]
    E --> F["DISSO"]
    F --> G["SSIG"]
    G --> H["SCK SCK"]
    H --> I["GPIO"]
    I --> J["SS"]
    J --> K["Vcc"]
    K --> L["SSIG"]
    L --> M["MODF"]
    M --> N["Clock Generator"]
    N --> B

When the SPI is configured as a Master (MSTR in SPCR is set), the operation of the pin depends on the setting of the Slave Select Ignore bit, SSIG. If SSIG = 1, the pin is a general-purpose output pin which does not affect the SPI system. Typically, the pin will be driving the pin of an SPI Slave. If SSIG = 1, must be held high to ensure Master SPI operation. If the pin is driven low by peripheral circuitry when the SPI is configured as a Master with SSIG = 1, the SPI system interprets this as another master selecting the SPI as a slave and starting to send data to it. To avoid bus contention, the SPI system takes the following actions:

1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of the SPI becoming a Slave, the MOSI and SCK pins become inputs.
2. The MODF Flag in SPSR is set, and if the SPI interrupt is enabled, the interrupt routine will be executed.

Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possibility that SS may be driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master mode.

17.1 Master Operation

An SPI master device initiates all data transfers on the SPI bus. The AT89LP428/828 is configured for master operation by setting MSTR = 1 in SPCR. Writing to the SPI data register (SPDR) while in master mode loads the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer is moved to the shift register; the transmit buffer empty flag, TXE, is set; and a transmission begins. The transfer may start after an initial delay, while the clock generator waits for the next full bit slot of the specified baud rate. The master shifts the data out serially on the MOSI line while providing the serial shift clock on SCK. When the transfer finishes, the SPIF flag is set to "1" and an interrupt request is generated, if enabled. The data received from the addressed SPI slave device is also transferred from the shift register to the receive buffer. Therefore, the SPIF bit flags both the transmit-complete and receive-data-ready conditions. The received data is accessed by reading SPDR.

While the TXE flag is set, the transmit buffer is empty. TXE can be cleared by software or by writing to SPDR. Writing to SPDR will clear TXE and load the transmit buffer. The user may load the buffer while the shift register is busy, i.e. before the current transfer completes. When the current transfer completes, the queued byte in the transmit buffer is moved to the shift register and the next transfer commences. TXE will generate an interrupt if the SPI interrupt is enabled and if the ENH bit in SPSR is set. For multi-byte transfers, TXE may be used to remove any dead time between byte transmissions.

The SPI master can operate in two modes: multi-master mode and single-master mode. By default, multi-master mode is active when SSIG = 0. In this mode, the input is used to disable a master device when another master is accessing the bus. When is driven low, the master device becomes a slave by clearing its MSTR bit and a Mode Fault is generated by setting the MODF bit in SPSR. MODF will generate an interrupt if enabled. The MSTR bit must be set in software before the device may become a master again. Single-master mode is enabled by setting SSIG = 1. In this mode is ignored and the master is always active. may be used as a general-purpose I/O in this mode.

17.2 Slave Operation

When the AT89LP428/828 is not configured for master operation, MSTR = 0, it will operate as an SPI slave. In slave mode, bytes are shifted in through MOSI and out through MISO by a master device controlling the serial clock on SCK. When a byte has been transferred, the SPIF flag is set to "1" and an interrupt request is generated, if enabled. The data received from the addressed master device is also transferred from the shift register to the receive buffer. The received data is accessed by reading SPDR. A slave device cannot initiate transfers. Data to be transferred to the master device must be preloaded by writing to SPDR. Writes to SPDR are double-buffered. The transmit buffer is loaded first and if the shift register is empty, the contents of the buffer will be transferred to the shift register.

While the TXE flag is set, the transmit buffer is empty. TXE can be cleared by software or by writing to SPDR. Writing to SPDR will clear TXE and load the transmit buffer. The user may load the buffer while the shift register is busy, i.e. before the current transfer completes. When the current transfer completes, the queued byte in the transmit buffer is moved to the shift register and waits for the master to initiate another transfer. TXE will generate an interrupt if the SPI interrupt is enabled and if the ENH bit in SPSR is set.

The SPI slave can operate in two modes: 4-wire mode and 3-wire mode. By default, 4-wire mode is active when SSIG = 0. In this mode, the input is used to enable/disable the slave device when addressed by a master. When is driven low, the slave device is enabled and will shift out data on MISO in response to the serial clock on SCK. While is high, the SPI slave will remain sleeping with MISO inactive. 3-wire mode is enabled by setting SSIG = 1. In this mode is ignored and the slave is always active. may be used as a general-purpose I/O in this mode.

The Disable Slave Output bit, DISSO in SPSR, may be used to disable the MISO line of a slave device. DISSO can allow several slave devices to share MISO while operating in 3-wire mode. In this case some protocol other than SS may be used to determine which slave is enabled.

17.3 Pin Configuration

When the SPI is enabled (SPE = 1), the data direction of the MOSI, MISO, SCK, and SS pins is automatically overridden according to the MSTR bit as shown in Table 17-1. The user doesn't need to reconfigure the pins when switching from master to slave or vice-versa. For more details on port configuration, refer to "Port Configuration" on page 35.

Table 17-1. SPI Pin Configuration and Behavior when SPE = 1

Pin Mode	Master (MSTR = 1) Slave (MSTR = 0)
SCK	Quasi-bidirectional	Output	Input (Internal Pull-up)
	Push-pull Output	Output	Input (Tristate)
	Input-only	No output (Tristated)	Input (Tristate)
	Open-drain Output	Output	Input (External Pull-up)
MOSI	Quasi-bidirectional	Output^(1)	Input (Internal Pull-up)
	Push-pull Output	Output^(2)	Input (Tristate)
	Input-only	No output (Tristated)	Input (Tristate)
	Open-drain Output	Output^(1)	Input (External Pull-up)
MISO	Quasi-bidirectional	Input (Internal Pull-up)	Output ( = 0)Internal Pull-up ( = 1 or DISSO = 1)
	Push-pull Output	Input (Tristate)	Output ( = 0)Tristated ( = 1 or DISSO = 1)
	Input-only	Input (Tristate)	No output (Tristated)
	Open-drain Output	Input (External Pull-up)	Output ( = 0)External Pull-up ( = 1 or DISSO = 1)

Notes: 1. In these modes MOSI is active only during transfers. MOSI will be pulled high between transfers to allow other masters to control the line.
2. In Push-pull mode MOSI is active only during transfers, otherwise it is tristated to prevent line contention. A weak external pull-up may be required to prevent MOSI from floating.

17.4 Serial Clock Timing

The TSCK, CPHA, CPOL and SPR bits in SPCR control the shape and rate of SCK. The two SPR bits provide four possible bit clock rates when the SPI is in master mode. The TSCK bit also allows a timer-generated bit rate. In slave mode, the SPI will operate at the rate of the incoming SCK as long as it does not exceed the maximum bit rate. There are also four possible combinations of SCK phase and polarity with respect to the serial data. CPHA and CPOL determine which format is used for transmission. The SPI data transfer formats are shown in Figures 17-3 and 17-4. To prevent glitches on SCK from disrupting the interface, CPHA, CPOL, and SPR should not be modified while the interface is enabled, and the master device should be enabled before selecting the slave device(s).

Figure 17-3. SPI Transfer Format with CPHA = 0

SCK CYCLE # (FOR REFERENCE) SCK (CPOL=0) SCK (CPOL=1) MOSI (FROM MASTER) MISO (FROM SLAVE) SS (TO SLAVE)

Note: *Not defined but normally MSB of character just received.

Figure 17-4. SPI Transfer Format with CPHA = 1

SCK CYCLE # (FOR REFERENCE) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (FROM MASTER) MISO (FROM SLAVE) SS (TO SLAVE)

Note: *Not defined but normally LSB of previously transmitted character.

17.5 SPI Registers

Table 17-2. SPDR – SPI Data Register

SPDR Address = EAHNot Bit Addressable Reset Value = 00H (after cold reset)unchanged (after warm reset)
B	SPD7	SPD6	SPD5	SPD4	SPD3	SPD2	SPD1
	i	t	7	6	5	4	3
1 Writes to SPDR load the transmit buffer. In Master mode, a write also starts a transfer if the master is currently idle.In Slave mode, if data is not loaded to SPDR the SPI will echo the last byte received on the next transfer. Reads from SPDR return the value of the receive buffer, which is the last byte received. If SPDR is not read before completion of the next transfer, the old value will be lost.

Table 17-3. SPCR – SPI Control Register

SPCR Address = E9H Reset Value = 0000 0000BNot Bit Addressable
	TSCK	SPE	DORD	MSTR	CPOL	CPHA	SPR1	SPR0
Bit	7	6	5	4	3	2	1	0

Symbol	Function
TSCK	SCK Clock Mode. When TSCK = 0, the SCK baud rate is based on the system clock, divided by the SPR_1-0 ratio.When TSCK = 1, the SCK baud rate is based on the Timer 1 overflow rate, divided by the SPR_1-0 ratio.
SPE	SPI Enable. SPI = 1 enables the SPI channel and connects , MOSI, MISO and SCK to pins P1.4, P1.5, P1.6, and P1.7. SPI = 0 disables the SPI channel.
DORD	Data Order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission.
MSTR	Master/Slave Select. MSTR = 1 selects Master SPI mode. MSTR = 0 selects slave SPI mode.
CPOL	Clock Polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is low when not transmitting. Please refer to Figure 23-9 on SPI clock phase and polarity control.
CPHA	Clock Phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between master and slave. Please refer to Figure 23-9 on SPI clock phase and polarity control.
SPR0 SPR1	SPI Clock Rate Select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and the oscillator frequency, f_osc. , is as follows:
	SPR1 SPR0	SCK (TSCK = 0)	SCK (TSCK = 1)
	0	0	f_osc/4	f_T1OVF/4
	0	1	f_osc/8	f_T1OVF/8
	1	0	f_osc/32	f_T1OVF/32
	1	1	f_osc/64	f_T1OVF/64

Notes: 1. Set up the clock mode before enabling the SPI: set all bits needed in SPCR except the SPE bit, then set SPE.
2. Enable the master SPI prior to selecting the slave device (SS low).

Table 17-4. SPSR – SPI Status Register

SPSR Address = E8H Reset Value = 0000 X000BNot Bit Addressable
Bit	SPIF WCOL		MODF	TXE	-	SSIG	DISSO	ENH
	7	6	5	4	3	2	1	0
Symbol	Function
SPIF	SPI Transfer Complete Interrupt Flag. When a serial transfer is complete, the SPIF bit is set by hardware and an interrupt is generated if ESP = 1. The SPIF bit may be cleared by software or by reading the SPI status register followed by reading/writing the SPI data register.
WCOL	Write Collision Flag. The WCOL bit is set by hardware if SPDR is written while the transmit buffer is full. The ongoing transfer is not affected. WCOL may be cleared by software or by reading the SPI status register followed by reading/writing the SPI data register.
MODF	Mode Fault Flag. MODF is set by hardware when a master mode collision is detected (MSTR = 1, SSIG = 0 and = 0 ) and an interrupt is generated if ESP = 1. MODF must be cleared by software.
TXE	Transmit Buffer Empty Flag. Set by hardware when the transmit buffer is loaded into the shift register, allowing a new byte to be loaded. TXE must be cleared by software. When ENH = 1 and ESP = 1, TXE will generate an interrupt.
SSIG	Slave Select Ignore. If SSIG = 0, the SPI will only operate in slave mode if (P1.4) is pulled low. When SSIG = 1, the SPI ignores in slave mode and is active whenever SPE (SPCR.6) is set. When MSTR = 1 and SSIG = 0, is monitored for master mode collisions. Setting SSIG = 1 will ignore collisions on . P1.4 may be used as a regular I/O pin when SSIG = 1.
DISSO	Disable slave output bit. When set, this bit causes the MISO pin to be tristated so that more than one slave device can share the same interface without multiple lines. Normally, the first byte in a transmission could be the slave address and only the selected slave should clear its DISSO bit.
ENH	TX Buffer Interrupt Enable. When ENH = 1, TXE will generate an SPI interrupt if ESP = 1. When ENH = 0, TXE does not generate an interrupt.

18. Dual Analog Comparators

The AT89LP428/828 provides two analog comparators. The analog comparators have the following features:

• Internal 3-level Voltage Reference
• Multiple Shared Analog Input Channels
- Selectable Interrupt Conditions

– High- or Low-level
– Rising- or Falling-edge
- Output Toggle

• Hardware Debouncing Modes

A block diagram of the dual analog comparators with relevant connections is shown in Figure 18-1. Input options allow the comparators to function in a number of different configurations as shown in Figure 18-3. Comparator operation is such that the output is a logic "1" when the positive input is greater than the negative input. Otherwise, the output is a zero. Setting the CENA (ACSRA.3) and CENB (ACSRB.3) bits enable Comparator A and B, respectively. The user must also set the CONA (ACSRA.5) or CONB (ACSRB.5) bits to connect the comparator inputs before using a comparator. When a comparator is first enabled, the comparator output and

interrupt flag are not guaranteed to be stable for 10 s. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. Before enabling the comparators, the analog inputs should be tristated by putting P2.4, P2.5, P2.6 and P2.7 into input-only mode. See “Port 2 Analog Functions” on page 38.

Figure 18-1. Dual Comparator Block Diagram

graph TD
    subgraph Inputs
        A["(P2.7) AIN3"] --> B["CSB1"]
        C["(P2.6) AIN2"] --> D["CSB0"]
        E["(P2.5) AIN1"] --> F["CSA0"]
        G["(P2.4) AIN0"] --> H["CSA1"]
    end

    B --> I["AND Gate 11"]
    D --> J["AND Gate 10"]
    F --> K["AND Gate 01"]
    H --> L["AND Gate 00"]
    I --> M["Comparator B"]
    J --> N["Comparator A"]
    K --> O["Comparator B"]
    L --> P["Comparator A"]

    M --> Q["CMB2"]
    M --> R["CMB1"]
    M --> S["CMB0"]
    M --> T["CFB"]
    M --> U["CFA"]
    M --> V["CMPB (P4.7)"]
    M --> W["Interrupt"]
    M --> X["EC"]
    M --> Y["CMPA (P4.6)"]

    I --> Z["RFB0"]
    I --> AA["RFB1"]
    I --> AB["RFA1"]
    I --> AC["RFA0"]
    I --> AD["RFB0"]
    I --> AE["RFB1"]

    Q --> AF["CMA2"]
    Q --> AG["CMA1"]
    Q --> AH["CMA0"]

    M --> AI["VAREF+Δ"]
    M --> AJ["VAREF"]
    M --> AK["VAREF-Δ"]

    AI --> AL["Ground"]
    AJ --> AL
    AK --> AL
    AL --> M
    style Inputs fill:#f9f,stroke:#333
    style M fill:#ccf,stroke:#333

Each comparator may be configured to cause an interrupt under a variety of output value conditions by setting the CMx_2-0 bits in ACSRx. The comparator interrupt flags CFx in ACSRx are set whenever the comparator outputs match the conditions specified by CMx_2-0 . The flags may be polled by software or may be used to generate an interrupt and must be cleared by software. Both comparators share a common interrupt vector. If both comparators are enabled, the user needs to read the flags after entering the interrupt service routine to determine which comparator caused the interrupt.

The CAC1-0 and CBC1-0 bits in AREF control when the comparator interrupts sample the comparator outputs. Normally, the outputs are sampled every clock system; however, the outputs may also be sampled whenever Timer 0, Timer 1 or Timer 2 overflows. These settings allow the comparators to be sampled at a specific time or to reduce the number of comparator events seen by the system when using level sensitive modes. The comparators will continue to function during Idle mode. If this is not the desired behavior, the comparators should be disabled before entering Idle. The comparators are always disabled during Power-down mode.

18.1 Analog Input Muxes

The positive input terminal of each comparator may be connected to any of the four analog input pins by changing the CSA_1-0 or CSB_1-0 bits in ACSRA and ACSRB. When changing the analog input pins, the comparator must be disconnected from its inputs by clearing the CONA or CONB bits. The connection is restored by setting the bits again after the muxes have been modified.

CLR EC ; Disable comparator interrupts

ANL ACSRA, #0DFh ; Clear CONA to disconnect COMP A

... ; Modify CSA or RFA bits

ORL ACSRA, #020h ; Set CONA to connect COMP A

ANL ACSRA, #0EFh ; Clear any spurious interrupt

SETB EC ; Re-enable comparator interrupts

The corresponding comparator interrupt should not be enabled while the inputs are being changed, and the comparator interrupt flag must be cleared before the interrupt is re-enabled in order to prevent an unintentional interrupt request.

18.2 Internal Reference Voltage

The negative input terminal of each comparator may be connected to an internal voltage reference by changing the RFB_1-0 or RFA_1-0 bits in AREF. The internal reference voltage, V_AREF , is set to 1.25V ± 5% . The voltage reference also provides two additional voltage levels approximately 125 mV above and below V_AREF . These levels may be used to configure the comparators as an internally referenced window comparator with up to four input channels. Changing the reference input must follow the same routine used for changing the positive input as described in the “Analog Input Muxes” section.

18.3 Comparator Interrupt Debouncing

The comparator output is normally sampled every clock cycle. The conditions on the analog inputs may be such that the comparator output will toggle excessively. This is especially true if applying slow moving analog inputs. Three debouncing modes are provided to filter out this noise for edge-triggered interrupts. In debouncing mode, the comparator uses Timer 1 to modulate its sampling time when CxC_1-0 = 00B . When a relevant transition occurs, the comparator waits until two Timer 1 overflows have occurred before resampling the output. If the new sample agrees with the expected value, CFx is set. Otherwise, the event is ignored. The filter may be tuned by adjusting the time-out period of Timer 1. Because Timer 1 is running free, the debouncer must wait for two overflows to guarantee that the sampling delay is at least 1 time-out period. Therefore, after the initial edge event, the interrupt may occur between 1 and 2 time-out periods later. See Figure 18-2. When the comparator clock is provided by one of the timer overflows, i.e. CxC_1-0 = 00B , any change in the comparator output must be valid after 4 samples to be accepted as an edge event.

Figure 18-2. Negative Edge with Debouncing Example

Comparator Out Timer 1 Overflow CFx Start Compare (rejected) Start Compare (accepted)

Figure 18-3. Dual Comparator Configuration Examples
a. dual independent comparators with external references

AIN0 AIN1 + - A CMPA CSA = 00 RFA = 00 CSB = 11 RFB = 00 AIN3 AIN2 + - B CMPB

b. 3-channel comparator with external reference

AIN0 AIN2 AIN3 AIN1 CSA = 00/10/11 RFA = 00 CMPA

c. 4-channel comparator with internal reference

AIN0 AIN1 AIN2 AIN3 VAREF A CMPA CSA = 00/01/10/11 RFA = 10

d. 2-channel comparator with internal reference & comparator with external reference

AIN0 AIN1 VAREF A CMPA CSA = 00/01 RFA = 10 AIN3 AIN2 B CMPB CSB = 11 RFB = 00

e. 2-channel comparator with external reference & comparator with internal reference

AIN0 AIN2 AIN1 A CMPA CSA = 00/10 RFA = 00 AIN3 VAREF B CMPB CSB = 11 RFB = 10

f. 2-channel window comparator with external reference

AIN2 AIN0 AIN3 AIN1 B CMPB A CMPA CSA = CSB = 00/11 RFA = RFB = 00

g. 4-channel window comparator with internal reference

VAREF+Δ AIN0 AIN1 AIN2 AIN3 VAREF-Δ B CMPB A CMPA CSA = CSB = 00/01/10/11 RFA = 01 RFB = 11

Table 18-1. ACSRA – Analog Comparator a Control and Status Register

ACSRA = 97H Reset Value = 0000 0000BNot Bit Addressable
	CSA1 CSA0		CONA CFA	CENA CMA2	CMA1 CMA0
B	i	t	7	6	5	4	3	2

Symbol Function
CSA[1 - 0]	Comparator A Positive Input Channel Select(1)
	CSA1 CSA0	A+ Channel
	0	0	AIN0 (P2.4)
	0	1	AIN1 (P2.5)
	1	0	AIN2 (P2.6)
	1	1	AIN3 (P2.7)
CONA	Comparator A Input Connect. When CONA = 1 the analog input pins are connected to the comparator. When CONA = 0 the analog input pins are disconnected from the comparator. CONA must be cleared to 0 before changing CSA [1 - 0] or RFA [1 - 0].
CFA	Comparator A Interrupt Flag. Set when the comparator output meets the conditions specified by the CMA [2 - 0] bits and CENA is set. The flag must be cleared by software. The interrupt may be enabled/disabled by setting/clearing bit 6 of IE.
CENA	Comparator A Enable. Set this bit to enable the comparator. Clearing this bit will force the comparator output low and prevent further events from setting CFA. When CENA = 1 the analog input pins, P2.4 - P2.7, have their digital inputs disabled if they are configured in input-only mode.
CMA[2 - 0]	Comparator Interrupt Mode
	CMA2	CMA1	CMA0	Interrupt Mode
	0	0	0	Negative (Low) level
	0	0	1	Positive edge
	0	1	0	Toggle with debouncing(2)
	0	1	1	Positive edge with debouncing(2)
	1	0	0	Negative edge
	1	0	1	Toggle
	1	1	0	Negative edge with debouncing(2)
	1	1	1	Positive (High) level

Notes: 1. CONA must be cleared to 0 before changing CSA [1 - 0].
2. Debouncing modes require the use of Timer 1 to generate the sampling delay.

Table 18-2. ACSRB – Analog Comparator B Control and Status Register

ACSRB = 9FH Reset Value = 1100 0000BNot Bit Addressable
	CSB1 CSB0		CONB CFB CENB CMB2 CMB1 CMB0
B	i	t	7	6	5	4	3	2

Symbol Function
CSB[1 - 0]	Comparator B Positive Input Channel Select(1)
	CSB1 CSB0	B+ Channel
	0	0	AIN0 (P2.4)
	0	1	AIN1 (P2.5)
	1	0	AIN2 (P2.6)
	1	1	AIN3 (P2.7)
CONB	Comparator B Input Connect. When CONB = 1, the analog input pins are connected to the comparator. When CONB = 0 the analog input pins are disconnected from the comparator. CONB must be cleared to 0 before changing CSB [1 - 0] or RFB [1 - 0].
CFB	Comparator B Interrupt Flag. Set when the comparator output meets the conditions specified by the CMB [2 - 0] bits and CENB is set. The flag must be cleared by software. The interrupt may be enabled/disabled by setting/clearing bit 6 of IE.
CENB	Comparator B Enable. Set this bit to enable the comparator. Clearing this bit will force the comparator output low and prevent further events from setting CFB. When CENB = 1, the analog input pins, P2.4 - P2.7, have their digital inputs disabled if they are configured in input-only mode.
CMB[2 - 0]	Comparator B Interrupt Mode
	CMB2	CMB1	CMB0	Interrupt Mode
	0	0	0	Negative (Low) level
	0	0	1	Positive edge
	0	1	0	Toggle with debouncing(2)
	0	1	1	Positive edge with debouncing(2)
	1	0	0	Negative edge
	1	0	1	Toggle
	1	1	0	Negative edge with debouncing(2)
	1	1	1	Positive (High) level

Notes: 1. CONB must be cleared to 0 before changing CSB [1 - 0].
2. Debouncing modes require the use of Timer 1 to generate the sampling delay.

Table 18-3. AREF – Analog Comparator Reference Control Register

AREF = AFH Reset Value = 0000 0000BNot Bit Addressable
	CBC1 CBC0		RFB1 RFB0 CAC1 CAC0 RFA1 RFA0
B	i	t	7	6	5	4	3	2

Symbol Function
CSC[1 - 0]	Comparator B Clock Select
	CBC1	CBC0	Clock Source
	0	0	System Clock
	0	0	Timer 0 Overflow
	0	1	Timer 1 Overflow
	0	1	Timer 2 Overflow
RFB[1 - 0]	Comparator B Negative Input Channel Select ^(1)
	CRF1 RFB0	B-channel
	0	0	AIN2 (P2.6)
	0	0	Internal V_AREF- (~1.2V)
	0	1	Internal V_AREF (~1.3V)
	0	1	Internal V_AREF+ (~1.4V)
CAC[1 - 0]	Comparator A Clock Select
	CAC1	CAC0	Clock Source
	0	0	System Clock
	0	0	Timer 0 Overflow
	0	1	Timer 1 Overflow
	0	1	Timer 2 Overflow
RFB[1 - 0]	Comparator A Negative Input Channel Select ^(2)
	RFA1	RFA0	A-channel
	0	0	AIN1 (P2.5)
	0	0	Internal V_AREF- (~1.2V)
	0	1	Internal V_AREF (~1.3V)
	0	1	Internal V_AREF+ (~1.4V)

Notes: 1. CONB (ACSRB.5) must be cleared to 0 before changing RFB [1 - 0].
2. CONA (ACSRA.5) must be cleared to 0 before changing RFA [1 - 0].

19. Programmable Watchdog Timer

The programmable Watchdog Timer (WDT) protects the system from incorrect execution by triggering a system reset when it times out after the software has failed to feed the timer prior to the timer overflow. By Default the WDT counts CPU clock cycles. The prescaler bits, PS0, PS1 and PS2 in SFR WDTCON are used to set the period of the Watchdog Timer from 16K to 2048K clock cycles. The Timer Prescaler can also be used to lengthen the time-out period (see Table 6-2 on page 23) The WDT is disabled by Reset and during Power-down mode. When the WDT times out without being serviced, an internal RST pulse is generated to reset the CPU. See Table 19-1 for the available WDT period selections.

Table 19-1. Watchdog Timer Time-out Period Selection

WDT Prescaler Bits			Period ^(1) (Clock Cycles)PS2 PS1 PS0
0	0	0	1
0	0	1	3
0	1	0	6
0	1	1	1
1	0	0	2
1	0	1	5
1 1 0 1024K
1 1 1 2048K

Note: 1. The WDT time-out period is dependent on the system clock frequency.

$$ \text { Time - out Period } = \frac {2 ^ {(P S + 1 4)}}{\text { Oscillator Frequency }} \times (T P S + 1) $$

The Watchdog Timer consists of a 14-bit timer with 7-bit programmable prescaler. Writing the sequence 1EH/E1H to the WDTRST register enables the timer. When the WDT is enabled, the WDTEN bit in WDTCON will be set to "1". To prevent the WDT from generating a reset when if overflows, the watchdog feed sequence must be written to WDTRST before the end of the time-out period. To feed the watchdog, two write instructions must be sequentially executed successfully. Between the two write instructions, SFR reads are allowed, but writes are not allowed. The instructions should move 1EH to the WDTRST register and then 1EH to the WDTRST register. An incorrect feed or enable sequence will cause an immediate watchdog reset. The program sequence to feed or enable the watchdog timer is as follows:

MOV WDTRST, #01Eh

MOV WDTRST, #0E1h

19.1 Software Reset

A Software Reset of the AT89LP428/828 is accomplished by writing the software reset sequence 5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate the software reset. A normal software reset will set the SWRST flag in WDTCON. However, if at any time an incorrect sequence is written to WDTRST (i.e. anything other than 1EH/E1H or 5AH/A5H), a software reset will immediately be generated and both the SWRST and WDTOVF flags will be set. In this manner an intentional software reset may be distinguished from a software error-generated reset. The program sequence to generate a software reset is as follows:

MOV WDTRST, #05Ah

MOV WDTRST, #0A5h

Table 19-2. WDTCON – Watchdog Control Register

WDTCON Address = A7H Reset Value = 0000 X000BNot Bit Addressable
	PS2	PS1	PS0	WDIDLE	-	SWRST WDTOVF WDTEN
B	i	t	7	6	5	4	3	2
Symbol Function
PS2PS1PS0	Prescaler Bits for the Watchdog Timer (WDT). When all three bits are cleared to 0, the watchdog timer has a nominal period of 16K clock cycles. When all three bits are set to 1, the nominal period is 2048K clock cycles.
WDIDLE	Disable/enable the Watchdog Timer in IDLE Mode. When WDIDLE = 0, WDT continues to count in IDLE mode. When WDIDLE = 1, WDT freezes while the device is in IDLE mode.
SWRST	Software Reset Flag. Set when a software reset is generated by writing the sequence 5AH/A5H to WDTRST. Also set when an incorrect sequence is written to WDTRST. Must be cleared by software.
WDTOVF	Watchdog Overflow Flag. Set when a WDT rest is generated by the WDT timer overflow. Also set when an incorrect sequence is written to WDTRST. Must be cleared by software.
WDTEN	Watchdog Enable Flag. This bit is READ-ONLY and reflects the status of the WDT (whether it is running or not). The WDT is disabled after any reset and must be re-enabled by writing 1EH/E1H to WDTRST

Table 19-3. WDTRST – Watchdog Reset Register

WDTRST Address = A6H(Write-Only)Not Bit Addressable
B	-	-	-	-	-	-	-
	i	t	7	6	5	4	3

20. Instruction Set Summary

The AT89LP428/828 is fully binary compatible with the MCS-51 instruction set. The difference between the AT89LP428/828 and the standard 8051 is the number of cycles required to execute an instruction. Instructions in the AT89LP428/828 may take 1, 2, 3, 4 or 5 clock cycles to complete. The execution times of most instructions may be computed using Table 20-1 on page 107.

Table 20-1. Instruction Execution Times and Exceptions

Generic Instruction Types Cycle Count Formula
Most arithmetic, logical, bit and transfer instructions			# bytes
Branches and Calls			# bytes + 1
Single Byte Indirect (i.e. ADD A, @Ri, etc.) 2
RET, RETI 4
MOVC 3
MOVX 2/4			(2)
MUL 2
DIV 4
INC DPTR 2
Arithmetic Bytes		Clock Cycles		Hex Code8051
ADD A, Rn	1	12	1	28 - 2F
ADD A, direct	2	12	2	25
ADD A, @Ri	1	12	2	26 - 27
ADD A, #data	2	12	2	24
ADDC A, Rn	1	12	1	38 - 3F
ADDC A, direct	2	12	2	35
ADDC A, @Ri	1	12	2	36 - 37
ADDC A, #data	2	12	2	34
SUBB A, Rn	1	12	1	98 - 9F
SUBB A, direct	2	12	2	95
SUBB A, @Ri	1	12	2	96 - 97
SUBB A, #data	2	12	2	94
INC Rn	1	12	1	08 - 0F
INC direct	2	12	2	05
INC @Ri	1	12	2	06 - 07
INC A	2	12	2	04
DEC Rn	1	12	1	18 - 1F
DEC direct	2	12	2	15
DEC @Ri	1	12	2	16 - 17
DEC A	2	12	2	14
INC DPTR	1	24	2	A3
INC /DPTR^(1)	2	-	3	A5 A3
MUL AB 1 48 2 A4
DIV AB 1 48 4 84
DA A 1 12 1 D4
Logical Bytes		Clock Cycles		Hex Code8051AT89LP
CLR A 1 12 1 E4
CPL A	1 12 1 F4
ANL A, Rn	1 12 1 58	-5F
ANL A, direct	2 12 2 55
ANL A, @Ri	1 12 2 56	-57
ANL A, #data	2	12	2	54
ANL direct, A	2 12 2 52
ANL direct, #data	3	24	3	53
ORL A, Rn	1 12 1 48	-4F
ORL A, direct	2 12 2 45
ORL A, @Ri	1 12 2 46	-47
ORL A, #data	2	12	2	44
ORL direct, A	2 12 2 42
ORL direct, #data	3	24	3	43
XRL A, Rn	1 12 1 68	-6F
XRL A, direct	2 12 2 65
XRL A, @Ri	1 12 2 66	-67
XRL A, #data	2	12	2	64
XRL direct, A	2 12 2 62
XRL direct, #data	3	24	3	63
RL A	1 12 1 23
RLC A 1 12 1 33
RR A	1 12 1 03
RRC A	1 12 1 13
SWAP A	1 12 1 C4
Data Transfer	Bytes	Clock Cycles		Hex Code8051AT89LP
MOV A, Rn	1 12 1	E8 - EF
MOV A, direct	2 12 2 E5
MOV A, @Ri	1 12 2	E6 - E7
MOV A, #data	2	12	2	74
MOV Rn, A	1 12 1	F8 - FF
MOV Rn, direct	2 24 2	A8 - AF
MOV Rn, #data	2	12	2	78 - 7F
MOV direct, A 2 12 2 F5
MOV direct, Rn 2 24 2 88 - 8F
MOV direct, direct 3 24 3 85
MOV direct, @Ri 2 24 2 86 - 87
MOV direct, #data3 2	4		3
MOV @Ri, A 1 12 1 F6 - F7
MOV @Ri, direct 2 24 2 A6 - A7
MOV @Ri, #data2 12 2 76 - 77
MOV DPTR, #data16	3	24	3	90
MOV /DPTR, #data16^(1)	4	-	4	A5 90
MOVC A, @A+DPTR	1 24 3 93
MOVC A, @A+/DPTR^(1)	2	-	4	A5 93
MOVC A, @A+PC	1 24 3 83
MOVX A, @Ri	1 24 2 E2	-E3
MOVX A, @DPTR	1 24	2/4	(2)	E0
MOVX A, @/DPTR^(1)	2	-	3/5^(2)	A5 E0
MOVX @Ri, A	1 24 2 F2	-F3
MOVX @DPTR, A	1 24	2/4	(2)	F0
MOVX @/DPTR, A^(1)	2	-	3/5^(2)	A5 F0
PUSH direct	2	24	2	C0
POP direct	2 24 2	D0
XCH A, Rn	1 12 1	C8 - CF
XCH A, direct	2 12 2	C5
XCH A, @Ri	1 12 2	C6 - C7
XCHD A, @Ri	1 12 2	D6 - D7
Bit Operations Bytes		Clock Cycles		Hex Code
		8051	AT89LP
CLR C	1 12 1	C3
CLR bit	2	12	2	C2
SETB C	1 12 1	D3
SETB bit	2	12	2	D2
CPL C	1 12 1 B3
CPL bit	2	12	2	B2
ANL C, bit	2	24	2	82
ANL C, bit	2 24 2 B0
ORL C, bit	2 24 2 72
ORL C, /bit	2	24	2	A0
MOV C, bit	2	12	2	A2
MOV bit, C	2	24	2	92
Branching Bytes		Clock Cycles		Hex Code8051
JC rel 2 24 3 40
JNC rel 2 24 3 50
JB bit, rel	3 24 4 20
JNB bit, rel	3 24 4 30
JBC bit, rel	3 24 4 10
JZ rel	2 24 3 60
JNZ rel	2 24 3 70
SJMP rel	2 24 3 80
ACALL addr11	2 24 3			11,31,51,71,91,B1,D1,F1
LCALL addr16	3 24 4 12
RET	1 24 4 22
RETI	1 24 4 32
AJMP addr11	2 24 3			01,21,41,61,81,A1,C1,E1
LJMP addr16	3 24 4 02
JMP @A+DPTR	1 24 2 73
JMP @A+PC(1)	2	-	3	A5 73
CJNE A, direct, rel	3 24 4	B5
CJNE A, #data, rel	3	24	4	B4
CJNE Rn, #data, rel	3	24	4	B8 - BF
CJNE @Ri, #data, rel	3	24	4	B6 - B7
CJNE A, @R0, rel(1)	3	-	4	A5 B6
CJNE A, @R1, rel(1)	3	-	4	A5 B7
DJNZ Rn, rel	2 24 3	D8 - DF
DJNZ direct, rel	3 24 4	D5
NOP	1 12 1 00
BREAK(1)(3)	2	-	2	A5 00

AT89LP

Notes: 1. This escaped instruction is an extension to the instruction set.

1. MOVX @DPTR instructions take 2 clock cycles when accessing ERAM and 4 clock cycles when accessing FDATA or CODE. (3 and 5 cycles for MOVX @/DPTR).

2. The BREAK instruction acts as a 2 cycle NOP.

21. Register Index

Table 21-1. Special Function Register Cross Reference

Name Address Description Index
ACC E0H
ACSRA	97H	Table 18-1 on page 102
ACSRB	9FH	Table 18-2 on page 103
AREF	AFH	Table 18-3 on page 104
B	F0H
CLKREG	8FH	Table 6-2 on page 23
DPCF (AUXR1)	A2H	Table 5-4 on page 19
DPH0	83H	Section 5.1 on page 17
DPH1	85H	Section 5.1 on page 17
DPL0	82H	Section 5.1 on page 17
DPL1	83H	Section 5.1 on page 17
GPIEN	9CH	Table 15-3 on page 76
GPIF	9DH	Table 15-4 on page 76
GPLS	9BH	Table 15-2 on page 76
GPMOD	9AH	Table 15-1 on page 75
IE	A8H	Table 9-2 on page 32
IE2	B4H	Table 9-5 on page 33
IP	B8H	Table 9-3 on page 32
IP2	B5H	Table 9-6 on page 34
IPH	B7H	Table 9-4 on page 33
IP2H	B6H	Table 9-7 on page 34
MEMCON	96H	Table 3-4 on page 14
P1	90H	Table 10-3 on page 36
P1M0	C2H	Table 10-2 and Table 10-3 on page 36
P1M1	C3H	Table 10-2 and Table 10-3 on page 36
P2	A0H	Table 10-3 on page 36
P2M0	C4H	Table 10-2 and Table 10-3 on page 36
P2M1	C5H	Table 10-2 and Table 10-3 on page 36
P3	B0H	Table 10-3 on page 36
P3M0	C6H	Table 10-2 and Table 10-3 on page 36
P3M1	C7H	Table 10-2 and Table 10-3 on page 36
P4	C0H	Table 10-3 on page 36
P4M0	BEH	Table 10-2 and Table 10-3 on page 36
P4M1	BFH	Table 10-2 and Table 10-3 on page 36
PAGE	86H	Table 3-3 on page 11
PCON	87H	Table 8-1 on page 29
PSWD0H
RCAP2H	CBH	Section 12.1 on page 53
RCAP2L	CAH	Section 12.1 on page 53
RH0	94H	Table 11-1 on page 41
RH1	95H	Table 11-1 on page 41
RL0	92H	Table 11-1 on page 41
RL1	93H	Table 11-1 on page 41
SADDR	A9H	Section 16.7 on page 90
SADEN	B9H	Section 16.7 on page 90
SBUF	99H	Section 16.3 on page 81
SCON	98H	Table 16-1 on page 78
SP	8	1 H
SPCR	E9H	Table 17-3 on page 97
SPDR	EAH	Table 17-2 on page 97
SPSR	E8H	Table 17-4 on page 98
T2CCA	D1H	Table 13-1 on page 63
T2CCC	D4H	Table 13-4 on page 64
T2CCF D5H	T	able 13-5 on page 65
T2CCH	D3H	Table 13-2 on page 63
T2CCL	D2H	Table 13-3 on page 63
T2CON	C8H	Table 12-3 on page 53
T2MOD	C9H	Table 12-4 on page 54
TCON	88H	Table 11-2 on page 45
TCONB	91H	Table 11-4 on page 47
TH0	8CH	Table 11-1 on page 41
TH1	8DH	Table 11-1 on page 41
TH2	CDH	Section 12.1 on page 53
TL0	8AH	Table 11-1 on page 41
TL1	8BH	Table 11-1 on page 41
TL2	CCH	Section 12.1 on page 53
TMOD	89H	Table 11-3 on page 46
WDTCON	A7H	Table 19-2 on page 106
WDTRST	A6H	Table 19-3 on page 106

22. On-chip Debug System

The AT89LP428/828 On-chip Debug (OCD) System uses a 2-wire serial interface to control program flow; read, modify, and write the system state; and program the nonvolatile memory. The OCD System has the following features:

• Complete program flow control
• Read-modify-write access to all internal SFRs and data memories
• Four hardware program address breakpoints
• Unlimited program software breakpoints using BREAK instruction
• Break on change in program memory flow
• Break on stack overflow/underflow
• Break on Watchdog overflow
• Break on reset
  • Non-intrusive operation
• Programming of nonvolatile memory

22.1 Physical Interface

The On-chip Debug System uses a 2-wire synchronous serial interface to establish communication between the target device and the controlling emulator system. The OCD interface is controlled by two User Fuses. OCD is enabled by clearing the OCD Enable Fuse. The OCD device connections are shown in Figure 22-1. When OCD is enabled, the RST port pin is configured as an input for the Debug Clock (DCL). Either the XTAL1, XTAL2 or P3.7 pin is configured as a bi-directional data line for the Debug Data (DDA) depending on the clock source selected. If the Internal RC Oscillator is selected, XTAL1 is configured as DDA (A). If the External Clock is selected, XTAL2 is configured as DDA (B). If the Crystal Oscillator is selected, P3.7 is configured as DDA (C). When OCD is enabled, the type of interface used depends on the OCD Interface Select User Fuse. This fuse selects between a normal Two-wire Interface (TWI) and a fast Two-wire Interface (FTWI). It is the duty of the user to program this fuse to the correct setting for their debug system at the same time they enable OCD (see "User Configuration Fuses" on page 121).

When designing a system where On-chip Debug will be used, the following observations must be considered for correct operation:

• P3.6/RST cannot be connected directly to V_CC and any external capacitors connected to RST must be removed.
• All external reset sources must be removed.
• If P3.7 needs to be debugged in-system using the crystal oscillator, the external clock option should be selected. The quartz crystal and any capacitors on XTAL1 or XTAL2 must be removed and an external clock signal must be driven on XTAL1. Some emulator systems may provide a user-configurable clock for this purpose.

Figure 22-1. AT89LP428/828 On-chip Debug Connections

22.2 Software Breakpoints

The AT89LP428/828 microcontroller includes a BREAK instruction for implementing program memory breakpoints in software. A software breakpoint can be inserted manually by placing the BREAK instruction in the program code. Some emulator systems may allow for automatic insertion/deletion of software breakpoints. The Flash memory must be re-programmed each time a software breakpoint is changed. Frequent insertions/deletions of software breakpoints will reduce the endurance of the nonvolatile memory. Devices used for debugging purposes should not be shipped to end customers. The BREAK instruction is treated as a two-cycle NOP when OCD is disabled.

22.3 Limitations of On-chip Debug

The AT89LP428/828 is a fully-featured microcontroller that multiplexes several functions on its limited I/O pins. Some device functionality must be sacrificed to provide resources for On-chip Debugging. The On-chip Debug System has the following limitations:

• The Debug Clock pin (DCL) is physically located on that same pin as Port Pin P3.6 and the External Reset (RST). Therefore, neither P3.6 nor an external reset source may be emulated when OCD is enabled.
• When using the Internal RC Oscillator during debug, DDA is located on the XTAL1/P4.0 pin. The P4.0 I/O function cannot be emulated in this mode.
• When using the External Clock during debug, DDA is located on the XTAL2/P4.1 pin and the system clock drives XTAL1/P4.0. The P4.1 I/O and CLKOUT functions cannot be emulated in this mode.
• When using the Crystal Oscillator during debug, DDA is located on the P3.7 pin and the crystal connects to XTAL1/P4.0 and XTAL2/P4.1. The P3.6 I/O function cannot be emulated in this mode.

23. Programming the Flash Memory

The Atmel AT89LP428/828 microcontroller features 4K/8K bytes of on-chip In-System Programmable Flash program memory and 512/1024 bytes of nonvolatile Flash data memory. In-System Programming allows programming and reprogramming of the microcontroller positioned inside the end system. Using a simple 4-wire SPI interface, the programmer communicates serially with the AT89LP428/828 microcontroller, reprogramming all nonvolatile memories on the chip. In-System Programming eliminates the need for physical removal of the chips from the system. This will save time and money, both during development in the lab, and when updating the software or parameters in the field. The programming interface of the AT89LP428/828 includes the following features:

• 4-wire SPI Programming Interface
• Active-low Reset Entry into Programming
- Slave Select Allows Multiple Devices on Same Interface
- User Signature Array
- Flexible Page Programming
- Row Erase Capability
• Page Write with Auto-Erase Commands
- Programming Status Register

For more detailed information on In-System Programming, refer to the Application Note entitled "AT89LP In-System Programming Specification".

23.1 Physical Interface

Flash Programming utilizes the Serial Peripheral Interface (SPI) pins of an AT89LP428/828 microcontroller. The SPI is a full-duplex synchronous serial interface consisting of four wires: Serial Clock (SCK), Master-in/Slave-out (MISO), Master-out/Slave-in (MOSI), and an active-low Slave Select (SS). When programming an AT89LP428/828 device, the programmer always operates as the SPI master, and the target system always operates as the SPI slave. To enter or remain in Programming mode the device's reset line (RST) must be held active (low). With the addition of VCC and GND, an AT89LP428/828 microcontroller can be programmed with a minimum of seven connections as shown in Figure 23-1.

Figure 23-1. In-System Programming Device Connections

AT89LP428/LP828 Serial Clock → P1.7/SCK Serial Out ← P1.6/MISO VCC Serial In → P1.5/MOSI SS → P1.4/SS GND P3.6/RST ← RST

The Programming Interface is the only means of externally programming the AT89LP428/828 microcontroller. The Interface can be used to program the device both in-system and in a standalone serial programmer. The Interface does not require any clock other than SCK and is not limited by the system clock frequency. During Programming, the system clock source of the target device can operate normally.

When designing a system where In-System Programming will be used, the following observations must be considered for correct operation:

• The ISP interface uses the SPI clock mode 0 (CPOL = 0, CPHA = 0) exclusively with a maximum frequency of 5 MHz.
• The AT89LP428/828 will enter programming mode only when its reset line (RST) is active (low). To simplify this operation, it is recommended that the target reset can be controlled by the In-System programmer. To avoid problems, the In-System programmer should be able to keep the entire target system reset for the duration of the programming cycle. The target system should never attempt to drive the four SPI lines while reset is active.
• The R Sput may be disabled to gain an extra I/O pin. In these cases, the pin will always function as a reset during power up. To enter programming the pin must be driven low prior to the end of Power-on Reset (POR). After POR has completed, the device will remain in ISP mode until is brought high. Once the initial ISP session has ended, the power to the target device must be cycled OFF and ON to enter another session.
• The \$B should not be left floating during reset if ISP is enabled.
• The ISP Enable Fuse must be set to allow programming during any reset period. If the ISP Fuse is disabled, ISP may only be entered at POR.
• For standalone programmers, may be tied directly to GND to ensure correct entry into Programming mode regardless of the device settings.

23.2 Memory Organization

The AT89LP428/828 offers 4K/8K bytes of In-System Programmable (ISP) nonvolatile Flash code memory and 512/1024 bytes of nonvolatile Flash data memory. In addition, the device contains a 128-byte User Signature Array and a 64-byte read-only Atmel Signature Array. The memory organization is shown in Tables 23-1 and 23-2 and Figure 23-2. The memory is divided into pages of 64 bytes each. A single read or write command may only access a single page in the memory. Each memory type resides in its own address space and is accessed by commands specific to that memory. However, all memory types share the same page size.

User configuration fuses are mapped as a row in the memory, with each byte representing one fuse. From a programming standpoint, fuses are treated the same as normal code bytes except they are not affected by Chip Erase. Fuses can be enabled at any time by writing 00h to the appropriate locations in the fuse row. However, to disable a fuse, i.e. set it to FFh, the entire fuse row must be erased and then reprogrammed. The programmer should read the state of all the fuses into a temporary location, modify those fuses which need to be disabled, then issue a Fuse Write with Auto-Erase command using the temporary data. Lock bits are treated in a similar manner to fuses except they may only be erased (unlocked) by Chip Erase.

Table 23-1. Code Memory Size

Device # Code	Size Page Size # Pages Address Range
AT89LP428	4K bytes	64 bytes	64	0000H - 0FFFH
AT89LP828	8K bytes	64 bytes	128	0000H - 1FFFH

Table 23-2. Data Memory Size

Device # Data	Size Page Size # Pages Address Range
AT89LP428	512 bytes	64 bytes	8	0200H - 03FFH
AT89LP828	1024 bytes	64 bytes	16	0200H - 05FFH

Figure 23-2. AT89LP428/828 Memory Organization

User Fuse Row Page 0 User Signature Array Page 1 Page 0 Atmel Signature Array Page 0 Data Memory Page 15 05FF — Page 0 0200 Code Memory Page 127 1FFF Page 126 — Page 1 Page 0 0000 3F

23.3 Command Format

Programming commands consist of an opcode byte, two address bytes, and zero or more data bytes. In addition, all command packets must start with a two-byte preamble of AAH and 55H. The preamble increases the noise immunity of the programming interface by making it more difficult to issue unintentional commands. Figure 23-3 on page 118 shows a simplified flow chart of a command sequence.

A sample command packet is shown in Figure 23-4 on page 118. The SS pin defines the packet frame. SS must be brought low before the first byte in a command is sent and brought back high after the final byte in the command has been sent. The command is not complete until SS returns high. Command bytes are issued serially on MOSI. Data output bytes are received serially on MISO. Packets of variable length are supported by returning SS high when the final required byte has been transmitted. In some cases command bytes have a don't care value. Don't care bytes in the middle of a packet must be transmitted. Don't care bytes at the end of a packet may be ignored.

Page-oriented instructions always include a full 16-bit address. The higher order bits select the page and the lower order bits select the byte within that page. The AT89LP428/828 allocates 6 bits for byte address and 7 bits for page address. The page to be accessed is always fixed by the page address as transmitted. The byte address specifies the starting address for the first

data byte. After each data byte has been transmitted, the byte address is incremented to point to the next data byte. This allows a page command to linearly sweep the bytes within a page. If the byte address is incremented past the last byte in the page, the byte address will roll over to the first byte in the same page. While loading bytes into the page buffer, overwriting previously loaded bytes will result in data corruption.

For a summary of available commands, see Table 23-3 on page 119.

Figure 23-3. Command Sequence Flow Chart

graph TD
    A["Input Preamble 1 (AAH)"] --> B["Input Preamble 2 (55H)"]
    B --> C["Input Opcode"]
    C --> D["Input Address High Byte"]
    D --> E["Input Address Low Byte"]
    E --> F["Input/Output Data"]
    F --> G{Address +1}
    G --> C

Figure 23-4. ISP Command Packet

SS SCK MOSI MISO Preamble 1 Preamble 2 Opcode Address High Address Low Data In X X X X 7 0 6 5 4 3 2 1 7 0 6 5 4 3 2 1 Data Out

Table 23-3. Programming Command Summary

Command Opcode Addr High Addr Low Data 0 Data n
Program Enable ^(1)	1010 1100 01	01 0011 ---
Chip Erase	1000 1010	-	-	-	-
Read Status	0110 0000	xxxx xxxx	xxxx xxxx	Status Out
Load Page Buffer ^(2)	0101 0001	xxxx xxxx	00bb bbbb	DataIn 0 ... DataIn n
Write Code Page ^(2)	0101 0000	000a aaaa	aabb bbbb	DataIn 0 ... DataIn n
Write Code Page with Auto-Erase ^(2)	0111 0000	000a aaaa	aabb bbbb	DataIn 0 ... DataIn n
Read Code Page ^(2)	0011 0000	000a aaaa	aabb bbbb	DataOut 0 ... DataOut n
Write Data Page ^(2)	1101 0000	0000 0aaa	aabb bbbb	DataIn 0 ... DataIn n
Write Data Page with Auto-Erase ^(2)	1101 0010	0000 0aaa	aabb bbbb	DataIn 0 ... DataIn n
Read Data Page ^(2)	1011 0000	0000 0aaa	aabb bbbb	DataOut 0 ... DataOut n
Write User Fuses ^(2)(3)(4)	1110 0001	0000 0000	00bb bbbb	DataIn 0 ... DataIn n
Write User Fuses with Auto-Erase ^(2)(3)(4)	1111 0001	0000 0000	00bb bbbb	DataIn 0 ... DataIn n
Read User Fuses ^(2)(3)(4)	0110 0001	0000 0000	00bb bbbb	DataOut 0 ... DataOut n
Write Lock Bits ^(2)(3)(5)	1110 0100	0000 0000	00bb bbbb	DataIn 0 ... DataIn n
Read Lock Bits ^(2)(3)(5)	0110 0100	0000 0000	00bb bbbb	DataOut 0 ... DataOut n
Write User Signature Page ^(2)	0101 0010	0000 0000	0abb bbbb	DataIn 0 ... DataIn n
Write User Signature Page with Auto-Erase ^(2)	0111 0010	0000 0000	0abb bbbb	DataIn 0 ... DataIn n
Read User Signature Page ^(2)	0011 0010	0000 0000	0abb bbbb	DataOut 0 ... DataOut n
Read Atmel Signature Page ^(2)(6)	0011 1000	0000 0000	00bb bbbb	DataOut 0 ... DataOut n

Notes: 1. Program Enable must be the first command issued after entering into programming mode.
2. Any number of Data bytes from 1 to 64 may be written/read. The internal address is incremented between each byte.
3. Each byte address selects one fuse or lock bit. Data bytes must be 00H or FFH.
4. See Table 23-6 on page 121 for Fuse definitions.
5. See Tab le 23-5 on page 120 for Lock Bit definitions.
6. Atmel Signature Bytes:

Address:	0000H	0001H	0002H
AT89LP428:	1EH	40H	FFH
AT89LP828:	1EH	42H	FFH

1. Symbol Key:

a:	Page Address Bit
b:	Byte Address Bit
x:	Don't Care Bit

23.4 Status Register

The current state of the memory may be accessed by reading the status register. The status register is shown in Table 23-4.

Table 23-4. Status Register

	-	-	-	-		SUCCESS
B	i	t	7	6	5	4 3		2

Symbol Function
LOAD	Load Flag. Cleared low by the load page buffer command and set high by the next memory write. This flag signals that the page buffer was previously loaded with data by the load page buffer command.
SUCCESS	Success Flag. Cleared low at the start of a programming cycle and will only be set high if the programming cycle completes without interruption from the brownout detector (BOD).
WRTINH	Write Inhibit Flag. Cleared low by the BOD whenever programming is inhibited due to V_CC falling below the minimum required programming voltage. If a BOD episode occurs during programming, the SUCCESS flag will remain low after the cycle is complete. WRTINH low also forces BUSY low.
BUSY	Busy Flag. Cleared low whenever the memory is busy programming or if write is currently inhibited.

23.5 DATA Polling

The AT89LP428/828 implements DATA polling to indicate the end of a programming cycle. While the device is busy, any attempted read of the last byte written will return the data byte with the MSB complemented. Once the programming cycle has completed, the true value will be accessible. During Erase the data is assumed to be FFH and DATA polling will return 7FH. When writing multiple bytes in a page, the DATA value will be the last data byte loaded before programming begins, not the written byte with the highest physical address within the page.

23.6 Flash Security

The AT89LP428/828 provides two Lock Bits for Flash Code Memory security. Lock bits can be left unprogrammed (FFH) or programmed (00H) to obtain the protection levels listed in Table 23-5. Lock bits can only be erased (set to FFH) by Chip Erase. Lock bit mode 2 disables programming of all memory spaces, including the User Signature Array and User Configuration Fuses. User fuses must be programmed before enabling Lock bit mode 2 or 3. Lock bit mode 3 implements mode 2 and also blocks reads from the code memory; however, reads of the User Signature Array, Atmel Signature Array, and User Configuration Fuses are still allowed.

Table 23-5. Lock Bit Protection Modes

Program Lock Bits (by address)
Mode 00H	01H Protection Mode
1	FFH	FFH	No program lock features
2	00H	FFH	Further programming of the Flash is disabled
3	00H 00H		Further programming of the Flash is disabled and verify (read) is also disabled; OCD is disabled

23.7 User Configuration Fuses

The AT89LP428/828 includes 11 user fuses for configuration of the device. Each fuse is accessed at a separate address in the User Fuse Row as listed in Table 23-6. Fuses are cleared by programming 00H to their locations. Programming FFH to a fuse location will cause that fuse to maintain its previous state. To set a fuse (set to FFH), the fuse row must be erased and then reprogrammed using the Fuse Write with Auto-erase command. The default state for all fuses is FFH.

Table 23-6. User Configuration Fuse Definitions

Address Fuse Name Description
00 - 01H	Clock Source - CS [0:1](2)	Selects source for the system clock:CS1 CS0 Selected Source00H 00H High Speed Crystal Oscillator (XTAL)00H FFH Low Speed Crystal Oscillator (XTAL)FFH 00H External Clock on XTAL1 (XCLK)FFH FFH Internal RC Oscillator (IRC)
02 - 03H	Start-up Time - SUT [0:1]	Selects time-out delay for the POR/BOD/PWD wake-up period:SUT1 SUTO Selected Time-out00H 00H 1 ms (XTAL); 16 μs (XCLK/IRC)00H FFH 2 ms (XTAL); 512 μs (XCLK/IRC)FFH 00H 4 ms (XTAL); 1 ms (XCLK/IRC)FFH FFH 16 ms (XTAL); 4 ms (XCLK/IRC)
04H	Reset Pin Enable(3)	FFH: RST pin functions as reset00H: RST pin functions as general-purpose I/O
05H	Brown-out Detector Enable	FFH: Brown-out Detector Enabled00H: Brown-out Detector Disabled
06H	On-chip Debug Enable	FFH: On-chip Debug Disabled00H: On-chip Debug Enabled
07H	ISP Enable(3)	FFH: In-System Programming Enabled00H: In-System Programming Disabled (Enabled at POR only)
08H	User Signature Programming	FFH: Programming of User Signature Disabled00H: Programming of User Signature Enabled
09H	Tristate Ports	FFH: I/O Ports start in input-only mode (tristated) after reset00H: I/O Ports start in quasi-bidirectional mode after reset
0AH	OCD Interface Select	FFH: Fast Two-wire Interface00H: Do not use
0BH	In-Application Programming	FFH: In-Application Programming Disabled00H: In-Application Programming Enabled

Notes: 1. The default state for all fuses is FFH.
2. Changes to these fuses will only take effect after a device POR.
3. Changes to these fuses will only take effect after the ISP session terminates by bringing RST high.

23.8 User Signature and Analog Configuration

The User Signature Array contains 128 bytes of nonvolatile memory in two 64-byte pages. The first page of the User Signature Array (0000H - 003FH) is available for serial numbers, firmware revision information, date codes or other user parameters. The User Signature Array may only be written by an external device when the User Signature Programming Fuse is enabled. When the fuse is enabled, Chip Erase will also erase the first page of the array. When the fuse is disabled, the array is not affected by write or erase commands. Programming of the Signature Array can also be disabled by the Lock Bits. However, reading the signature is always allowed and the array should not be used to store security sensitive information. The User Signature Array may be modified during execution through the In-Application Programming interface, regardless of the state of the User Signature Programming fuse or Lock Bits, provided that the IAP Fuse is enabled. Note that the address of the User Signature Array, as seen by the IAP interface, equals the User Signature address plus 128 (0080H - 00FFH instead of 0000H - 007FH).

The second page of the User Signature Array (0040H - 007FH) contains analog configuration parameters for the AT89LP428/828. Each byte represents a parameter as listed in Table 23-7 and is preset in the factory. The parameters are read at POR and the device is configured accordingly. The second page of the array is not affected by Chip Erase. Other bytes in this page may be used as additional signature space; however, care should be taken to preserve the parameter values when modifying other bytes.

Table 23-7. Analog Configuration Definitions

Address Parameter Name Description
0040H	RC Oscillator Calibration Byte	The RC Calibration Byte controls the frequency of the internal RC oscillator. The frequency is inversely proportional to the calibration value such that higher values result in lower frequencies. A copy of the factory-set calibration value is stored at location 0008H of the Atmel Signature.

23.9 Programming Interface Timing

This section details general system timing sequences and constraints for entering or exiting In-System Programming as well as parameters related to the Serial Peripheral Interface during ISP. The general timing parameters for the following waveform figures are listed in section “Timing Parameters” on page 126.

23.9.1 Power-up Sequence

Execute this sequence to enter programming mode immediately after power-up. In the RST pin is disabled or if the ISP Fuse is disabled, this is the only method to enter programming (see "External Reset" on page 26).

1. Apply power between V cc and GND pins. RST should remain low.
2. Wait at least t_PWRUP and drive high.
3. Wait at least t_SUT for the internal Power-on Reset to complete. The value of t_SUT will depend on the current settings of the device.
4. Start programming session.

Figure 23-5. Serial Programming Power-up Sequence

VCC RST SS SCK tPWRUP tPOR + tsUT tzss HIGH ZMISO HIGH ZMOSI

23.9.2 Power-down Sequence

Execute this sequence to power-down the device after programming.

1. Drive SCK low.
2. Wait at least t_SSD and bring SS high.
3. Tristate MOSI.
4. Wait at least t_ssz and then tristate SS and SCK.
5. Wait no more than t_PWRDN and power off V_cc .

Figure 23-6. Serial Programming Power-down Sequence

VCC RST SS SCK tSSD tSSZ tPWRDN HIGH ZMISO HIGH ZMOSI

23.9.3 ISP Start Sequence

Execute this sequence to exit CPU execution mode and enter ISP mode when the device has passed Power-on Reset and is already operational.

1. Drive RST low.
2. Drive SS high.
3. Wait t RLZ + tSTL.
4. Start programming session.

Figure 23-7. In-System Programming (ISP) Start Sequence

VCC XTAL1 RST SS SCK tRLZ tSTL tZSS tSSE HIGH ZMISO- HIGH ZMOSI-

23.9.4 ISP Exit Sequence

Execute this sequence to exit ISP mode and resume CPU execution mode.

1. Drive SCK low.
2. Wait at least t_SSD and drive SS high.
3. Tristate MOSI.
4. Wait at least t_ssz and bring RST high.
5. Tristate SCK.
6. Wait t _RHZ and tristate SS.

Figure 23-8. In-System Programming (ISP) Exit Sequence

VCC XTAL1 RST SS SCK tSSD tSSZ tRHZ HIGH ZMISO HIGH ZMOSI

Note: The waveforms on this page are not to scale.

23.9.5 Serial Peripheral Interface

The Serial Peripheral Interface (SPI) is a byte-oriented full-duplex synchronous serial communication channel. During In-System Programming, the programmer always acts as the SPI master and the target device always acts as the SPI slave. The target device receives serial data on MOSI and outputs serial data on MISO. The Programming Interface implements a standard SPI Port with a fixed data order. For In-System Programming, bytes are transferred MSB first as shown in Figure 23-9. The SCK phase and polarity follow SPI clock mode 0 (CPOL = 0, CPHA = 0) where bits are sampled on the rising edge of SCK and output on the falling edge of SCK. For more detailed timing information see Figure 23-10.

Figure 23-10. Serial Programming Interface Timing

SS tSSE tSCK tSR tSF tSSD SCK tSHSL tSLSH MISO tSOE tSOV tSOH tSOX MOSI tSIS tSIH

23.9.6 Timing Parameters

The timing parameters for Figure 23-5, Figure 23-6, Figure 23-7, Figure 23-8, and Figure 23-10 are shown in Table 23-8.

Table 23-8. Programming Interface Timing Parameters

Symbol Parameter Min Max Units
t_CLCL	System Clock Cycle Time 0 60 ns
t_PWRUP	Power On to High Time	10		μs
t_POR	Power-on Reset Time		100	μs
t_PWRDN	Tristate to Power Off		1	μs
t_RLZ	Low to I/O Tristate	t_CLCL	2 t_CLCL	ns
t_STL	Low Settling Time	100		ns
t_RHZ	High to Tristate	0	2 t_CLCL	ns
t_SCK	Serial Clock Cycle Time	200^(1)		ns
t_SHSL	Clock High Time	75 ns
t_SLSH	Clock Low Time	50 ns
t_SR	Rise Time		25	ns
t_SF	Fall Time		25	ns
t_SIS	Serial Input Setup Time	10		ns
t_SIH	Serial Input Hold Time	10		ns
t_SOH	Serial Output Hold Time		10	ns
t_SOV	Serial Output Valid Time		35	ns
t_SOE	Output Enable Time		10	ns
t_SOX	Output Disable Time		25	ns
t_SSE	Enable Lead Time	t_SLSH		ns
t_SSD	Disable Lag Time	t_SLSH		ns
t_ZSS	SCK Setup to Low	25		ns
t_SSZ	SCK Hold after High	25		ns
t_WR	Write Cycle Time	2.5		ms
t_AWR	Write Cycle with Auto-Erase Time	5		ms
t_ERS	Chip Erase Cycle Time	7.5		ms

Note: 1. t SCK is independent of t_CLCL .

24. Electrical Characteristics

24.1 Absolute Maximum Ratings\*

Operating Temperature	-40°C to +85°C
Storage Temperature	-65°C to +150°C
Voltage on Any Pin with Respect to Ground	-0.7V to +5.5V
Maximum Operating Voltage	5.5V
DC Output Current	15.0 mA

*NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

24.2 DC Characteristics

T_A = -40^ to 85^ , V_CC = 2.4V to 5.5V (unless otherwise noted)

Symbol Parameter Condition Min Max Units
V_IL	Input Low-voltage		-0.5	0.3 V_CC	V
V_IH	Input High-voltage		0.7 V_CC	V_CC+0.5	V
V_OL	Output Low-voltage(1)	I_OL=8 mA, V_CC=5V±10%		0.4	V
		I_OL=4 mA		0.4
V_OH	Output High-voltageWith Weak Pull-ups Enabled	I_OH=-100 μA, V_CC=5V±10%	2.4		V
		I_OH=-25 μA	0.75 V_CC		V
		I_OH=-10 μA	0.9 V_CC		V
V_OH1	Output High-voltageWith Strong Pull-ups Enabled	I_OH=-20 mA, V_CC=5V±10%	0.75 V_CC
		I_OH=-8 mA, V_CC=5V±10%	0.9 V_CC
		I_OH=-6 mA	0.75 V_CC
		I_OH=-2 mA	0.9 V_CC
I_IL	Logic 0 Input Current	V_IN=0.45V		-100	μA
I_TL	Logic 1 to 0 Transition Current	V_IN=2.7V, V_CC=5V±10%		-300	μA
I_LI	Input Leakage Current	0< V_IN< V_CC		±10	μA
C_IO	Pin Capacitance	Test Freq. = 1 MHz, T_A=25°C		10	pF
I_CC	Power Supply Current	Active Mode, 12 MHz, V_CC=5V/3V		10/6	mA
		Idle Mode, 12 MHz, V_CC=5V/3V		5/3	mA
	Power-down Mode(2)	V_CC=5V		5	μA
		V_CC=3V		2	μA

Notes: 1. Under steady state (non-transient) conditions, I_OL must be externally limited as follows:
Maximum I_OL per port pin: 10 mA
Maximum total I_OL for all output pins: 15 mA
If I_OL exceeds the test condition, V_OL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
2. Minimum V_cc for Power-down is 2V.

24.3 Typical Characteristics

The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as quasi-bidirectional (with internal pull-ups). A square wave generator with rail-to-rail output is used as an external clock source for consumption versus frequency measurements.

24.3.1 Supply Current (Internal Oscillator)

Figure 24-1. Active Supply Current vs. Vcc (8 MHz Internal Oscillator)

Figure 24-2. Idle Supply Current vs. Vcc (8 MHz Internal Oscillator)

24.3.2 Supply Current (External Clock)

Figure 24-3. Active Supply Current vs. Frequency

Figure 24-4. Idle Supply Current vs. Frequency

24.3.3 Crystal Oscillator

Figure 24-5. Quartz Crystal Input at 5V

Figure 24-6. Ceramic Resonator Input at 5V

24.3.4 Quasi-Bidirectional Input

Figure 24-7. Quasi-bidirectional Input Transition Current at 5V

Figure 24-8. Quasi-bidirectional Input Transition Current at 3V

24.4 Clock Characteristics

The values shown in this table are valid for T_A = -40^ to 85^ and V_CC = 2.4 to 5.5V, unless otherwise noted.

Figure 24-9. External Clock Drive Waveform

Table 24-1. External Clock Parameters

Symbol Parameter		V_CC = 2.4V to 5.5V V		_cc = 4.0V to 5.5V		UnitsMin Max Min M
1/t_CLCL	Oscillator Frequency	0	20	0	25	MHz
t_CLCL	Clock Period 50 40	ns
t_CHCX	External Clock High Time	12		12		ns
t_CLCX	External Clock Low Time	12		12		ns
t_CLCH	External Clock Rise Time		5		4	ns
t_CHCL	External Clock Fall Time		5		4	ns

Table 24-2. Clock Characteristics

Symbol	Parameter	Condition	Min	Max	Units
f_XTAL	Crystal Oscillator Frequency	Low Speed Oscillator	10	500	kHz
		High Speed Oscillator	0.5	25	MHz
f_RC	Internal Oscillator Frequency	T_A = 25°C; V_CC = 5.0V	7.92	8.08	MHz
		V_DD = 2.4 to 5.5V	7.60	8.40	MHz

24.5 Reset Characteristics

The values shown in this table are valid for T_A = -40^ to 85^ and V_CC = 2.4 to 5.5V, unless otherwise noted.

Table 24-3. Reset Characteristics

Symbol	Parameter	Condition	Min	Max	Units
R_RST	Reset Pull-up Resistor		50	250	kΩ
V_POR	Power-On Reset Threshold		1.3	1.6	V
V_BOD	Brown-Out Detector Threshold		1.9	2.2	V
V_BH	Brown-Out Detector Hysteresis		200	300	mV
t_POR	Power-On Reset Delay		135	150	μs
t_WDTRST	Watchdog Reset Pulse Width		16t_CLCL		ns

24.6 Serial Peripheral Interface Timing

The values shown in this table are valid for T_A = -40^ to 85^ and V_CC = 2.4 to 5.5V, unless otherwise noted.

Table 24-4. SPI Master Characteristics

Symbol Parameter	Min Max Units
t_CLCL	Oscillator Period	50		ns
t_SCK	Serial Clock Cycle Time 4t	_CLCL		ns
t_SHSL	Clock High Time t	_SCK/2 - 25 ns
t_SLSH	Clock Low Time t	_SCK/2 - 25 ns
t_SR	Rise Time		25	ns
t_SF	Fall Time		25	ns
t_SIS	Serial Input Setup Time	10		ns
t_SIH	Serial Input Hold Time	10		ns
t_SOH	Serial Output Hold Time		10	ns
t_SOV	Serial Output Valid Time		35	ns

Table 24-5. SPI Slave Characteristics

Symbol Parameter	Min	Max	Units
t_CLCL	Oscillator Period	50		ns
t_SCK	Serial Clock Cycle Time	4t_CLCL		ns
t_SHSL	Clock High Time	1.5 t_CLCL - 25		ns
t_SLSH	Clock Low Time	1.5 t_CLCL - 25		ns
t_SR	Rise Time		25	ns
t_SF	Fall Time		25	ns
t_SIS	Serial Input Setup Time	10		ns
t_SIH	Serial Input Hold Time	10		ns
t_SOH	Serial Output Hold Time		10	ns
t_SOV	Serial Output Valid Time		35	ns
t_SOE	Output Enable Time		10	ns
t_SOX	Output Disable Time		25	ns
t_SSE	Slave Enable Lead Time	10		ns
t_SSD	Slave Disable Lag Time	0		ns

Figure 24-10. SPI Master Timing (CPHA = 0)

SS tSCK tsR tSF SCK (CPOL = 0) tSHSL tSLSH tSLSH tSHSL tSIS tSIH MISO tSOH tSOV MOSI

Figure 24-11. SPI Slave Timing (CPHA = 0)

SS tSSE tSCK tSR tSF tSSD SCK (CPOL = 0) tSHSL tSLSH tSHSL SCK (CPOL=1) tSLSH tSHSL MISO tSOE tSOV tSOH tSOX MOSI tsIS tsIH

Figure 24-12. SPI Master Timing (CPHA = 1)

SS tSCK tSF tSR SCK (CPOL = 0) tSHSL tSLSH tSR SCK (CPOL = 1) tSLSH tSHSL tSIS tSIH MISO tSOH tSOV MOSI

Figure 24-13. SPI Slave Timing (CPHA = 1)

SS tSSE tSCK tSF tSR tSSD SCK (CPOL = 0) tSHSL tSLSH tSHSL SCK (CPOL = 1) tSOE tSOV tSOH tSOX MISO tSIS tSIH MOSI

24.7 Dual Analog Comparator Characteristics

The values shown in this table are valid for T_A = -40^ to 85^ and V_CC = 2.4 to 5.5V, unless otherwise noted.

Table 24-6. Dual Analog Comparator Characteristics

Symbol Parameter Condition Min Max Units
V_CM	Common Mode Input Voltage		GND	V_DD	V
V_OS	Input Offset Voltage	V_CC=5.5V 20 mV
V_AREF	Analog Reference Voltage		1.2	1.3	V
V_ REF	Reference Delta Voltage		70	170	mV
t_CMP	Comparator Propagation Delay	V_IN+-V_IN-=20 mV; V_CC=2.4V		200	ns
t_AREF	Reference Settling Time		3		μs

Figure 24-14. Analog Reference Voltage Typical Characteristics

24.8 Serial Port Timing: Shift Register Mode

The values in this table are valid for V_CC = 2.4V to 5.5V and Load Capacitance = 80pF .

Symbol Parameter		Variable Oscillator		UnitsMin Max
t_XLXL	Serial Port Clock Cycle Time 2t	t_CLCL -15 μs
t_QVXH	Output Data Setup to Clock Rising Edge	t_CLCL -15 ns
t_XHQX	Output Data Hold after Clock Rising Edge	t_CLCL -15 ns
t_XHDX	Input Data Hold after Clock Rising Edge	0		ns
t_XHDV	Input Data Valid to Clock Rising Edge	15		ns

Figure 24-15. Shift Register Mode Timing Waveform

Clock Write to SBUF Output Data Clear RI Input Data tQVXH 0 1 2 3 4 5 6 7 tXHQX tXHDV Valid Valid Valid Valid Valid Valid Valid Valid Valid SET TI SET RI

24.9 Test Conditions

24.9.1 AC Testing Input/Output Waveform (1)

VCC - 0.5V 0.45V 0.2 VCC + 0.9V TEST POINTS 0.2 VCC - 0.1V

Note: 1. AC Inputs during testing are driven at V_CC - 0.5V for a logic "1" and 0.45V for a logic "0". Timing measurements are made at V_IH min. for a logic "1" and V_IL max. for a logic "0".

24.9.2 Float Waveform (1)

VLOAD VLOAD+ 0.1V Timing Reference Points VLOAD- 0.1V VOL- 0.1V VOL+ 0.1V

Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change from the loaded V_OH/V_OL level occurs.

24.9.3 I cc Test Condition, Active Mode, All Other Pins are Disconnected

VCC RST VCC Icc (NC) CLOCK SIGNAL XTAL2 XTAL1 GND

24.9.4 I cc Test Condition, Idle Mode, All Other Pins are Disconnected

Vcc RST Vcc (NC) CLOCK SIGNAL XTAL2 XTAL1 GND Vcc Icc

24.9.5 Clock Signal Waveform for I CC Tests in Active and Idle Modes, t_CLCH = t_CHCL = 5 ns

24.9.6 I cc Test Condition, Power-down Mode, All Other Pins are Disconnected, V_CC = 2V to 5.5V

VCC RST VCC Icc (NC) XTAL2 XTAL1 GND VCC

25. Ordering Information

25.1 Green Package (Pb/Halide-free)

Speed (MHz)	Power Supply Ordering Code Package Operation Range
20 2.4V to 5.5V	AT89LP428-20AUAT89LP428-20PUAT89LP428-20JUAT89LP428-20MU	32A28P332J32M1-A	Industrial(-40°C to 85°C)
	AT89LP828-20AUAT89LP828-20PUAT89LP828-20JUAT89LP828-20MU
25 4.0V to 5.5V	AT89LP428-25AUAT89LP428-25PUAT89LP428-25JUAT89LP428-25MU	32A28P332J32M1-A	Industrial(-40°C to 85°C)
	AT89LP828-25AUAT89LP828-25PUAT89LP828-25JUAT89LP828-25MU

Package Types
32A	32-lead, Thin Plastic Quad Flat Package (TQFP)
28P3	28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
32J	32-lead, Plastic J-leaded Chip Carrier (PLCC)
32M1-A	32-pad, 5 x 5 x1.0 mm Body, Lead Pitch 0.5 mm, Micro Lead Frame Package (MLF)

26. Packaging Information

26.1 32A - TQFP

PIN 1 PIN 1 IDENTIFIER B E1 E e D1 D C 0°~7° L A1 A2 A

COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL	MIN	NOM	MAX	NOTE
A--1.20
A1 0.05-0.15
A2 0.95 1.00 1.05
D 8.75	9.00	9.25
D1	6.90	7.00	7.10 Note 2
E	8.75	9.00	9.25
E1 6.90	7.00	7.10 Note 2
B	0.30	-0.45
C 0.09	-0.20
L	0.45-	0.75
e	0.80 TYP

10/5/2001

2325 Orchard ParkwaySan Jose, CA 95131

TITLE32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

DRAWING NO.32A

REV.B

26.2 28P3 - PDIP

Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL	MIN	NOM	MAX	NOTE
A--4.5724
A1 0.254--
D 35.00-35.51 Note 1
E 7.366-8.382
E1 7.112-7.518 Note 1
B 0.356-0.559
B1 1.143-1.78
B2 0.762-1.143
L 2.921-3.81
C 0.203-0.356
eB	--10	160
e	2.540 TYP

05/18/04

2325 Orchard Parkway San Jose, CA 95131

TITLE

28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP)

DRAWING NO.	REV.
28P3	C

26.3 32J - PLCC

COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL	MIN	NOM	MAX	NOTE
A 3.175 – 3.556
A1 1.524 – 2.413
A2 0.381 – –
D 12.319 – 12.573
D1 11.354 – 11.506 Note 2
D2	9.906 –	10.922
E	14.859 –	15.113
E1	13.894 –	14.046	Note 2
E2	12.471 –	13.487
B 0.660 – 0.813
B1 0.330 – 0.533
e	1.270 TYP

10/04/01
Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.

2325 Orchard Parkway San Jose, CA 95131

TITLE

32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)

DRAWING NO. REV.

32J

B

26.4 32M1-A - MLF

D D1 1 2 3 Pin 1 ID E1 E

TOP VIEW

Pin #1 Notch (0.20 R) K D2 P P E2 b e L 1 2 3 K

BOTTOM VIEW
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.

SIDE V A2 A A3 A1 0.08 C

SIDE VIEW

COMMON DIMENSIONS (Unit of Measure = mm)

SYMBOL	MIN	NOM	MAX	NOTE
A 0.80 0.90 1.00
A1 - 0.02 0.05
A2 - 0.65 1.00
A 3	0.20 REF
b	0.18	0.23	0.30
D	4.90 5.00 5.10
D1	4.70 4.75 4.80
D2 2.95 3.10 3.25
E	4.90 5.00 5.10
E1	4.70 4.75 4.80
E2 2.95 3.10 3.25
e	0.50 BSC
L	0.30	0.40	0.50
P	-	-	0.60
	-	-	12^
K	0.20 -	-

5/25/06

2325 Orchard Parkway San Jose, CA 95131

TITLE

32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)

DRAWING NO.	REV.
32M1-A	E

27. Revision History

Revision No. History
Revision A – August 2009	• Initial Release

Features 1

1 Pin Configurations ...... 2

1.1 28P3-28-lead PDIP 2
1.2 32A - 32-lead TQFP (Top View) ...... 2
1.3 32J-32-lead PLCC 2
1.4 32M1-A - 32-pad MLF(Top View) ...... 2
1.5 Pin Description ....3

2 Overview 5

2.1 Block Diagram 6
2.2 Comparison to Standard 8051 ....7

3 Memory Organization 8

3.1 Program Memory 9
3.2 Internal Data Memory 10
3.3 External Data Memory 11
3.4 In-Application Programming (IAP) 14

4 Special Function Registers 15

5 Enhanced CPU 16

5.1 Enhanced Dual Data Pointers 17
5.2 Restrictions on Certain Instructions ....20

6 System Clock 20

6.1 Crystal Oscillator 21
6.2 External Clock Source 21
6.3 Internal RC Oscillator 22
6.4 System Clock Out 22
6.5 System Clock Divider 22

7 Reset 23

7.1 Power-on Reset 23
7.2 Brown-out Reset 25
7.3 External Reset 26
7.4 Watchdog Reset 26
7.5 Software Reset 26

8 Power Saving Modes 26

8.1 Idle Mode 26
8.2 Power-down Mode ...... 27

9 Interrupts 29

9.1 Interrupt Response Time 31
9.2 Interrupt Registers 32

10 I/O Ports 35

10.1 Port Configuration 35
10.2 Port 2 Analog Functions ....38
10.3 Port Read-Modify-Write 39
10.4 Port Alternate Functions ....39

11 Enhanced Timer 0 and Timer 1 with PWM 41

11.1 Mode 0 – Variable Width Timer/Counter ....42
11.2 Mode 1 – 16-bit Auto-Reload Timer/Counter ....42
11.3 Mode 2 - 8-bit Auto-Reload Timer/Counter ....43
11.4 Mode 3 - 8-bit Split Timer ....44
11.5 Pulse Width Modulation 47

12 Enhanced Timer 2 .... 52

12.1 Timer 2 Registers ....53
12.2 Capture Mode 55
12.3 Auto-Reload Mode 55
12.4 Baud Rate Generator ....59
12.5 Frequency Generator (Programmable Clock Out) 60

13 Compare/Capture Array 61

13.1 CCA Registers 62
13.2 Input Capture Mode 65
13.3 Output Compare Mode 66
13.4 Pulse Width Modulation Mode 68

14 External Interrupts 74

15 General-purpose Interrupts 74

16 Serial Interface (UART) 77

16.1 Multiprocessor Communications 77

16.2 Baud Rates 79
16.3 More About Mode 0 ....81
16.4 More About Mode 1 85
16.5 More About Modes 2 and 3 87
16.6 Framing Error Detection 90
16.7 Automatic Address Recognition 90

17 Enhanced Serial Peripheral Interface 91

17.1 Master Operation 93
17.2 Slave Operation 94
17.3 Pin Configuration 95
17.4 Serial Clock Timing 96
17.5 SPI Registers 97

18 Dual Analog Comparators 98

18.1 Analog Input Muxes 100
18.2 Internal Reference Voltage ....100
18.3 Comparator Interrupt Debouncing 100

19 Programmable Watchdog Timer 105

19.1 Software Reset 106

20 Instruction Set Summary 107

21 Register Index 111

22 On-chip Debug System 113

22.1 Physical Interface 113
22.2 Software Breakpoints 114
22.3 Limitations of On-chip Debug 114

23 Programming the Flash Memory 115

23.1 Physical Interface 115
23.2 Memory Organization 116
23.3 Command Format 117
23.4 Status Register 120
23.5 DATA Polling 120
23.6 Flash Security 120
23.7 User Configuration Fuses 121

23.8 User Signature and Analog Configuration 122
23.9 Programming Interface Timing 122

24 Electrical Characteristics 127

24.1 Absolute Maximum Ratings* 127
24.2 DC Characteristics 127
24.3 Typical Characteristics 128
24.4 Clock Characteristics 132
24.5 Reset Characteristics 132
24.6 Serial Peripheral Interface Timing 133
24.7 Dual Analog Comparator Characteristics 135
24.8 Serial Port Timing: Shift Register Mode 136
24.9 Test Conditions 136

25 Ordering Information 138

25.1 Green Package (Pb/Halide-free) 138

26 Packaging Information 139

26.1 32A - TQFP ....139
26.2 28P3 – PDIP ....140
26.3 32J - PLCC ....141
26.4 32M1-A - MLF ....142

27 Revision History 143

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