SY58606U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY58606U Microchip

4.25 Gbps Precision, 1:2 CML Fanout Buffer with Internal Termination and Fail Safe Input

Features

• Precision 1:2, 400 mV CML Fanout Buffer
- Guaranteed AC Performance over Temperature and Voltage:

• DC-to >4.25 Gbps Throughput
• <320 ps Propagation Delay (IN-to-Q)
• <15 ps Within-Device Skew

• <85 ps Rise/Fall Times

• Fail Safe Input

• Prevents Outputs From Oscillating When Input is Invalid
• Ultra-Low Jitter Design
• 100 fs RMS Typical Additive Jitter
  • High-Speed CML Outputs
• 2.5V ±5% or 3.3V ±10% Power Supply Operation
• Industrial Temperature Range: -40^ to +85^
  • Available In 16-lead (3 mm x 3 mm) QFN Package

Applications

• Data Distribution: OC-48, OC-48+FEC, XAUI
• SONET Clock and Data Distribution
• Fibre Channel Clock and Data Distribution
• Gigabit Ethernet Clock And Data Distribution

Markets

• Storage
• ATE
  • Test and Measurement
• Enterprise Networking Equipment
  • High-End Servers
• Access
  • Metro Area Network Equipment

General Description

The SY58606U is a 2.5/3.3V, high-speed, fully differential 1:2 CML fanout buffer optimized to provide two identical output copies with less than 15 ps of skew and 100 fs _RMS of typical additive phase jitter. The SY58606U can process clock signals as fast as 3 GHz or data patterns up to 4.25 Gbps.

The differential input includes Microchip's unique, 3-lead input termination architecture that interfaces to LVPECL, LVDS, or CML differential signals, (AC- or DC-coupled) as small as 100 mV (200 mV PP ) without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an integrated voltage reference ( VREF-AC ) is provided to bias the V_T pin. The outputs are 400 mV CML, with extremely fast rise/fall times guaranteed to be less than 85 ps.

The SY58606U operates from a 2.5V ±5% supply or 3.3V ±10% supply and is guaranteed over the full industrial temperature range (-40°C to +85°C). For applications that require LVPECL or LVDS outputs, consider Microchip's SY58607U and SY58608U, 1:2 fanout buffers with 800 mV and 325 mV output swings respectively. The SY58606U is part of Microchip's high-speed, Precision Edge® product line.

Package Type

SY58606U 3 mm x 3 mm QFN-16 (M) (Top View) VCC GND GND VCC IN 16 15 14 13 VT 12 VREF-AC 11 /IN 3 10 VREF-AC 4 9 5 6 7 8 VCC GND GND VCC Q0 /Q0 Q1 /Q1

Functional Block Diagram

IN 50Ω VT 50Ω /IN VREF-AC Q0 /Q0 Q1 /Q1

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Supply Voltage ( V_CC )....-0.5V to +4.0V

Input Voltage ( V_IN ) -0.5V to V_CC

CML Output Voltage ( V_OUT ) V_CC - 1.0V to V_CC + 0.5V

Current ( I_T ) Source or Sink on VT Pin....±100 mA

Input Current Source or Sink Current on, IN, /IN....±50 mA

Current ( I_REF ) Source or Sink Current on VREF-AC (Note 1) .... ±1.5 mA

Maximum Operating Junction Temperature ....+125°C

Lead Temperature (Soldering, 20 sec.)....+260°C

Storage Temperature ( T_S )....-65°C to +150°C

Operating Ratings ††

Supply Voltage ( V_CC )....+2.375V to +3.60V

Ambient Temperature ( T_A ) -40^ to +85^

Package Thermal Resistance (Note 2)

QFN-16, Still-Air ( _JA ) 60°C/W

QFN-16, Junction-to-Board ( _JB ) 33°C/W

† Notice: Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.

†† Notice: The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.

Note 1: Due to the limited drive capability, use for input of the same package only.

2: Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB and _JA values are determined for a 4-layer board in still-air number, unless otherwise stated.

DC ELECTRICAL CHARACTERISTICS (Note 1)

Electrical Characteristics: T_A = -40^ to +85^ , unless otherwise stated.

Parameters Sym.	Min. Typ. Max.	Units Conditions
Power Supply Voltage Range	V_CC	2.375 2.5	2.625		V	—
		3.0 3.3	3.6
Power Supply Current I	CC	— 60 77	mA	No load, max. V	cc
Differential Input Resistance (IN-to-/IN)	R_DIFF\_IN	90 100	110Ω	—
Input HIGH Voltage (IN, /IN)	V_IH	V_CC - 1.6	— V	CC	VIN, /IN, Note 2
Input LOW Voltage (IN, /IN)	V_IL	0	—	V_IH - 0.1	VIN, /IN
Input Voltage Swing (IN, /IN)	V_IN	0.1	—	1.7	V	See Figure 5-5, (Note 3)
Differential Input Voltage Swing (|IN - /IN|)	V_DIFF\_IN	0.2	—	—	V	See Figure 5-6
Input Voltage Threshold that Triggers FSI	V_IN\_FSI	— 30 100	mV			—
Output Reference Voltage	V_REF-AC	V_CC - 1.3	V_CC - 1.2	V_CC - 1.1	V—
Voltage from Input to VT	V_T-IN	—	—	1.28	V—

Note 1: The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
2: V_IN(MIN) not lower than 1.2V.
3: V_IN(MAX) is specified when VT is floating.

CML OUTPUTS DC ELECTRICAL CHARACTERISTICS (Note 1)

Electrical Characteristics: V_CC = +2.5V ± 5% or +3.3V ± 10% , R_L = 100 across the outputs; T_A = -40^ to +85^ , unless otherwise stated.

Parameter	Symbol	Min.	Typ.	Max.	Units	Condition
Output High Voltage	V_OH	V_CC - 0.02	V_CC - 0.01	V_CC	V	R_L = 50 to V_CC
Output Voltage Swing	V_OUT	325	400	—	mV	See Figure 5-5
Differential Output Voltage Swing	V_DIFF\_OUT	650	800	—	mV	See Figure 5-6
Output Source Impedance	R_OUT	45	50	55		—

Note 1: The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC ELECTRICAL CHARACTERISTICS

Electrical Characteristics: V_CC = +2.5V ± 5% or +3.3V ± 10% , R_L = 100 across the outputs; Input t_r/t_f : ≤300 ps; T_A = -40^ to +85^ , unless otherwise stated.

Parameter Symbol	Min. Typ.	Max. Units Condition
Maximum Frequency f	MAX	4.25 — — Gbps NRZ (Data)
		2.5 3.0 — GHz V				OUT ≥ 200 mV (Clock), VIN ≥ 400 mV
Propagation Delay IN-to-Q	t_PD	150 270 400 ps V				IN: 100 mV-200
		120 220 320 ps V				IN: 200 mV-800
Within Device Skew	t_SKEW	—	3	15	ps	Note 1
Part-to-Part Skew		—	—	100	ps	Note 2
Additive Jitter	t_JITTER	—	100	—	fs_RMS	Carrier = 622 MHzIntegration Range: 12 kHz – 20 MHz
Output Rise/Fall Time(20% to 80%)	t_r, t_f	30	50	85	ps	At full output swing
Duty Cycle	—	47	—	53	%	Differential I/O

Note 1: Within-device skew is measured between two different outputs under identical input transitions.
2: Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs.

TEMPERATURE SPECIFICATIONS

Parameters	Sym.	Min.	Typ.	Max.	Units	Conditions
Temperature Ranges
Operating Ambient Temperature Range	T_A	-40	—	+85	°C	—
Maximum Operating Junction Temperature	T_J	—	—	+125 °C	—
Lead Temperature	—	—	—	+260	°C	Soldering, 20 sec.
Storage Temperature Range	T_S	-65	— +150 °C —
Package Thermal Resistances (Note 1)
Thermal Resistance, 3x3 QFN-16Ld	_JA	—	60	— °C/W	Still-air
	_JB	—	33	— °C/W	Junction-to-board

Note 1: Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB and _JA values are determined for a 4-layer board in still-air number, unless otherwise stated.

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

V_CC = 3.3V , GND = 0V, R_L = 100 across the outputs, T_A = +25^ , unless otherwise stated.

FIGURE 2-1: Propagation Delay vs. Input Rise/Fall Time.

FIGURE 2-4: Propagation Delay vs. Input Rise/Fall Time.

FIGURE 2-2: Propagation Delay vs. Input Rise/Fall Time.

FIGURE 2-3: Propagation Delay vs. Input Rise/Fall Time.

V_CC = 2.5V , GND = 0V, V_N = 325 mV, Data Pattern: 2^3-1 , R_L = 100 across the outputs, T_A = +25^ C , unless otherwise stated.

FIGURE 2-5: 1.25 Gbps Data.

TIME (60ps/div.) 1

FIGURE 2-8: 4.25 Gbps Data.

TIME (100ps/div.)

FIGURE 2-6: 2.5 Gbps Data.

FIGURE 2-9: 625 MHz Clock.

TIME (80ps/div.) 1

FIGURE 2-7: 3.2 Gbps Data.

FIGURE 2-10: 1.25 Ghz Clock.

FIGURE 2-11: 2 GHz Clock.

FIGURE 2-12: 3 GHz Clock.

3.0 ADDITIVE PHASE NOISE PLOT

$$ V _ {C C} = + 3. 3 V, T _ {A} = + 2 5 ^ {\circ} C. $$

FIGURE 3-1: Additive Noise Plot.

4.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 4-1.

TABLE 4-1: PIN FUNCTION TABLE

Pin Number Symbol Description
1, 4 IN, /IN Differential Input: This input pair is the differential signal input to the device.Input accepts DC-coupled differential signals as small as 100 (200 mVPP). Each pin of this pair internally terminates with 50Ω to the VT pin. If the input swing falls below a certain threshold (typical 30 mV), the Fail Safe Input (FSI) feature will guarantee a stable output by latching the output to its last valid state. See the Input Interface Applications section.
2	VT	Input Termination Center Tap: Each side of the differential input pair terminates to the VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. See the Input Interface Applications section.
3	VREF-AC	Reference Voltage: This output biases to VCC - 1.2V. It is used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01 μF low-ESR capacitor to VCC. Maximum sink/source current is ±1.5 mA. See the Input Interface Applications section.
5, 8,13, 16	VCC	Positive Power Supply: Bypass with 0.1 μF//0.01 μF low-ESR capacitors as close to the VCC pins as possible.
6, 7, 14, 15	GND, Exposed pad	Ground: Exposed pad must be connected to a ground plane that is the same potential as the ground pins.
9, 1011, 12	/Q1, Q1/Q0, Q0	CML Differential Output Pairs: Differential buffered copies of the input signal. The output swing is typically 400 mV. Unused output pair may be left floating with no impact on jitter. See the CML Output Termination section.

5.0 FUNCTIONAL DESCRIPTION

5.1 Fail-Safe Input (FSI)

The input includes a special fail-safe circuit to sense the amplitude of the input signal and to latch the outputs when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100 mV_PK ( 200 mV_PP ), typically 30 mV_PK . Maximum frequency of SY58606U is limited by the FSI function.

5.2 Input Clock Failure Case

If the input clock fails to a floating, static, or extremely low signal swing, then the FSI function will eliminate a metastable condition and guarantee a stable output. No ringing and no undetermined state will occur at the output under these conditions.

Note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to the Typical Performance Curves section for detailed information.

Timing Diagrams

/IN IN t_pd /Q Q V_IN t_pd V_OUT

FIGURE 5-1: Propagation Delay.

FIGURE 5-2: Fail Safe Feature.

Input and Output Stage

VCC IN 50Ω VT 50Ω /IN GND

FIGURE 5-3: Simplified Differential Input Buffer.

VCC 50Ω 50Ω /Q Q GND

FIGURE 5-4: Simplified CML Output Buffer.

Single-Ended and Differential Swings

V_IN, V_OUT 400mV (typical)

FIGURE 5-5: Single-Ended Swing.

V_DIFF_IN^a V_DIFF_OUT 800mV (typical)

FIGURE 5-6: Differential Swing.

6.0 INPUT INTERFACE APPLICATIONS

VCC CML IN /IN GND SY58606U NC VT VREF-ACNC

FIGURE 6-1: CML Interface (DC-Coupled) May connect VT to V_CC .

VCC LVPECL GND RP Rp VCC IN /IN 0.1μF VT VREF-AC SY58606U Note: For 3.3V, RP = 100Ω. For 2.5V, RP = 50Ω.

FIGURE 6-4: LVPECL Interface (AC-Coupled).

VCC CML GND IN /IN VCC 0.1μF VT VREF-AC SY58606U

FIGURE 6-2: CML Interface (AC-Coupled).

Vcc LVDS IN /IN SY58606U GND NC VT VREF-ACNC

FIGURE 6-5: LVDS Interface (DC-Coupled).

VCC LVPECL GND VCC 0.1μF RP IN /IN VT NC VREF-AC Note: For 3.3V, Rp = 50Ω. For 2.5V, Rp = 19Ω. SY58606U

FIGURE 6-3: LVPECL Interface (DC-Coupled).

7.0 CML OUTPUT TERMINATION

VCC 50Ω50Ω Z0 = 50Ω /Q 100Ω Z0 = 50Ω Q GND

FIGURE 7-1: CML DC-Coupled Termination.

VCC 50Ω50Ω Z0= 50Ω /Q 50Ω VBIAS Z0= 50Ω=50Ω Q GND

FIGURE 7-3: CML AC-Coupled Termination.

Vcc 50Ω50Ω Z0= 50Ω /Q 50Ω Vcc Z0= 50Ω=50Ω Q GND

FIGURE 7-2: CML DC-Coupled Termination.

8.0 PACKAGING INFORMATION

8.1 Package Marking Information

16-Lead QFN*

Example

Legend: XX...X Product code or customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week '01')

NNN Alphanumeric traceability code

ePb-free JEDEC ^® designator for Matte Tin (Sn)

* This package is Pb-free. The Pb-free JEDEC designator (e3) can be found on the outer packaging for this package.

•, ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle mark).

Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo.

Underbar (_) and/or Overbar (−) symbol may not be to scale.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

TITLE

16 LEAD QFN 3x3mm PACKAGE OUTLINE & RECOMMENDED LAND PATTERN

DRAWING # QFN33-16LD-PL-1

UNIT MM

PIN 1 DOT BY MARKING 3.0000±0.050 1 2 3.0000±0.050

TOP VIEW NOTE 1, 2, 3

1.5500±0.050 Exp.DAP PIN #1 IDENTIFICATION CHAMFER 0.300 X 45° 0.4000±0.050 1.5500±0.050 Exp.DAP 2 1.5000±0.050 Ref. 0.2300±0.050 BSC 0.5000

BOTTOM VIEW NOTE: 1, 2, 3

0.850±0.050 0.000-0.050 0.2030±0.025

SIDE VIEW NOTE 1, 2, 3

NOTE:

1. MAX PACKAGE WARPAGE IS 0.05 MM

2. MAX ALLOWABLE BURR IS 0.076 MM IN ALL DIRECTIONS

3. PIN #1 IS ON TOP WILL BE LASER MARKED

4. RED CIRCLE IN LAND PATTERN INDICATE THERMAL VIA. SIZE SHOULD BE 0.30-0.35 MM

IN DIAMETER AND SHOULD BE CONNECTED TO GND FOR MAX THERMAL PERFORMANCE

1. GREEN RECTANGLES (SHADED AREA) indicate SOLDER STENCIL OPENING ON EXPOSED

PAD AREA. SIZE SHOULD BE 0.60×0.60 MM IN SIZE, 0.20 MM SPACING.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

POD-Land Pattern drawing # QFN33-16LD-PL-1

RECOMMENDED LAND PATTERN NOTE: 4, 5

Symmetrical geometric diagram with green hatched squares surrounding a central crosshair (no text or symbols)

STACKED-UP

0.48±0.02 0.80±0.02 0.23±0.02 160±0.02 224±0.02 3.20±0.02 1.60±0.02 2.24±0.02 3.20±0.02 0.50 BSC

EXPOSED METAL TRACE

0.70±0.02 0.40±0.02 0.10±0.02 0.23±0.02 1.40±0.02 2.24±0.02 3.04±0.02 2.24±0.02 3.04±0.02

Revision A (May 2019)

• Converted Micrel document SY58606U to Microchip data sheet template DS20006199A.
• Minor text changes throughout.

NOTES:

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.

PART NO. X Device Supply Voltage X Package Temperature Range XX Tape and Reel

Device:

SY58606: 4.25 Gbps Precision, 1:2 CML Fanout Buffer with Internal Termination and Fail Safe Input

Supply Voltage:

U = 2.5V/3.3V

Package:

M = 3 mm x 3 mm QFN-16

Temperature Range:

G = -40^ to 85^ (NiPdAu Lead-Free)

Special Processing:

= 100/Tube TR = 1,000/Reel

Examples:

a) SY58606UMG: SY58606, 2.5V/3.3V Supply

Voltage, 3 mm x 3 mm 16-Lead

QFN, -40^ to +85^

Temperature Range, 100/Tube

b) SY58606UMG-TR: SY58606, 2.5V/3.3V Supply

Voltage, 3 mm x 3 mm 16-Lead

QFN, -40^ to +85^

Temperature Range, 1,000/Reel

Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.

NOTES:

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.
- Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
- There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
- Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC ^ MCUs and dsPIC ^ DSCs, KEELQ ^ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 16949=

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The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

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Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

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All other trademarks mentioned herein are property of their respective companies.

© 2019, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-4494-7

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