SY56020R - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY56020R Microchip

The SY56020R is a fully-differential, low-voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with input equalization. The SY56020R can process clock signals as fast as 4.5GHz or data patterns up to 6.4Gbps.

The differential input includes Micrel's unique, 3-pin input termination architecture that interfaces to CML differential signals, without any level-shifting or termination resistor networks in the signal path. The differential input can also accept AC-coupled LVPECL and LVDS signals. Input voltages as small as 200mV (400mV pp ) are applied before the 9", 18" or 27" FR4 transmission line. For AC-coupled input interface applications, an internal voltage reference is provided to bias the V T pin. The outputs are CML, with extremely fast rise/fall times guaranteed to be less than 90ps.

The SY56020R operates from a 2.5V ±5% core supply and a 1.2V, 1.8V or 2.5V ±5% output supply and is guaranteed over the full industrial temperature range ( -40^ to +85^ ). The SY56020R is part of Micrel's high-speed, Precision Edge ^® product line.

Datasheets and support documentation can be found on Micrel's web site at: www.micrel.com.

Functional Block Diagram

graph TD
    IN -->|50Ω| XOR1["Equalization"]
    VT -->|50Ω| XOR1
    /IN -->|50Ω| XOR1
    EQ["EQ (3 level input)"] --> XOR1
    XOR1 --> Q0["Q0"]
    XOR1 --> Q1["Q1"]
    XOR1 --> Q2["Q2"]
    XOR1 --> Q3["Q3"]
    Q0 --> Q0_out["/Q0"]
    Q1 --> Q1_out["/Q1"]
    Q2 --> Q2_out["/Q2"]
    Q3 --> Q3_out["/Q3"]

Precision Edge is a registered trademark of Micrel, Inc.

Precision Edge®

Features

• 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer
• Equalizes 9, 18, 27 inches of FR4
- Guaranteed AC performance over temperature and voltage:

- DC-to > 6.4Gbps Data throughput

- DC-to > 4.5GHz Clock throughput

- <280 ps propagation delay (IN-to-Q)

- <15ps within-device skew

- <90ps rise/fall times

• Ultra-low jitter design
• < 1 ps_RMS random jitter
  • High-speed CML outputs
• 2.5V ±5% V CC , 1.2/1.8V/2.5V ±5% V CCO power supply operation
• Industrial temperature range: -40^ to +85^
  • Available in 16-pin (3mm x 3mm) QFN package

Applications

• Data distribution
• SONET clock and data distribution
• Fiber Channel clock and data distribution
• Gigabit Ethernet clock and data distribution

Markets

• Storage
• ATE
  • Test and measurement
• Enterprise networking equipment
  • High-end servers
  • Metro area network equipment

Ordering Information

Part Number Package Type Operating Range Package Marking Lead Finish
SY56020RMG QFN-16 Industrial R020 with Pb-Free bar-line indicator				NiPdAuPb-Free
SY56020RMGTR(2) QFN-16 Industrial R020 with Pb-Free bar-line indicator				NiPdAuPb-Free

Notes:
1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ , DC Electricals only.
2. Tape and Reel.

Pin Configuration

VCC Q0 /Q0 VCCO 16 15 14 13 VT 1 12 Q1 IN 2 11 /Q1 /IN 3 10 Q2 EQ 4 9 /Q2 5 6 7 8 GND /Q3 Q3 VCCO

16-Pin QFN

Truth Table

EQ Equalization FR4 6mil Stripline
LOW	9"
FLOAT	18"
HIGH	27"

Pin Description

Pin Number	Pin Name Pin Function
2,3	IN,	Differential Input: Signals as small as 200mV V_PK (400m V_PP ) applied to the input of 9, 18 or 27 indnes 6mil FR4 stripline transmission line are then terminated with this differential input. Each input pin internally terminates with 50Ω to the VT pin.
1	VT	Input Termination Center-Tap: Each side of the differential input pair terminates to VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. An internal high impedance resistor divider biases VT to allow input AC-coupling. For AC-coupling, bypass VT with 0.1μF low-ESR capacitor to V_CC . See “Interface Applications” subsection and Figure 2a.
4 EQ Three level input for equalization control. High, float, low.
16	VCC	Positive Power Supply: Bypass with 0.1μF//0.01μF low-ESR capacitors as close to the V_CC pins as possible. Supplies input and core circuitry.
8,13	VCCO	Output Supply: Bypass with 0.1μF//0.01μF low-ESR capacitors as close to the V_CCO pins as possible. Supplies the output buffers.
5	GND, Exposed pad	Ground: Exposed pad must be connected to a ground plane that is the same potential as the ground pins.
15,14	Q0, /Q0
12,11	Q1, /Q1	CML Differential Output Pairs: Differential buffered copy of the input signal. The output swing is typically 390mV. See “Interface Applications” subsection for termination information.
10,9	Q2, /Q2
7,6	Q3, /Q3

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_cc )....-0.5V to +3.0V

Supply Voltage ( V_CCO ) -0.5V to +3.0V

CML Output Voltage ( V_OUT ).... 0.6V to 3.0V

Current ( V_T )

Source or Sink on VT pin....±100mA

Input Current

Source or Sink Current on (IN, /IN) ....±50mA

Maximum Operating Junction Temperature..... 125°C

Lead Temperature (soldering, 20sec.).... 260°C

Storage Temperature ( T_s ) -65^ to +150^

Operating Ratings ^(2)

Supply Voltage ( V_cc ) 2.375V to 2.625V

(V_cc0) 1.14V to 2.625V

Ambient Temperature ( T_A )....-40°C to +85°C

Package Thermal Resistance ^(3)

QFN

Still-Air ( _JA )....75°C/W

Junction-to-Board (_JB) 33°C/W

DC Electrical Characteristics ^(4)

T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter Condition	Min. Typ. Max. Units
V_CC	Power Supply Voltage Range	V_CC	2.375	2.5	2.625	V
		V_CCO	1.14	1.2	1.26
		V_CCO	1.7	1.8	1.9
		V_CCO	2.375	2.5	2.625
I_CC	Power Supply Current	Maximum V_CC .		60	85	mA
I_CCO	Power Supply Current	No Load. Maximum V_CCO .		64	84	mA
R_IN	Input Resistance (IN-to- V_T , /IN-to- V_T )		45	50	55	Ω
R_DIFF\_IN	Differential Input Resistance (IN-to-/IN)		90	100	110	Ω
V_IH	Input HIGH Voltage (IN, /IN)	IN, /IN	1.42		cc	V V
V_IL	Input LOW Voltage (IN, /IN)	IN, /IN1.22V = 1.7-0.475	1.22		V_IH-0.2	V
V_IN	Input Voltage Swing (IN, /IN)	See Figure 3a, applied to input of transmission line.	0.2		1.0	V
V_DIFF\_IN	Differential Input Voltage Swing (|IN - /IN|)	See Figure 3b, applied to input of transmission line.	0.4		2.0	V
V_T\_IN	Voltage from Input to V_T				1.28	V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB and _JA values are determined for a 4-layer board in still-air number, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

CML Outputs DC Electrical Characteristics ^(5)

V_CCO = 1.14V to 1.26V R_L = 50 to V_CCO

V_cc0 = 1.7V to 1.9V , 2.375V to 2.625V , R_L = 50 to V_cc0 or 100 across the outputs.

V_CC = 2.375V to 2.625V ; T_A = -40^ C to +85^ C , unless otherwise stated.

Symbol	Parameter Condition	Min.	Typ.	Max.	Units
V_OH Output HIGH Voltage R		_L=50 to V_CCO			V_CC-0.020 V	_CC-0.010	V_CC	V
V_OUT Output Voltage Swing See Figure 3a		300	390	475 mV
V_DIFF\_OU T	Differential Output Voltage Swing	See Figure 3b			600	780	950	mV
R_OUT	Output Source Impedance				45	50	55

Three Level EQ Input DC Electrical Characteristics ^(5)

V_CC = 2.375V to 2.625V ; T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min.	Typ.	Max.	Units
V_IH	Input HIGH Voltage		V_CC - 0.3		V_CC	V
V_IL	Input LOW Voltage		0		V_EE + 0.3	V
I_IH	Input HIGH Current	V_IH = V_CC			400	μA
I_IL	Input LOW Current	V_IL = GND	-480			μA

Note:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC Electrical Characteristics

V_CCO = 1.14V to 1.26V R_L = 50 to V_CCO

V_CCO = 1.7V to 1.9V , 2.375V to 2.625V , R_L = 50 to V_CCO or 100 across the outputs,

V_CC = 2.375V to 2.625V ; T_A = -40^ C to +85^ C , unless otherwise stated.

Symbol	Parameter	Condition	Min.	Typ.	Max.	Units
f_MAX	Maximum Frequency	NRZ Data	6.4			Gbps
		V_OUT > 200mV Clock	4.5			GHz
t_PD	Propagation Delay IN-to-Q	Note 6, Figure 1	100	180	280	ps
t_Skew	Output-to-Output Skew	Note 7		3	15	ps
	Part-to-Part Skew	Note 8			100	ps
t_Jitter	Random Jitter	Note 9			1	ps_RMS
t_rt_f	Output Rise/Fall Time(20% to 80%)	At full output swing.	20	50	90	ps

Notes:

1. Propagation delay is measured with no attenuating transmission line connected to the input.
2. Output-to-Output skew is the difference in time between both outputs, receiving data from the same input, for the same temperature, voltage and transition.
3. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs.
4. Random jitter is measured with a K28.7 pattern, measured at ≤ f_MAX .

Interface Applications

For Input Interface Applications see Figures 4a-e and for CML Output Termination, see Figures 5a-d.

CML Output Termination with VCCO 1.2V

For VCCO of 1.2V, Figure 5a, terminate the output with 50Ω to 1.2V, DC coupled, not 100Ω differentially across the outputs.

If AC-coupling is used, Figure 5d, terminate into 50Ω to 1.2V before the coupling capacitor and then connect to a high value resistor to a reference voltage.

Do not AC-couple with internally terminated receiver. For example, 50Ω ANY-IN input. AC-coupling will offset the output voltage by 200mV and this offset voltage will be too low for proper driver operation. Any unused output pair needs to be terminated when VCCO is 1.2V, do not leave floating.

CML Output Termination with VCCO 1.8V, 2.5V

For VCCO of 1.8V, Figure 5a and Figure 5b, terminate either with 50 ohms to VCCO or 100 ohms differentially across the outputs. AC- or DC-coupling is fine. For best signal integrity, terminate any unused output pairs.

Input Termination

From 1.8V CML driver: Terminate input with VT tied to 1.8V. Don't terminate 100 ohms differentially.

From 2.5V CML driver: Terminate input with either VT tied to 2.5V or 100 ohms differentially.

The input cannot be DC-coupled from a 1.2V CML driver.

Input AC-Coupling

The SY56020R input can accept AC-coupling from any driver. Bypass VT with a 0.1μF low-ESR capacitor to VCC as shown in Figures 4c and 4d. VT has an internal high impedance resistor divider as shown in Figure 2a, to provide a bias voltage for AC-coupling.

Timing Diagrams

/IN IN /Q Q tpd

Figure 1. Propagation Delay
Figure 1. Propagation Delay

Typical Characteristics

V_CC = 2.5, V_CCO = 1.2V, GND = 0V, V_IN = 400mV, R_L = 50 to 1.2V, Data Pattern: 2^23-1, T_A = 25^, unless otherwise stated.

6.4Gbps, 24 inch FR4 Output Swing (100mv/div) TIME (50ps/div.)

6.4Gbps, 18 inch FR4 Output Swing (100mv/div) TIME (50ps/div.)

6.4Gbps, 9 inch FR4 Output Swing (100mv/div) TIME (50ps/div.)

Input and Output Stage

VCC 12.5k IN 50Ω VT 50Ω 33k JIN GND GND

VCCO 50Ω 50Ω /Q / Q GND

Figure 2a. Simplified Differential Input Buffer Figure 2b. Simplified CML Output Buffer

Single-Ended and Differential Swings

V_IN V_OUT 400mV (Typ.)

VDIFF_IN VDIFF_OUT 800mV (Typ.)

Figure 3a. Single-Ended Swing Figure 3b. Differential Swing

Input Interface Applications

Vcc (2.5V) CML IN IN GND SY56020R NC VT

Figure 4a. CML Interface (DC-Coupled, 1.8V, 2.5V)
Option: May connect V_T to V_CC

VCC (1.8V, 2.5V) CML GND VCC (1.8V, 2.5V) IN /IN VT SY56020R

Figure 4b. CML Interface (DC-Coupled, 1.8V, 2.5V)

VCC (1.8V,2.5V,3.3V) CML GND VCC 0.1μF IN /IN SY56020R VT

Figure 4c. CML Interface (AC-Coupled)

VCC (3.3V, 2.5V) LVPECL GND Rp Rp GND IN IN VCC 0.1μF VT For 3.3V, Rp = 100Ω. For 2.5V, Rp = 50Ω. SY56020R

Figure 4d. LVPECL Interface (AC-Coupled)

VCC LVDS GND IN /IN VCC 0.1μF VT SY56020R

Figure 4e. LVPECL Interface (DC-Coupled)

CML Output Termination

VCCO (1.2V, 1.8V, 2.5V) 50Ω 50Ω Q Zc = 50Ω IN 50Ω VCCO (1.2V, 1.8V, 2.5V) 50Ω Zc = 50Ω /IN /Q GND

Figure 5a. 1.2V, 1.8V or 2.5V CML DC-Coupled Termination

Vcc0 (1.8V, 2.5V) 50Ω 50Ω Q Z0 = 50Ω IN 100Ω Z0 = 50Ω /Q /IN GND

Figure 5b. 1.8V or 2.5V CML DC-Coupled Termination

VCCO (1.8V, 2.5V) 50Ω 50Ω Q Z0 = 50Ω IN 50Ω VBIAS 50Ω /Ω Z0 = 50Ω /IN GND

Figure 5c. CML AC-Coupled Termination (Vcco 1.8V or 2.5V)

VCCO (1.2V) 50Ω 50Ω Q Zc = 50Ω 1.2V 50Ω IN 1kΩ VBias /Q Zc = 50Ω /IN 1kΩ 50Ω 1.2V GND

Figure 5d. CML AC-Coupled Termination ( V_cco 1.2V only)

Related Product and Support Documents

Part Number Function Datasheet Link
HBW Solutions	New Products and Termination Application Notes	http://www.micrel.com/page.do?page=/product-info/as/HBWsolutions.shtml

Package Information

Pin 1 Dot By Marking 3.000BSC 1 2 3 3.000BSC 16

TOP VIEW

PIN #1 ID. 1.60±0.100 Exp. DAP CHAMFER 0.30 X 45° 1 2 1.60±0.10 Exp. DAP 0.500 BSC 0.25±0.05 0.400±0.050 1.500 Ref. R0.20 + 1 2

VARIATION A
VARIATION B
BOTTOM VIEW

0.850±0.050 SEATING PLANE 0.000-0.050 0.203±0.025

SIDE VIEW
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm. 3. MAXIMUM ALLOWABE BURRS IS 0.076 mm IN ALL DIRECTIONS.
4 PIN #1 ID ON TOP WILL BE LASER/INK MARKED. DIMENSION APPLIES TO METALIZED TERMINAL AND IS MEASURED BETWEEN 0.20 AND 0.25 mm FROM TERMINAL TIP.
APPLIED ONLY FOR TERMINALS.
APPLIED FOR EXPOSED PAD AND TERMINALS.

16-Pin QFN

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