SY58034U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY58034U Microchip

■ Provides six ultra-low skew copies of the selected input
■ 2:1 MUX input included for clock switchover applications
■ Guaranteed AC performance over temperature and voltage:

• Clock frequency range: DC to > 6GHz
- <290ps IN-to-OUT t_pd
- < 60pstr/tf times
• <20ps skew (output-to-output)

■ Unique input isolation design minimizes crosstalk
■ Ultra low-jitter design:

• 60fs RMS phase jitter

• <0.7ps _RMS crosstalk-induced jitter

■ Low supply voltage operation: 2.5V and 3.3V
■ Unique input termination and VT pin accepts DC-coupled and AC-coupled inputs (CML, PECL, LVDS)
■ Internal 50Ω output source termination
■ 400mV CML output swing
- -40°C to +85°C temperature range
■ Available in 32-pin (5mm x 5mm) QFN package

Precision Edge®

DESCRIPTION

The SY58034U is a 2.5V/3.3V precision, high-speed 1:6 fanout buffer capable of handling clocks up to 6GHz. A differential 2:1 MUX input is included for redundant clock switchover applications.

The differential input includes Micrel's unique, 3-pin input termination architecture that allows the device to interface to any differential signal (AC- or DC-coupled) as small as 100mV without any level shifting or termination resistor networks in the signal path. The outputs are 50y source terminated CML, with extremely fast rise/fall times guaranteed to be less than 60ps.

The SY58034U operates from a 2.5V ±5% supply or a 3.3V ±10% supply and is guaranteed over the full industrial temperature range of -40°C to +85°C. For applications that require LVPECL outputs, consider the SY58035U or SY58036U Multiplexers. The SY58034U is part of Micrel's high-speed, Precision Edge® product line.

All support documentation can be found on Micrel's web site at www.micrel.com.

APPLICATIONS

■ Redundant clock distribution
■ All SONET/SDH clock distribution
■ All Fibre Channel distribution
■ All Gigabit Ethernet clock distribution

FUNCTIONAL BLOCK DIAGRAM

graph TD
    A["IN0"] --> B["50Ω"]
    C["V_T0"] --> D["50Ω"]
    E["/IN0"] --> F["0"]
    G["V_REF-AC0"] --> H["1"]
    I["IN1"] --> J["50Ω"]
    K["V_T1"] --> L["50Ω"]
    M["/IN1"] --> N["0"]
    O["V_REF-AC1"] --> P["1"]
    Q["SEL (TTL/CMOS)"] --> R["2:1 MUX"]
    R --> S["MUX"]
    T["1:6 Fanout"] --> U["Q0"]
    T --> V["/Q0"]
    T --> W["Q1"]
    T --> X["/Q1"]
    T --> Y["Q2"]
    T --> Z["/Q2"]
    T --> AA["Q3"]
    T --> AB["/Q3"]
    T --> AC["Q4"]
    T --> AD["/Q4"]
    T --> AE["Q5"]
    T --> AF["/Q5"]

Precision Edge is a registered trademark of Micrel, Inc.

PACKAGE/ORDERING INFORMATION

GND SEL VCC Q0 /Q0 /Q1 /Q1 VCC IN0 32 31 30 29 28 27 26 25 1 24 VCC VREF-AC0 23 22 /IN0 3 /IN1 4 VT0 5 VT1 6 VREF-AC1 7 /IN1 8 9 10 11 12 13 14 15 16 GND VCC /Q2 /Q2 Q3 /Q3 VCC GND VCC VREF-AC1 VCC GND

32-Pin QFN

Ordering Information ^(1)

Part Number	Package Type	Operating Range	Package Marking	Lead Finish
SY58034UMG	QFN-32	Industrial	SY58034U with Pb-free bar-line indicator	NiPdAu Pb-Free
SY58034UMGTR(2)	QFN-32	Industrial	SY58034U with Pb-free bar-line indicator	NiPdAu Pb-Free

Notes:

1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ , DC electricals only.

2. Tape and Reel.

PIN DESCRIPTION

Pin Number	Pin Name	Pin Function
1, 45, 8	IN0, /IN0IN1, /IN1	Differential Input: These input pairs are the differential signal inputs to the device. These inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50 . Note that these inputs will default to an indeterminate state if left open. Please refer to the “Input Interface Applications” section for more details.
2, 6	VT0, VT1	Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section for more details.
31	SEL	This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. The MUX select switchover function is asynchronous.
10	NC	No connect.
11, 16, 18,23, 25, 30	VCC	Positive Power Supply: Bypass with 0.1 F^TMTM 0.01μF low ESR capacitors and place as close to the VCC pins as possible.
29, 2827, 2622, 2120, 1915, 1413, 12	Q0, /Q0,Q1, /Q1,Q2, /Q2,Q3, /Q3,Q4, /Q4,Q5, /Q5	Differential Outputs: These CML output pairs are low skew output copies of the selected input. The output stage is optimized to deliver a 400mV swing (single-ended) into 50 . Each output includes a 50 source-termination resistor, thus minimizing any return reflections. Unused output pins may be left floating. Please refer to the “Truth Table” for details.
9, 17, 24, 32	GND,Exposed Pad	Ground. Ground pin and exposed pad must be connected to the same ground plane.
3, 7	VREF-AC0,VREF-AC1	Reference Voltage: These output biases to V_CC-1.2V . It is used for AC-coupling inputs (IN, /IN). Connect V_REF-AC directly to the VT pin. Bypass with 0.01μF low ESR capacitor to V_CC . See “Input Interface Applications” section. Maximum sink/source current is ±1.5mA. Due to the limited capability, the VREF-AC pin is only intended to drive its respective VT pin.

TRUTH TABLE

SEL
0	IN0 Input Selected
1	IN1 Input Selected

Absolute Maximum Ratings ^(1)

Power Supply Voltage ( V_CC ) ..... -0.5V to +4.0V

Input Voltage ( V_IN ) ...... -0.5V to V_CC

CML Output Voltage ( V_OUT ) ...... V_CC-1.0V to V_CC+0.5V

Termination Current

Source or sink current on VT pin ....±100mA

Input Current

Source or sink current on IN, /IN pin ....±50mA

Source or sink current on VREF-AC pin ....±2mA

Lead Temperature (soldering, 20 sec.) 260°C

Storage Temperature Range ( T_S ) .....-65°C to +150°C

Operating Ratings ^(2)

Power Supply Voltage ( V_CC ) ..... +2.375V to +2.625V ..... +3.0V to +3.6V

Ambient Temperature Range ( T_A ) ..... -40°C to +85°C

Package Thermal Resistance ^(3)

QFN ( _JA ) Still-Air 35°C/W

QFN ( _JB ) Junction-to-Board..... 16°C/W

DC ELECTRICAL CHARACTERISTICS ^(4)

T_A = -40^ to 85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_CC	Power Supply Voltage		2.375	2.5	2.625	V
			3.0	3.3	3.6	V
I_CC	Power Supply Current	No load, max. V_CC		245	320	mA
R_DIFF\_IN	Differential Input Resistance|IN-/IN|		90	100	110
R_IN	Input Resistance (IN-to-VT)		45	50	55
V_IH	Input HIGH Voltage (IN, /IN)	Note 5	V_CC-1.6		V_CC	V
V_IL	Input LOW Voltage (IN, /IN)		0		V_IH-0.1	V
V_IN	Input Voltage Swing (IN, /IN)	See Figure 1a.	0.1		1.7	V
V_DIFF\_IN	Differential Input Voltage Swing|IN, /IN|	See Figure 1b.	0.2			V
V_T IN	IN to V_T (IN, /IN)				1.28	V
V_REF-AC	Reference Voltage		V_CC-1.3	V_CC-1.2	V_CC-1.1	V

Notes:

1. Permanent device damage may occur if the measurements in the "Absolute Maximum Ratings" section are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Thermal performance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB and _JA are determined for a 4-layer board in a still air, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. V_IH (min) not lower than 1.2V.

CML OUTPUT DC ELECTRICAL CHARACTERISTICS ^(6)
V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C to 85^ C ; R_L = 100y across each output pair or equivalent, unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units
V_OH	Output HIGH Voltage R	_L=50 to V_CC	V_CC-0.020 V	_CC	V
V_OUT	Output Voltage Swing See Figure 1a. 325 400 mV
V_DIFF\_OUT	Differential Output Voltage Swing See Figure 1b. 650 800 mV
R_OUT	Output Source Impedance 40 50	60

LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS ^(6)
V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C to 85^ C , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_IH	Input HIGH Voltage		2.0			V
V_IL	Input LOW Voltage				0.8	V
I_IH	Input HIGH Current		-125		40	μA
I_IL	Input LOW Current		-300			μA

Note:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC ELECTRICAL CHARACTERISTICS ^(7)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C to 85^ C , R_L = 100y across each output pair, or equivalent, unless otherwise stated.

						stinUxaMp
f_MAX	Maximum Operating Frequency	Clock V_OUT 200mV	6	7.5		GHz
t_pd	Differential Propagation Delay(IN0 or IN1-to-Q)(SEL-to-Q)		140	220	290	ps
			100	200	400	ps
t_pd Tempco	Differential Propagation DelayTemperature Coefficient			65		fs/°C
t_SKEW	Output-to-OutputPart-to-Part	Note 8			20	ps
		Note 9			100	ps
t_JITTER	RMS Phase Jitter	Output = 622MHzIntegration range: 12kHz - 20MHz		60		fs
	Adjacent ChannelCrosstalk-Induced Jitter	Note 10			0.7	ps_RMS
t_r, t_f	Output Rise/Fall Time	Full swing, 20% to 80%	20		60	ps

Notes:

1. High frequency AC electricals are guaranteed by design and characterization.
2. Output-to-output skew is measured between outputs under identical transitions.
3. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
4. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the inputs.

SINGLE-ENDED AND DIFFERENTIAL SWINGS

V_{IN}, \nV_{OUT} 400mV (Typ.)

Figure 1a. Single-Ended Voltage Swing

VDIFF_IN, VDIFF_OUT 800mV (Typ.)

Figure 1b. Differential Voltage Swing

TIMING DIAGRAMS

TYPICAL OPERATING CHARACTERISTICS

V_CC = 2.5V , GND = 0, V_IN = 100mV , R_L = 100 across the output; T_A = 25^ , unless otherwise stated.

Output Swing vs. Frequency

Propagation Delay vs. Temperature

FUNCTIONAL CHARACTERISTICS

V_CC = 2.5V , GND = 0, V_IN = 400mV , R_L = 100 across the output; T_A = 25^ , unless otherwise stated.

INPUT AND OUTPUT STAGES

Vcc IN 50Ω VT 50Ω /IN GND

Figure 2a. Simplified Differential Input Stage

Vcc 50Ω50Ω /Q Q GND

Figure 2b. Simplified CML Output Stage

INPUT INTERFACE APPLICATIONS

Vcc CML IN /IN GND SY58034U VREF-ACNC NC VT Option: May connect VT to Vcc

Figure 3a. CML Interface (DC-Coupled)

VCC CML IN /IN GND VCC 0.01μF SY58034U VREF-AC VT

Figure 3b. CML Interface (AC-Coupled)

Vcc LVPECL GND IN IN SY58034U VREF-ACNC VT Vcc 0.01μF Rpd For 3.3V, Rpd = 50Ω. For 3.5V, Rpd = 19Ω.

Figure 3c. LVPECL Interface (DC-Coupled)

VCC LVPECL IN Rpd Rpd GND VCC VREF-AC VT 0.01μF For 3.3V, Ppd = 100Ω For 2.5V, Ppd = 50Ω SY58034U

Figure 3d. LVPECL Interface (AC-Coupled)

Vcc LVDS GND IN /IN SY58034U VREF-ACNC VTNC

Figure 3e. LVDS Interface

OUTPUT INTERFACE APPLICATIONS

VCC 50Ω 50Ω /Q 100Ω Q 16mA GND

Figure 4. CML DC-Coupled Termination

VCC 50Ω 50Ω /Q Q 50Ω DC bias point per application 50Ω 16mA GND

Figure 5. CML AC-Coupled Termination

RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION

Part Number	Function	Data Sheet Link
SY58035U	4.5GHz, 1:6 LVPECL Fanout Buffer with 2:1 MUX Input and Internal Termination	http://www.micrel.com/product-info/products/sy58035u.shtml
SY58036U	6GHz, 1:6 400mV LVPECL Fanout Buffer with 2:1 MUX Input and Internal Termination	http://www.micrel.com/product-info/products/sy58036u.shtml
HBW Solutions	New Products and Applications	www.micrel.com/product-info/products/solutions.shtml

32-PIN QFN (QFN-32)

5.0 BSC 32 1 2 PIN #1 ID 0.20 DIA TYP. 5.0 BSC

TOP VIEW

0.25±0.05 32X 0.20 MIN. 3.10±0.10 0.40±0.05 4X 0.50 BSC 32 PIN #1 ID R0.20 1 2 3.10±0.10

BOTTOM VIEW

0.85±0.05 SEATING PLANE 0.00~0.05 0.20 REF

NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm.
3. MAXIMUM ALLOWABE BURRS IS 0.076 mm IN ALL DIRECTIONS.
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.

SIDE VIEW

Package EP- Exposed Pad Die Comp/Side Island Heat Dissipation Heat Dissipation Heavy Copper Plane Vee Heavy Copper Plane

PCB Thermal Consideration for 32-Pin QFN Package (Always solder, or equivalent, the exposed pad to the PCB)

Package Notes:

1. Package meets Level 2 qualification.
2. All parts are dry-packaged before shipment.
3. Exposed pads must be soldered to a ground for proper thermal management.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

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The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify

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