SY88073L/83L - Carte d'évaluation Microchip - Free user manual and instructions

USER MANUAL SY88073L/83L Microchip

SY88073L/SY88083L Evaluation Board

1G to 12.5G Limiting Post Amplifiers with Programmable Decision Threshold (073L) Digital Offset Correction (083L)

General Description

The SY88073L/083L evaluation board enables fast and thorough evaluation of the SY88073L/083L limiting amplifiers.

The board is an easy-to-use, single-supply design, driven by a high-speed pattern generator and terminated to a 50Ω scope. The board features simple user adjustability of the LOS threshold, through the adjustment of an on-board potentiometer and different setting options selections using jumpers.

The SY88073L/083L are part of Micrel's industry-leading family of ultra-small high-speed fiber-optic ICs.

Datasheets and support documentation are available on Micrel's web site at: www.micrel.com.

Features

• Multi-rate operation from 1.0625Gbps to 12.5Gbps
• External crosspoint adjustment (073L)
• Digital offset correction (083L)
- Wide differential input range (10mV PP to 1800mV PP )
- Wide SD de-assert or LOS assert threshold range - 4.5mV PP to 30mV PP - 4dB typical electrical hysteresis

- Fast SD assert and LOS de-assert times - 1μs typical; 2μs maximum

- Selectable LOS or SD status signal indicator

- Selectable RXOUT+/RXOUT– polarity (073L)

- TTL-compatible JAM input with internal pull-up

- Low-noise CML data inputs with integrated 50Ω termination impedance to internal reference V_REF

- Low-noise CML data outputs with integrated 50Ω termination impedance - 30ps typical rise/fall times

- Wide range power supply: 3.3V ±10%

- Industrial temp range: -40^ to +85^

• Available in a tiny 3mm x 3mm QFN package

Applications

• 10G Gigabit Ethernet,
• 8G and 10G Fibre Channel
• SONET OC192; SDH STM64
• WDM/DWDM systems
• OBSAI, CPRI

Markets

• PON/FTTx - XGPON.2 ONU/ONT
  • Telecom, datacom/enterprise
• Storage area networks
  • High-performance computing
• Wireless

Ordering Information ^(1)

Ordering Part Number	PCB Revision	Description
SY88073L-EVAL	SY88073L-EB-1-A	Evaluation Board for 1.0625G to 12.5G Limiting Post Amplifier with Programmable Decision Threshold
SY88083L-EVAL	SY88073L-EB-1-A	Evaluation Board for 1.0625G to 12.5G Limiting Post Amplifier with Digital Offset Correction

Note:
1. The same evaluation board (SY88073L-EB-1-A) is used for both SY88073L and SY88083L.

Evaluation Board

SQUELCH FUNCTION: INSTALL JUMPER BETWEEN /EN AND SQL NO SQUELCH FUNCTION: INSTALL JUMPER BETWEEN /EN AND GND LOS: KEEP OPEN OR APPLY HIGH SD: INSTALL JUMPER 083L: INSTALL JUMPER TO DISABLE DOC KEEP OPEN OR APPLY HIGH TO ENABLE DOC 073L: INSTALL JUMPER IF NO CROSSING ADJUST REMOVE JUMPER AND APPLY VOLTAGE TO VTHP TO ADJUST CROSSING 083L: N/A 073L: KEEP OPEN OR APPLY HIGH FOR NORMAL POLARITY INSTALL JUMPER FOR POLARITY INVERSION OUTPUT INPUT MICREL HIT/ATI SEVED COMMUNICATIONS 408 235-1740 S788073L-LB-1-A RXOUT- J4 SD/LOSLVL ADJUST SQUELCH FUNCTION: INSTALL JUMPER BETWEEN LOS AND SQL NO SQUELCH FUNCTION: KEEP OPEN 083L: N/A 073L: INSTALL JUMPER BETWEEN VTHN AND GND IF NO CROSSING ADJUST INSTALL JUMPER BETWEEN VTHN AND VTHREF TO ADJUST CROSSING

Evaluation Board Description

The SY88073L/083L evaluation board is designed to operate with a single 3.3V ±10% power supply and is configured with AC-coupled inputs and outputs. The high-speed input and output signals are brought out to SMA connectors through matched length AC-coupled differential traces.

AC-Coupled Input

The AC-coupled inputs are internally biased as follows:

- For the SY88073L, the internal 50Ω resistors are terminated to V_CC - 1.2V . For the SY88083L, the internal 50Ω resistors are terminated to V_CC - 0.9V .

AC-Coupled Output

The board is configured with AC-coupled outputs to interface directly with 50Ω load equipment inputs. If only one output is used, the unused complementary output must be terminated with 50Ω-to-ground.

Coupling Capacitors Selection

The coupling capacitor value should be carefully selected, especially when the same circuit is used for multi-rate applications.

The RC time constant created by the capacitor and the input termination resistor can cause a baseline DC droop if the selected capacitor value is too small for the data rate and the data pattern contains long strings of Consecutive Identical Digits (CID). It can also cause pattern-dependent jitter if the selected value is too large for the data rate. Choose the coupling capacitor value to get an optimized low-frequency cutoff that minimizes the two problems together.

For 1G/10G or 2.5G/10G application range, 10nF would be a good choice, but be sure to optimize the coupling capacitor value for the specific application.

Measurements

Evaluating RXOUT+ and RXOUT-

1. Set a DC power supply to +3.3V and turn it off.
2. Connect the positive lead to V_cc post and the negative lead to GND post.
3. Connect the /EN input to GND (jumper between pin1 and pin 2 of JP2) to enable the RXOUT+ and RXOUT-output buffers.
4. For SY88083L: Do not install jumpers on JP1 and JP3.

5. For SY88073L: Connect VTHN and VTHP to GND (install jumper on JP1 and jumper between pins 1 and 2 of JP3) to turn off the crosspoint adjustment or connect VTHN to VTHREF (jumper between pin 2 and pin 3 of JP3) and apply a voltage to VTHP (JP1 open) to adjust the eye crossing (start with a voltage close to VTHREF).

6. Set the desired frequency on a pattern generator with amplitude between 5mV_PP and 1800mV_PP . Typical data patterns are 2^7-1 or 2^23-1 PRBS patterns, depending on the application. Because the inputs to the board are AC-coupled, the voltage offset of the pattern generator is not significant and can be set between GND and VCC.

7. Connect the pattern generator with differential outputs as a data source to the RXIN+ and RXIN- inputs on the SY88073L/083L evaluation board. Use matched length differential cables.
8. Turn the power supply on.
9. Observe RXOUT+ and RXOUT- outputs on a 50Ω input scope.

Adjusting Crosspoint (073L)

1. As mentioned in step 5 above, to adjust crosspoint, move the jumper on JP3 to connect VTHN to VTHREF.
2. Remove the jumper from JP1.
3. Apply a 1.25V DC voltage to TP1 and adjust it slightly to set crossing at 50%, higher or lower.

Digital Offset Correction (DOC) (083L)

The DOC circuit corrects for internal offset and may not be able to fully compensate for offset that external circuits and/or driving devices such TIA may impose at the inputs of the device.

To enable the DOC function in the SY88083L, leave JP1 open or apply a high signal to DOC_EN (pin 2 of JP1).

To disable the DOC function, install a jumper on JP1.

LOS/SD Timing Measurements

The board comes with 10nF coupling capacitors at the inputs and outputs. To minimize the effect of the input RC time constant on the signal delay from the SMA connectors to the input of the device, the caps must be replace with lower values caps (100pF or lower). Otherwise this delay may increase the measured LOS/SD assert/de-assert time significantly.

LOS Hysteresis Measurements

The SY88073L/083L evaluation board provides a potentiometer (R2) to allow for convenient adjustment of SD/LOSLVL without the need for an extra power supply. SD/LOSLVL taps off a potentiometer connected between V_CC and V_REF . V_REF is an internal reference voltage of approximately V_CC - 1.3V . So, SD/LOSLVL can be set to any voltage between V_CC and V_CC - 1.3V , as specified in the SY88073L and SY88083L datasheets.

The potentiometer creates a voltage divider. Thus the SD/LOSLVL can be calculated using Equation 1:

$$ = V _ {e c} \frac {1 . 3 \times R}{R + 1 . 5} E q. 1 $$

R is the resistance (in kΩ) of the potentiometer from V_CC to the tap at SD/LOSLVL. Follow the steps below to measure the LOS/SD hysteresis as a function of the input voltage swing at the RXIN+ and RXIN- inputs.

Minimum Input Swing Hysteresis Measurement

The minimum acceptable BER input swing for the SY88073L and SY88083L is 10mV_PP .

1. Set a DC power supply to +3.3V and turn it off. Connect the positive lead to the V_cc post and the negative lead to the GND post.
2. Connect the /EN input to GND (jumper between pin 1 and pin 2 of JP2) to enable the RXOUT+ and RXOUT-output buffers.
3. Connect a DMM or similar voltage-measurement device between the LOS_LVL pin and V_CC .
4. Connect a second DMM, or similar voltage-measurement device between the LOS output and GND. From here on, this DMM will be referred to as the LOS DMM. To use a scope instead of the LOS DMM, move the jumper from /EN-GND to /EN-SQL (from pin 1 and pin 2 to pin 2 and pin 3 of JP2), install a jumper from LOS to SQL (between pin 2 and pin 3 of JP4) to set the squelch function, and observe the output waveform (RXOUT+ and/or RXOUT−) on the scope instead of measuring LOS with DMM.
5. Connect the pattern generator with differential outputs as a data source to RXIN+ and RXIN- inputs on the SY88073L evaluation board. Use matched length differential cables.
6. Turn the power supply on.
7. Adjust the trim pot R2 so the voltage at the SD/LOSLVL pin is around 1.3V below V_CC . This sets the LOS for maximum sensitivity. At this level the LOS output should go high or low (measured with the LOS DMM), as the input voltage swing at RXIN+ and RXIN− is varied up and down around 10mV_PP .

8. Adjust the trim pot to set the sensitivity to a desired level and lower the amplitude of the input signal until LOS is asserted high, then increase the input signal until the LOS de-asserts low.

9. The hysteresis between the assert and de-assert levels can be calculated using Equation 2:

$$ \text { Hysteresis(dB) } = 2 0 \mathrm{Log} \frac {\mathrm{D} ^ {-}}{\mathrm{A} ^ {-}} \tag {Eq.2} $$

Where:

LOS-D is the LOS de-assert input level and LOS-A is the LOS assert input level.

This hysteresis should be >3dB, and typically 4dB.

Evaluation Board Schematics ^(1)

SY88073L JP2 3 SQL JP6 1 JP5 2 VCC C7 0.1μF C8 0.01μF C9 0.1μF C5 0.01μF 500Ω J1 RXIN+ C3 0.01μF 500Ω RXIN+ C4 0.01μF 500Ω RXIN- GND GND VTHN VTH_REF VCC VCCOUT+ VCC C6 0.01μF 500Ω VCC C10 0.01μF C11 0.1μF R1 5kΩ R2 20kΩ C12 0.1μF C13 0.1μF JP3 3 2 1 JP4 3 2 1 C12 0.1μF C11 0.1μF C12 0.1μF C13 0.1μF C12 0.1μF C12 0.1μF C13 0.1μF C12 0.1μF C13 0.1μF C12 0.1μF

SY88083L JP2 3 SQL JP6 1 C7 0.1μF JAM SD/LOS_SEL TEST JP5 1 VCC C8 0.01μF C9 0.1μF C4 0.01μF GND DOC_EN RXIN+ RXIN- GND NC SD/LOS SD/LOS/VL VCC C5 0.01μF 500 RXOUT+ RXOUT- 500 C6 0.01μF VCC C10 0.01μF C11 0.1μF R1 5kΩ R2 20kΩ JP3 3 2 1 C13 0.1μF JP4 3 2 1 SQL C12 0.1μF JP1 2 1 C3 0.01μF C4 0.01μF J1 RXIN+ J2 RXIN- J3 RXOUT+ J4 RXOUT- VCC PS_VCC TP1 C1 10μF C2 0.1μF GROUND TP2

Bill of Materials

Item	Part Number	Manufacturer	Description	Qty.
C3-6, C8, C10	C1005X7R1C103K050BC	TDK^(2)	CAP CER 0.01μF 16V 10% X7R 0402	6
C7, C9, C11-C13	C1005X7R1C104K050BC	TDK	CAP CER 0.1μF 16V 10% X7R 0402	4
C2 C1608X7R1E104K080AA		TDK	CAP CER 0.1μF 16V 10% X7R 0603	1
C1	C3216X5R0J106K/1.60	TDK	CAP CER 10UF 6.3V 10% X5R 1206	1
JP1-JP6	TSW-103-07-S-S	Samtec (3) 0.1mil	Center through hole terminal strip 5
R1	CRCW06035111F	Vishay^(4)	5kΩ, 10%, 1/16W Resistor SMD, Size 0603	1
R2	3269W-1-153G	Bourns (5)	20kΩ Trimpot	1
TP2	5011	Keystone^(6)	Color Coded PCB test point, Black	1
TP1	5010	Keystone	Color Coded PCB test point, Red	1
J1-J4	32K243-40ML5	Rosenberger^(7)	End Launch SMA	4
U1	SY88073L/083L	Micrel, Inc. (8)	1G to 12.5G Limiting Post Amplifiers with Programmable Decision Threshold (073L) Digital Offset Correction (083L)	1

Notes:

1. TDK: www.tdk.com.
2. Samtec: www.samtec.com.
3. Vishay: www.vishay.com
4. Bourns, Inc.: www.bourns.com.
5. Keystone Electronics Corp.: www.keyelco.com.
6. Rosenberger: www.rosenberger.com.
7. Micrel, Inc.: www.micrel.com.

TCG Support

Hotline: [phone]

Email Support: [e-mail]

Application Hints and Notes

For application notes about high-speed termination on high-bandwidth FOM and clock synthesizer products, SONET jitter measurement, and other TCG products, go to Micrel's website at: http://www.micrel.com.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL [phone] FAX [phone] WEB http://www.micrel.com

Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel's terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

© 2014 Micrel, Incorporated.

Revision History

Date	Change Description/Edits by:	Rev.
2/26/14	Initial release of evaluation board documentation.	1.0