SN74LV166ADR - Electronic component TEXAS INSTRUMENTS - Free user manual and instructions

USER MANUAL SN74LV166ADR TEXAS INSTRUMENTS

●2-V to 5.5-V V cc Operation
●Max t pd of 10.5 ns at 5 V
●Typical V OLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25^
●Typical V OHV (Output VOH Undershoot)

2.3 V at VCC = 3.3 V, TA = 25°C
●I off Supports Partial-Power-Down-Mode Operation
●Synchronous Load

SN54LV166A...J OR W PACKAGE
SN74LV166A ... D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)

SER 1 16 VCC A 2 15 SH/LD B 3 14 H C 4 13 QH D 5 12 G CLK INH 6 11 F CLK 7 10 E GND 8 9 CLR

●Direct Overriding Clear
●Parallel-to-Serial Conversion
●Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
●ESD Protection Exceeds JESD 22

• 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)

SN54LV166A...FK PACKAGE
(TOP VIEW)

A SER NC VCC SH/LD B 4 3 2 1 2 0 1 9 C 5 NC 6 D 7 CLK INH 8 9 1 0 1 1 2 1 3 CLK GND NC CLR E QH NC G F

NC - No internal connection

description/ordering information

The 'LV166A devices are 8-bit parallel-load shift registers, designed for 2-V to 5.5-V V _CC operation.

ORDERING INFORMATION

T_A	PACKAGE^†		ORDERABLEPART NUMBER	TOP-SIDEMARKING
-40°C to 85°C	SOIC - D	Tube of 40 SN7	4LV166AD	LV166A
		Reel of 2500 SN7	74LV166ADR
	SOP - NS Reel of	2000 SN74LV1	6ANSR 74LV166A
	SSOP - DB	Reel of 2000	SN74LV166ADBR	LV166A
	TSSOP - PW	Tube of 90 SN7	4LV166APW	LV166A
		Reel of 2000 SN7	74LV166APWR
		Reel of 250	SN74LV166APWT
	TVSOP - DGV	Reel of 2000	SN74LV166ADGVR	LV166A
-55°C to 125°C	CDIP - J	Tube of 25	SNJ54LV166AJ	SNJ54LV166AJ
	CFP - W	Tube of 150	SNJ54LV166AW	SNJ54LV166AW
	LCCC - FK	Tube of 55	SNJ54LV166AFK	SNJ54LV166AFK

†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

description/ordering information (continued)

The 'LV166A parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high. CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.

These devices are fully specified for partial-power-down applications using I_off . The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

FUNCTION TABLE

INPUTS						OUTPUTS
						INTERNAL		Q_H
SH/LD—CLK INH CLK SER PARALLEL A...H						Q_A	Q_B
LXXXXXLLL
HX	L	L	X		X	Q	A0	Q_B0
H	L	L	↑	X	a...h		a	b
H	H	L	↑	H	X		H	Q_An
H	H	L	↑	L	X		L	Q_An
HXH↑XX	Q						A0	Q_B0

logic diagram (positive logic)

graph TD
    A["SH/LD 15"] --> B["AND Gate"]
    C["SER 1"] --> B
    B --> D["AND Gate"]
    E["CLK INH 6/7"] --> F["AND Gate"]
    G["CLK 9"] --> F
    F --> H["AND Gate"]
    I["A"] --> J["AND Gate"]
    K["B"] --> L["AND Gate"]
    M["C"] --> N["AND Gate"]
    O["D"] --> P["AND Gate"]
    Q["E"] --> R["AND Gate"]
    S["F"] --> T["AND Gate"]
    U["G"] --> V["AND Gate"]
    W["H"] --> X["AND Gate"]
    Y["13"] --> Z["QH"]
    style A fill:#f9f,stroke:#333
    style C fill:#f9f,stroke:#333
    style E fill:#f9f,stroke:#333
    style Q fill:#f9f,stroke:#333
    style I fill:#ccf,stroke:#333
    style G fill:#ccf,stroke:#333
    style H fill:#ccf,stroke:#333
    style U fill:#ccf,stroke:#333
    style V fill:#ccf,stroke:#333
    style Z fill:#ccf,stroke:#333

typical clear, shift, load, inhibit, and shift sequence

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage range, V_CC -0.5 V to 7 V

Input voltage range, V_I (see Note 1) -0.5 V to 7 V

Output voltage range applied in high or low state, V_O (see Notes 1 and 2) -0.5 V to V CC + 0.5 V.....

Voltage range applied to any output in the power-off state, V_O (see Note 1) -0.5 V to 7 V.....

Input clamp current, I_IK(V_I < 0) -20 mA

Output clamp current, I_OK ( V_O < 0 ) -50 mA

Continuous output current, I_O ( V_O=0 to V_CC ) ±25 mA

Continuous current through V_CC or GND ± 50mA

Package thermal impedance, _JA (see Note 3): D package 73^ / W

DB package 82°C/W

DGV package 120°C/W

NS package 64°C/W

PW package 108°C/W

Storage temperature range, T_stg -65^ to 150^

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

1. This value is limited to 5.5 V maximum.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 4)

		SN54LV166A SN74	LV166A	UNIT
		MIN MAX MIN MAX
V_CC Supply voltage 2 5.5 2 5.5 V
V_IH High-level input voltage	V_CC=2 V 1.5 1.5			V
	V_CC=2.3 V to 2.7 V V	CC×0.7 V	CC×0.7
	V_CC=3 V to 3.6 V	V_CC×0.7 V	CC×0.7
	V_CC=4.5 V to 5.5 V V	CC×0.7 V	CC×0.7
V_IL Low-level input voltage	V_CC=2 V 0.5 0.5			V
	V_CC=2.3 V to 2.7 V V	CC×0.3 V	CC×0.3
	V_CC=3 V to 3.6 V	V_CC×0.3 V	CC×0.3
	V_CC=4.5 V to 5.5 V V	CC×0.3 V	CC×0.3
V_I Input voltage		0 5.5 0 5.5 V
V_O Output voltage		0 V_CC	0 V_CC	V
I_OH High-level output current	V_CC=2 V	-50	-50	μA
	V_CC=2.3 V to 2.7 V	-2	-2	mA
	V_CC=3 V to 3.6 V	-6	-6
	V_CC=4.5 V to 5.5 V	-12	-12
I_OL Low-level output current	V_CC=2 V	50	50	μA
	V_CC=2.3 V to 2.7 V	2	2	mA
	V_CC=3 V to 3.6 V	6	6
	V_CC=4.5 V to 5.5 V	12	12
t/ v Input transition rise or fall rate	V_CC=2.3 V to 2.7 V	200	200	ns/V
	V_CC=3 V to 3.6 V	100	100
	V_CC=4.5 V to 5.5 V	20	20
TA Operating free-air temperature		-55 125	-40 85	°C

NOTE 4: All unused inputs of the device must be held at V_CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS	V_CC	SN54LV166A			SN74LV166A			UNIT
			MIN	TYP	MAX	MIN	TYP	MAX
V_OH	I_OH=-50 μA	2 V to 5.5 V	V_CC-0.1			V_CC-0.1			V
	I_OH=-2 mA	2.3 V	2			2
	I_OH=-6 mA	3 V	2.48			2.48
	I_OH=-12 mA	4.5 V	3.8			3.8
V_OL	I_OL=50 μA	2 V to 5.5 V			0.1			0.1	V
	I_OL=2 mA	2.3 V			0.4			0.4
	I_OL=6 mA	3 V			0.44			0.44
	I_OL=12 mA	4.5 V			0.55			0.55
I_I	V_I=5.5 V or GND	0 to 5.5 V			±1			±1	μA
I_CC	V_I=V_CC or GND, I_O=0	5.5 V			20			20	μA
I_off	V_I or V_O=0 to 5.5 V	0			5			5	μA
C_i	V_I=V_CC or GND	3.3 V			1.6			1.6	pF

SCLS456C - FEBRUARY 2001 - REVISED APRIL 2005

timing requirements over recommended operating free-air temperature range, V_CC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)

		T_A=25°C SN54LV166A SN74LV166A			UNIT
		MIN MAX MIN MAX MIN MAX
t_w	Pulse duration	low 8 9 9
		CLK high or low	8.5 9 9
t_su	Setup time	CLK INH before CLK↑ 7 7 7
		Data before CLK↑ 6.5 8.5 8.5
		SH/LD before CLK↑ 7 8.5 8.5
		SER before CLK↑ 8.5 9.5 9.5
		↑ inactive before CLK↑	6	7	7
t_h	Hold time	Data after CLK↑	-0.5	0	0

timing requirements over recommended operating free-air temperature range, V_CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)

		T_A=25°C SN	54LV166A SN74	LV166A	UNIT
		MIN MAX MIN	MAX MIN MAX
t_w	Pulse duration	low 6 7 7			ns
		CLK high or low	6 7 7
t_su	Setup time	CLK INH before CLK↑ 5 5 5			ns
		Data before CLK↑	5 6 6
		SH/LD before CLK↑ 5 6 6
		SER before CLK↑	5 6 6
		↑ inactive before CLK↑	4	4	4
t_h	Hold time	Data after CLK↑	0	0	0

timing requirements over recommended operating free-air temperature range, V_CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

		T_A=25°C SN54LV166A SN74LV166A			UNIT
		MIN MAX MIN MAX MIN4 MAX
t_w	Pulse duration	low 5 5 5			ns
		CLK high or low	4 4 4
t_su	Setup time	CLK INH before CLK↑	3.5 3.5 3.5		ns
		Data before CLK↑ 4.5 4.5 4.5
		SH/LD before CLK↑ 4 4 4
		SER before CLK↑	4 4 4
		↑ inactive before CLK↑	3.5	3.5	3.5
t_h	Hold time	Data after CLK↑	1	1	1

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

TEXAS

INSTRUMENTS

switching characteristics over recommended operating free-air temperature range, V_CC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	LOADCAPACITANCE	T_A=25°C SN54L	V166A SN74LV	66A	UNIT
				MIN TYP MAX MIN MAX	MAX MIN MAX
f_max			C_L=15 pF 50^*	105* 45* 45			MHz
			C_L=50 pF 40	30 35 35
t_PHL		Q_H	C_L=15 pF	8.8* 16* 1* 18*	1 18		ns
t_pd	CLK			9.2* 19.8* 1*	22* 1 22
t_PHL		Q_H	C_L=50 pF	11.3 19.5	1 22 1 22		ns
t_pd	CLK			11.8 23.3	1 26 1 26

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

switching characteristics over recommended operating free-air temperature range, V_CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	LOADCAPACITANCE	T_A=25°C SN54LV166A SN74LV166A			UNIT
				MIN TYP MAX MIN MAX MIN MAX
f_max			C_L=15 pF 65^*	150* 55* 55			MHz
			C_L=50 pF 60	120 50 50
t_PHL		Q_H	C_L=15 pF	6.3* 12.5* 1*	15*	1 15	ns
t_pd	CLK			6.6* 15.4* 1*	18*	1 18
t_PHL		Q_H	C_L=50 pF	7.9 16.3	1 18.5	1 18.5	ns
t_pd	CLK			8.3 18.9	1 21.5	1 21.5

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

switching characteristics over recommended operating free-air temperature range, V_CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	LOADCAPACITANCE	T_A=25°C SN54L		V166A SN74LV ^-1		66A		UNIT
				MIN TYP MAX MIN MAX
f_max			C_L=15 pF	110* 205* 90* 90						MHz
			C_L=50 pF 95	160 85 85
t_PHL		Q_H	C_L=15 pF	4.6*	8.6*	1* 10*	1 10			ns
t_pd	CLK			4.8*	9.9*	1* 11.5*	1	11.5
t_PHL		Q_H	C_L=50 pF	5.7 10.6		1 12	1 12	2		ns
t_pd	CLK			6.1	11.9	1	13.5	1	13.5

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

operating characteristics, T_A = 25^

PARAMETER		TEST CONDITIONS	VCC	TYP	UNIT
Cpd	Power dissipation capacitance	CL=50 pF, f=10 MHz	3.3 V	39.1	pF
			5 V	44.5

PARAMETER MEASUREMENT INFORMATION

From Output Under Test Test Point CL (see Note A) LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS CL (see Note A) RL = 1 kΩ S1 VCC Open GND LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS

TEST S1
t_PLH/t_PHL	Open
t_PLZ/t_PZL	V_CC
t_PHZ/t_PZH	GND
Open Drain	V_CC

Input 50% VCC tw 50% VCC VCC 0 V VOLTAGE WAVEFORMS PULSE DURATION

Timing Input 50% VCC VCC 0 V tsu th Data Input 50% VCC 50% VCC VCC 0 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

Output Control 50% VCC 50% VCC VCC 0 V tPZL tPLZ Output Waveform 1 S1 at VCC (see Note B) 50% VCC VOL + 0.3 V VOL tPZH tPHZ Output Waveform 2 S1 at GND (see Note B) 50% VCC VOH - 0.3 V VOH =0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING

NOTES: A. C L includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z O = 50 Ω, t r ≤ 3 ns, t _f ≤ 3 ns.

D. The outputs are measured one at a time, with one input transition per measurement.

E. tPLZ and tPHZ are the same as t_dis .

F. tPZL and tPZH are the same as ten.

G. tPHL and tPLH are the same as t_pd .

H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

PACKAGING INFORMATION

Orderable Device Status(1)		Package Type	Package Drawing	Pins	Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4-5)	Samples
SN74LV166AD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV166A											Samples
SN74LV166ADBR	ACTIVE	SSOP	DB	16	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	LV166A	Samples
SN74LV166ADG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV166A											Samples
SN74LV166ADGVR	ACTIVE	TVSOP	DGV	16	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	LV166A	Samples
SN74LV166ADR	ACTIVE	SOIC	D	16	2500	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	LV166A	Samples
SN74LV166ANSR	ACTIVE	SO	NS	16	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	74LV166A	Samples
SN74LV166APW	ACTIVE	TSSOP	PW	16	90	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	LV166A	Samples
SN74LV166APWR	ACTIVE	TSSOP	PW	16	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	LV166A	Samples
SN74LV166APWRG4	ACTIVE	TSSOP	PW	16	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	LV166A	Samples

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "\~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

Package Drawing

Pins

SPQ Reel

Diameter (mm)

Reel Width W1 (mm)

A0 (mm)

B0 (mm)

K0 (mm)

P1 (mm)

W (mm)

Pin1 Quadrant

SN74LV166ADBR SSOP DB 16

2000 330.0

16.4

8.35 6.6 2.4

12.0 16.0 Q1

SN74LV166ADGVR TVSOP DGV

16 2000 3

30.0 1

2.4 6.8 4.0

1.6 8.0 12.0 Q1

SN74LV166ADR SOIC D 16 250

0 330.0

16.4 6.5

10.3 2.1 8

16.0 Q1

SN74LV166ANSR SO

NS 16 2000

330.0 16.4 8.2

10.5 2.5 1

16.0 Q1

SN74LV166APWR

TSSOP PW

16 2000

330.0 12.4

6.9 5.6 1

6 8.0 12.0

Q1

TAPE AND REEL BOX DIMENSIONS W L

*All dimensions are nominal

Device	Package Type	Package Drawing	Pins	SPQ	Length (mm)	Width (mm)	Height (mm)
SN74LV166ADBR SSOP DB 16 2000 853.0	449.0 35.0
SN74LV166ADGVR TVSOP DGV 16 2000 853.0	449.0 35.0
SN74LV166ADR SOIC D 16 2500	340.5 336.1 32.0
SN74LV166ANSR	SO	NS 16 2000	853.0	449.0 35.0
SN74LV166APWR	TSSOP	PW	16	2000	853.0	449.0	35.0

TUBE

T - Tube height L - Tube length W-Tube width B - Alignment groove width

*All dimensions are nominal

Device	Package Name	Package Type	Pins	SPQ	L (mm)	W (mm)	T (μm)	B (mm)
SN74LV166AD D SO	C 16 40 507 8 3940	4.32
SN74LV166ADG4 D SO	DIC 16 40 507 8 3940	4.32
SN74LV166APW PW	TSSOP 16 90 530 1	0.2 3600 3.5

DGV (R-PDSO-G\*\*) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

DIM\PINS **	14		20		382416	48	56
A MAX	3,70		5,10	5,103,70	7,90	9,80	11,40
A MIN	3,50	3,50	4,90	4,90	7,70	9,60	11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 per side.
D. Falls within JEDEC: 24/48 Pins - MO-153

14/16/20/56 Pins - MO-194

D (R-PDSO-G16)
PLASTIC SMALL OUTLINE

0.394 (10,00) 0.386 (9,80) 16 9 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,80) Pin 1 Index Area 1 8 0.050 (1,27) 0.020 (0,51) 0.012 (0,31) ⊕ 0.010 (0,25) M 0.069 (1,75) Max 0.010 (0,25) 0.004 (0,10) Gcuge Plane 0.010 (0,25) 0.005 (0,13) 0'-8" Seating Plane 0.010 (0,25) 0.050 (1,27) 0.016 (0,40) 4040047-6/M 06/11

NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.006 (0,15) each side.
Body width does not include interlead flash. Interlead flash shall not exceed 0.017 (0,43) each side.
E. Reference JEDEC MS-012 variation AC.

D (R-PDSO-G16)

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate designs.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

SMALL OUTLINE PACKAGE

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

SMALL OUTLINE PACKAGE

16X (1.5) 1 16X (0.45) 14X (0.65) 8 (5.8) SYMM (R0.05) TYP 16 SYMM 9

LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN SCALE: 10X

SOLDER MASK OPENING METAL EXPOSED METAL 0.05 MAX ALL AROUND

NON-SOLDER MASK DEFINED (PREFERRED)

METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL 0.05 MIN ALL AROUND

SOLDER MASK DEFINED
SOLDER MASK DETAILS

4220204/A 02/2017

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SMALL OUTLINE PACKAGE

16X (1.5) 1 16X (0.45) SYMM (R0.05) TYP 16 SYMM 14X (0.65) 8 (5.8)

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

SMALL OUTLINE PACKAGE

A 8.2 TYP 7.4 PIN 1 INDEX AREA 16 14X 0.65 6.5 5.9 NOTE 3 2X 4.55 8 9 16X 0.38 0.22 B 5.6 5.0 NOTE 4 ⊕ 0.1@ A B

C 0.1 C SEATING PLANE

0.25 0.09 SEE DETAIL A

GAGE PLANE 0.25 0°-8° 0.95 0.55 2 MAX 0.05 MIN

DETAIL A TYPICAL

4220763/A 05/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. Reference JEDEC registration MO-150.

SMALL OUTLINE PACKAGE

16X (1.85) SYMM (0.05) TYP 16 16X (0.45) 14X (0.65) 8 (7) 9 SYMM

LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN SCALE: 10X

SOLDER MASK OPENING METAL EXPOSED METAL 0.05 MAX ALL AROUND

NON-SOLDER MASK DEFINED (PREFERRED)

METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL 0.05 MIN ALL AROUND

SOLDER MASK DETAILS

4220763/A 05/2022

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SMALL OUTLINE PACKAGE

16X (1.85) 1 16X (0.45) SYMM (R0.05) TYP 16 14X (0.65) 8 SYMM 9 (7)

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220763/A 05/2022

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

MECHANICAL DATA

NS (R-PDSO-G\*\*)

PLASTIC SMALL-OUTLINE PACKAGE

14-PINS SHOWN

1,27 14 0,51 0,35 Ø 0,25① 8 5,60 5,00 8,20 7,40 1 7 A

0,15 NOM Gage Plane 0,25 0°-10° 1,05 0,55

2,00 MAX 0,15 0,05

Seating Plane 0.10

DIM\PINS **	14	16	20	24
A MAX	10,50	10,50	12,90	15,30
A MIN	9,90	9,90	12,30	14,70

4040062/C 03/03

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.

SOP

4220735/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

SOP

16X (1.85) 1 16X (0.6) SYMM SEE DETAILS 16 SYMM 14X (1.27) 8 (R0.05) TYP 9 (7)

LAND PATTERN EXAMPLE SCALE:7X

METAL SOLDER MASK OPENING 0.07 MAX ALL AROUND

NON SOLDER MASK DEFINED

SOLDER MASK OPENING METAL 0.07 MIN ALL AROUND

SOLDER MASK DEFINED
SOLDER MASK DETAILS

4220735/A 12/2021

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SOP

16X (1.85) 1 16X (0.6) 14X (1.27) 8 (R0.05) TYP SYMM 16 SYMM 9 (7)

SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X

4220735/A 12/2021

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

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