SN74LV125APWR - Electronic component TEXAS INSTRUMENTS - Free user manual and instructions

USER MANUAL SN74LV125APWR TEXAS INSTRUMENTS

SN74LV125A Quadruple Bus Buffer Gates With 3-State Outputs

1 Features

• 2-V to 5.5-V V CC Operation
• Max t pd of 6 ns at 5 V
• Typical V OLP (Output Ground Bounce) < 0.8 V at V CC = 3.3 V, T A = 25°C
- Typical V OHV (Output V OH Undershoot)

2.3 V at V CC = 3.3 V, T A = 25°C
• Support Mixed-Mode Voltage Operation on All Ports
- I_off Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22 - 4000-V Human-Body Model - 200-V Machine Model - 2000-V Charged-Device Model

2 Applications

• Flow Meters
  • Solid State Drives (SSDs): Enterprise
  • Power Over Ethernet (PoE)
  • Programmable Logic Controllers
  • Motor Drives and Controls
  • Electronic Points of Sale

3 Description

The SN74LV125A quadruple bus buffer gate is designed for 2-V to 5.5-V Vcc operation.

Device Information

PART NUMBER(1)	PACKAGE BODY SIZE (NOM)
SN74LV125A	DGV (TVSOP, 14) 3.60 mm x 4.40 mm
	D (SOIC, 14) 8.65 mm × 3.90 mm
	NS (SO, 14) 10.20 mm x 5.30 mm
	DB (SSOP, 14) 6.20 mm x 5.30 mm
	PW (TSSOP, 14) 5.00 mm x 4.40 mm

(1) For all available packages, see the orderable addendum at the end of the data sheet.

1OE 1A 1Y 2OE 2A 2Y

30E 3A 3Y 40E 4A 4Y

Simplified Schematic

Table of Contents

1 Features....1
2 Applications....1
3 Description....1
4 Revision History....2
5 Pin Configuration and Functions....3 Pin Functions....3
6 Specifications....4

6.1 Absolute Maximum Ratings.... 4
6.2 ESD Ratings....4
6.3 Recommended Operating Conditions....5
6.4 Thermal Information....5
6.5 Electrical Characteristics....6
6.6 Switching Characteristics, V_CC = 2.5 V ± 0.2 V ....6
6.7 Switching Characteristics, V_CC = 3.3 V ± 0.3 V ......6
6.8 Switching Characteristics, V_CC = 5 ~V ± 0.5 ~V ......7
6.9 Noise Characteristics....7
6.10 Operating Characteristics....7
6.11 Typical Characteristics....7

7 Parameter Measurement Information...... 8

8 Detailed Description....9

8.1 Overview....9
8.2 Functional Block Diagram....9
8.3 Feature Description....9
8.4 Device Functional Modes....9

9 Application and Implementation.... 10

9.1 Application Information.... 10
9.2 Typical Application.... 10

10 Power Supply Recommendations....11

11 Layout....12

11.1 Layout Guidelines.... 12
11.2 Layout Example.... 12

12 Device and Documentation Support....12

12.1 Related Links.... 12
12.2 Trademarks....12
12.3 Electrostatic Discharge Caution....12
12.4 Glossary....12

13 Mechanical, Packaging, and Orderable Information.... 12

4 Revision History

Changes from Revision N (January 2015) to Revision O (May 2022) Page

- Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standards....4

Changes from Revision M (December 2014) to Revision N (January 2015) Page

• Added T _j spec to Absolute Maximum Ratings table.... 4
• Added text to Overview section 9

Changes from Revision L (April 2005) to Revision M (December 2014) Page

• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.... 1
• Deleted Ordering Information table....1
• Changed MAX operating temperature to 125^ in Recommended Operating Conditions table. 5

5 Pin Configuration and Functions

SN74LV125A . . . D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW)

1OE 1 14 VCC 1A 2 13 4OE 1Y 3 12 4A 2OE 4 11 4Y 2A 5 10 3OE 2Y 6 9 3A GND 7 8 3Y

SN74LV125A...RGY PACKAGE (TOP VIEW)

OE 10E VCC 1 14 1A 2 1Y 3 2OE 4 2A 5 2Y 6 7 8 ND (5) 3Y 4OE 4A 4Y 3OE 3A

Pin Functions

PIN		TYPE(1)	DESCRIPTION
NO. NAME
1 1OE I Output Enable 1, Active Low
2 1A I 1A Input
3 1Y O 1Y Output
4 2OE I Output Enable 2, Active Low
5 2A I 2A Input
6 2Y O 2Y Output
7 GND — Ground Pin
8 3Y O 3Y Output
9 3A I 3A Input
10	3OE I Output Enable 3, Active Low
11 4Y O 4Y Output
12	4A I 4A Input
13	4OE I Output Enable 4, Active Low
14	VCC	— Power Pin

(1) Signal Types: I = Input, O = Output, I/O = Input or Output.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

			MIN(1)	MAX	UNIT
V_CC	Supply voltage -0.5 7 V
V_I	Input voltage range(2)		-0.5 7 V
V_O	Voltage range applied to any output in the high-impedance or power-off state(2)		-0.5 7 V
V_O	Output voltage range(2)(3)		-0.5 V	_CC + 0.5 V
I_IK	Input clamp current V	_1 < 0 -20 mA
I_OK	Output clamp current V	_o < 0 -50 mA
I_O	Continuous output current V	_o = 0 to V_CC		±35 mA
	Continuous current through V_CC or GND ±70 mA
T_j	Junction temperature 150 °C
T_stg	Storage temperature -65	150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 5.5-V maximum.

6.2 ESD Ratings

		MAX	UNIT
V_(ESD) Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins ^(1)	±4000	V
	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins ^(2)	±2000
	Machine Model (MM)	±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) ^(1)

			SN74LV125A	UNIT
			MIN MAX
V_CC	Supply voltage 2 5.5 V
V_IH	High-level input voltage	V_CC=2 V 1.5		V
		V_CC=2.3 V to 2.7 V V	cc×0.7
		V_CC=3 V to 3.6 V V	cc×0.7
		V_CC=4.5 V to 5.5 V V	cc×0.7
V_IL	Low-level input voltage	V_CC=2 V 0.5		V
		V_CC=2.3 V to 2.7 V V	cc×0.3
		V_CC=3 V to 3.6 V V	cc×0.3
		V_CC=4.5 V to 5.5 V V	cc×0.3
V_I	Input voltage 0 5.5 V
V_O	Output voltage	High or low state 0 V	cc	V
		3-state 0 5.5
I_OH	High-level output current	V_CC=2 V -50 A
		V_CC=2.3 V to 2.7 V	-2	mA
		V_CC=3 V to 3.6 V	-8
		V_CC=4.5 V to 5.5 V	-16
I_OL	Low-level output current	V_CC=2 V	50	μA
		V_CC=2.3 V to 2.7 V	2	mA
		V_CC=3 V to 3.6 V	8
		V_CC=4.5 V to 5.5 V	16
t/ v	Input transition rise or fall rate	V_CC=2.3 V to 2.7 V	200	ns/V
		V_CC=3 V to 3.6 V	100
		V_CC=4.5 V to 5.5 V	20
T_A	Operating free-air temperature		-40 125	°C

(1) All unused inputs of the device must be held at V_CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004).

6.4 Thermal Information

THERMAL METRIC(1)		SN74LV125A							UNIT
		D	DB	DGV	N	NS	PW	RGY
		14 PINS
R_ JA	Junction-to-ambient thermal resistance	92.7	105.0	127.6	89.2	89.6	119.8	55.0	°C/W
R_ JC(top)	Junction-to-case (top) thermal resistance	54.1	57.5	50.7	47.0	47.2	48.6	67.4
R_ JB	Junction-to-board thermal resistance	47.0	52.3	60.5	47.9	48.4	61.5	31.0
_JT	Junction-to-top characterization parameter	18.9	19.1	6.1	14.1	14.0	5.7	2.6
_JB	Junction-to-board characterization parameter	46.7	51.8	59.8	47.5	48.1	61.0	31.1
R_ JC(bot)	Junction-to-case (bottom) thermal resistance	N/A	N/A	N/A	N/A	N/A	N/A	11.6

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS V		cc	T_A =25°C-40°C to 85°C-40°C to 125°C			UNIT
			MIN TYP MAX MIN MAX MAX MIN MAX
V_OH	I_OH =-50 μA	2 V to 5.5 V	V_CC -0.1 V	cc-0.1 V	cc-0.1	V
	I_OH =-2 mA 2.3 V 2 2 2
	I_OH =-8 mA 3 V 2.48 2.48		2.48
	I_OH =-16 mA	4.5 V	3.8	3.8	3.8
V_OL	I_OL =50 μA	2 V to 5.5 V	0.1	0.1	0.1	V
	I_OL =2 mA	2.3 V	0.4	0.4	0.4
	I_OL =8 mA	3 V	0.44	0.44	0.44
	I_OL =16 mA	4.5 V	0.55	0.55	0.55
I_I	V_I =5.5 V or GND	0 to 5.5 V	±1	±1	±1	μA
I_OZ	V_O = V_CC or GND	5.5 V	±5	±5	±5	μA
I_CC	V_I = V_CC or GND, I_O =0	5.5 V	20	20	20	μA
I_off	V_I or V_O =0 to 5.5 V	0	5	5.5 μA
C_I	V_I = V_CC or GND	3.3 V	1.6			pF
		5 V	1.6

6.6 Switching Characteristics, V_CC = 2.5 V ± 0.2 V

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	LOADCAPACITANCE	T_A =25°C			-40°C to 85°C		-40°C to 125°C		UNIT
				MIN	TYP	MAX	MIN	MAX	MIN	MAX
t_pd	A	Y	C_L =15 pF		6.8(1)	13(1)	1	15.5	1	17	ns
t_en	OE	Y			7(1)	13(1)	1	15.5	1	17
t_dis	OE	Y			5.1(1)	14.7(1)	1	17	1	18
t_pd	A	Y	C_L =50 pF		8.7	16.5	1	18.5	1	20	ns
t_en	OE	Y			8.8	16.5	1	18.5	1	20
t_dis	OE	Y			7.3	18.2	1	20.5	1	21.5
t_sk(o)						2		2		2

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.

6.7 Switching Characteristics, V_CC = 3.3 V ± 0.3 V

over recommended operating free-air temperature range(unless otherwise noted) (see Figure 7-1)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	LOADCAPACITANCE	T_A =25°C			-40°C to 85°C		-40°C to 125°C		UNIT
				MIN	TYP	MAX	MIN	MAX	MIN	MAX
t_pd	A	Y	C_L =15 pF		4.8(1)	8(1)	1	9.5	1	11	ns
t_en		Y			4.8(1)	8(1)	1	9.5	1	10.5
t_dis		Y			4.1(1)	9.7(1)	1	11.5	1	12.5
t_pd	A	Y	C_L =50 pF		6.1	11.5	1	13	1	14.5	ns
t_en		Y			6.2	11.5	1	13	1	14
t_dis		Y			5.5	13.2	1	15	1	16
t_sk(o)						1.5		1.5		1.5

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.

6.8 Switching Characteristics, V_CC = 5 V ± 0.5 V

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	LOADCAPACITANCE	T_A =25°C-40°C to 85°C-40°C to 125°C						UNIT
				MIN TYP MAX MIN MAX MIN MAX
t_pd	A	Y	C_L =15 pF	3.4(1)	5.5(1)		16.517.5			ns
t_en	Y 3.4			(1)	5.1(1)		161	7
t_dis	Y 3.2			(1)	6.8(1)		181	9
t_pd	A	Y	C_L =50 pF	4.3	7.5		18.519.5			ns
t_en	Y			4.4	7.1181		9
t_dis		Y		4	8.8		110	1	11
t_sk(o)						1	1		1

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.

6.9 Noise Characteristics

$$ V _ {C C} = 3. 3 \mathrm{V}, C _ {L} = 5 0 \mathrm{pF}, T _ {A} = 2 5 ^ {\circ} \mathrm{C} $$

PARAMETER^(1)		SN74LV125A			UNIT
		MIN	TYP	MAX
V_OL(P)	Quiet output, maximum dynamic V_OL		0.4	0.8	V
V_OL(V)	Quiet output, minimum dynamic V_OL		-0.3	-0.8	V
V_OH(V)	Quiet output, minimum dynamic V_OH		3		V
V_IH(D)	High-level dynamic input voltage	2.31			V
V_IL(D)	Low-level dynamic input voltage			0.99	V

(1) Characteristics are for surface-mount packages only.

6.10 Operating Characteristics

$$ \mathrm{T} _ {\mathrm{A}} = 2 5 ^ {\circ} \mathrm{C} $$

PARAMETER		TEST CONDITIONS	V_CC	TYP	UNIT
C_pd	Power dissipation capacitance	Outputs enabled	C_L = 50 pF, f = 10 MHz	3.3 V	15.5
				5 V	17.6

6.11 Typical Characteristics

Figure 6-1. TPD vs Temperature

Figure 6-2. TPD vs V_CC at 25^

7 Parameter Measurement Information

7.1

TEST S1
tPLH/tPHL	Open
tPLZ/tPZL	VCC
tPHZ/tPZH	GND
Open Drain	VCC

NOTES: A. C L includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z O = 50 Ω, t F ≤ 3 ns, t _F ≤ 3 ns.

D. The outputs are measured one at a time, with one input transition per measurement.

E. tPLZ and tPHZ are the same as t_dis .

F. tPZL and tPZH are the same as t_en .

G. tPHL and tPLH are the same as t_pd .

H. All parameters and waveforms are not applicable to all devices.

Figure 7-1. Load Circuit And Voltage Waveforms

8 Detailed Description

8.1 Overview

The SN74LV125A quadruple bus buffer gate is designed for 2-V to 5.5-V Vcc operation.

These devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, tie to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

8.2 Functional Block Diagram

1OE 1A 1Y 2OE 2A 2Y

3OE 3A 3Y 4OE 4A 4Y

Figure 8-1. Logic Diagram (Positive Logic)

8.3 Feature Description

- Wide operating voltage range

- Operates from 2 V to 5.5 V

- Allows down-voltage translation

- Inputs accept voltages to 5.5 V

- I_off Feature

– Supports Live Insertion, Partial Power-Down Mode, and Back-Drive Protection

8.4 Device Functional Modes

Table 8-1. Function Table (Each Buffer)

INPUTS(1)		OUTPUT(2)Y
OE	A
LHH
LLL
HXZ

(1) H = High Voltage Level, L = Low Voltage Level, X = Don't Care
(2) H = Driving High, L = Driving Low, Z = High Impedance State

9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SN74LV125A is a low-drive CMOS device that can be used for a multitude of bus interface type applications where output ringing is a concern. The low drive and slow edge rates minimize overshoot and undershoot on the outputs. The inputs are 5.5-V tolerant at any valid V_CC , making it ideal for translating down to V_CC .

9.2 Typical Application

graph LR
    A["5-V system"] --> B["μC or System Logic"]
    B --> C["1A"]
    B --> D["4A"]
    C --> E["Vcc 1OE"]
    D --> F["4OE"]
    E --> G["Regulated 3.3 V or 5 V"]
    F --> G
    G --> H["μC System Logic LEDs"]
    H --> I["GND"]
    I --> E

Figure 9-1. Typical Application Schematic

9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads, so routing and load conditions should be considered to prevent ringing.

9.2.2 Detailed Design Procedure

1. Recommended Input Conditions

2. For rise time and fall time specifications, see t/ V in the Section 6.3 table.

3. For specified High and low levels, see V_IH and V_IL in the Section 6.3 table.

4. Recommend Output Conditions

5. Load currents should not exceed 35 mA per output and 70 mA total for the part.

6. Outputs should not be pulled above V cc.

9.2.3 Application Curves

Figure 9-2. Switching Characteristics Comparison

10 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Section 6.3 table.

Each V_CC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 F is recommended. If there are multiple V_CC pins, 0.01 F or 0.022 F is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 F and 1 F are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results.

11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states.

Specified in Figure 11-1 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or V_CC , whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.

11.2 Layout Example

Vcc Unused Input Input Output

Input Unused Input Output

Figure 11-1. Layout Diagram

12 Device and Documentation Support

12.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.

Table 12-1. Related Links

PARTS PRODUCT	FOLDER SAMPLE & BUY	TECHNICAL DOCUMENTS	TOOLS & SOFTWARE	SUPPORT & COMMUNITY
SN74LV125A Click here Click here Click here Click here

12.2 Trademarks

All trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.4 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGING INFORMATION

Orderable Device Status(1)		Package Type	Package Drawing	Pins	Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4-5)	Samples
SN74LV125AD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV125A											Samples
SN74LV125ADBR	ACTIVE	SSOP	DB	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV125A	Samples
SN74LV125ADG4	ACTIVE	SOIC	D	14	50	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV125A	Samples
SN74LV125ADGVR	ACTIVE	TVSOP	DGV	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV125A	Samples
SN74LV125ADR	ACTIVE	SOIC	D	14	2500	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV125A	Samples
SN74LV125ADRE4	ACTIVE	SOIC	D	14	2500	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV125A	Samples
SN74LV125AN	ACTIVE	PDIP	N	14	25	RoHS & Non-Green	NIPDAU	N / A for Pkg Type	-40 to 125	SN74LV125AN	Samples
SN74LV125ANSR	ACTIVE	SO	NS	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	74LV125A	Samples
SN74LV125APW	ACTIVE	TSSOP	PW	14	90	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV125A	Samples
SN74LV125APWR	ACTIVE	TSSOP	PW	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV125A	Samples
SN74LV125APWRE4	ACTIVE	TSSOP	PW	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV125A	Samples
SN74LV125APWRG4	ACTIVE	TSSOP	PW	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV125A	Samples
SN74LV125APWT	ACTIVE	TSSOP	PW	14	250	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV125A	Samples
SN74LV125ARGYR	ACTIVE	VQFN	RGY	14	3000	RoHS & Green	NIPDAU	Level-2-260C-1 YEAR	-40 to 125	LV125A	Samples
SN74LV125ARGYRG4	ACTIVE	VQFN	RGY	14	3000	RoHS & Green	NIPDAU	Level-2-260C-1 YEAR	-40 to 125	LV125A	Samples

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: Ti defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "\~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LV125A :

• Automotive : SN74LV125A-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

A0	Dimension designed to accommodate the component width
B0	Dimension designed to accommodate the component length
K0	Dimension designed to accommodate the component thickness
W	Overall width of the carrier tape
P1	Pitch between successive cavity centers

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Pocket Quadrants User Direction of Feed

*All dimensions are nominal

Device Package	Type	Package Drawing	Pins	SPQ Reel	Diameter (mm)	Reel Width W1 (mm)	A0 (mm)	B0 (mm)	K0 (mm)	P1 (mm)	W (mm)	Pin1 Quadrant
SN74LV125ADBR SSOP DB 14	2000 330.0	16.4	8.35 6.6 2	4 12.0 16.0	Q1
SN74LV125ADGVR	TVSOP	DGV	14	2000	330.0	12.4	6.8	4.0	1.6	8.0	12.0	Q1
SN74LV125ADR	SOIC	D	14	2500	330.0	16.4	6.5	9.0	2.1	8.0	16.0	Q1
SN74LV125ANSR	SO	NS 14	2000 330.0 16.4	8.2 10.5 2	5 12.0 16.0	Q1
SN74LV125APWR	TSSOP	PW	14	2000	330.0	12.4	6.9	5.6	1.6	8.0	12.0	Q1
SN74LV125APWT	TSSOP	PW	14	250	330.0	12.4	6.9	5.6	1.6	8.0	12.0	Q1
SN74LV125ARGYR	VQFN	RGY	14	3000	330.0	12.4	3.75	3.75	1.15	8.0	12.0	Q1

TAPE AND REEL BOX DIMENSIONS H L

*All dimensions are nominal

Device Package	Type Package Draw	wing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LV125ADBR SSOP DB 14 2000 853.0 449.0 35.0
SN74LV125ADGVR TVSOP DGV 14 2000 853.0 449.0 35.0
SN74LV125ADR SOIC D		14 2500 853.0 449.0 35.0
SN74LV125ANSR	SO	NS 14 2000 853.0 449.0 35.0
SN74LV125APWR	TSSOP	PW	14	2000	853.0	449.0	35.0
SN74LV125APWT	TSSOP	PW	14	250	853.0	449.0	35.0
SN74LV125ARGYR	VQFN	RGY 14 3000 853.0 449.0 35.0

TUBE

T - Tube height L - Tube length W - Tube width B - Alignment groove width

*All dimensions are nominal

Device Package	Name Package Type	Pins SPQ L	(mm) W (mm)	T (μm) B	(mm)
SN74LV125AD D SO	C 14 50 506.6 8 3940	4.32
SN74LV125ADG4	D SOIC 14	50 506.6 8 3940	4.32
SN74LV125AN	N	PDIP	14	25	506	13.97	11230	4.32
SN74LV125APW	PW	TSSOP	14	90	530	10.2	3600	3.5

RGY (S-PVQFN-N14)

PLASTIC QUAD FLATPACK NO-LEAD

3,65 3,35 A 13 9 B 3,65 3,35 Pin 1 Index Area Top and Bottom 1 2 6 F 1,00 0,80 0,20 Nominal Lead Frame Seating Plane 0,08 C 0,05 0,00 C Seating Height 2,00 0,50 14X 0,50 0,30 2 6 1 THERMAL PAD 7 1,50 SIZE AND SHAPE SHOWN ON SEPRATE SHEET 8 14X 0,30 0,18 13 9 ⊕ 0,10 M C A B 0,05 M C

Bottom View

4203539-2/1 06/2011

NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.
C. QFN (Quad Flatpack No-Lead) package configuration.
D. The package thermal pad must be soldered to the board for thermal and mechanical performance.
E. See the additional figure in the Product Data Sheet for details regarding the exposed thermal pad features and dimensions.

Pin 1 identifiers are located on both top and bottom of the package and within the zone indicated.

The Pin 1 identifiers are either a molded, marked, or metal feature.

G. Package complies to JEDEC MO-241 variation BA.

RGY (S-PVQFN-N14)

PLASTIC QUAD FLATPACK NO-LEAD

THERMAL INFORMATION

This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB). After soldering, the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC).

For information on the Quad Flatpack No-Lead (QFN) package and its advantages, refer to Application Report, QFN/SON PCB Attachment, Texas Instruments Literature No. SLUA271. This document is available at www.ti.com.

The exposed thermal pad dimensions for this package are shown in the following illustration.

2 6 Exposed Thermal Pad 1 7 2,05±0,10 14 8 13 9 2,05±0,10

Bottom View

Exposed Thermal Pad Dimensions

4206353-2/P 03/14

NOTE: All linear dimensions are in millimeters

RGY (S-PVQFN-N14)
PLASTIC QUAD FLATPACK NO-LEAD

Example Board Layout 4,30 Note D 4,30 2,60 1,50 2,05 2,05 8x0,50 0.28 Example Stencil Design 0.125mm Stencil Thickness (Note E) 4,25 4,25 2,65 1,50 0,82 50 0,30 0,80 x 14 PL 8x0,50 0,23 x 14 PL. 64% solder coverage by printed area on center thermal pad Non Solder Mask Defined Pad Example Solder Mask Opening (Note F) R0,14 0,08 0,85 0,28 Example Pad Geometry (Note C) All Around Example Via Layout Design may vary depending on constraints (Note D, F) 6xØ0,3 1,00 1,00 4208122-2/P 03/14

NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate designs.
D. This package is designed to be soldered to a thermal pad on the board. Refer to Application Note, Quad Flat-Pack QFN/SON PCB Attachment, Texas Instruments Literature No. SLUA271, and also the Product Data Sheets for specific thermal information, via requirements, and recommended board layout. These documents are available at www.ti.com http://www.ti.com.
E. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC 7525 for stencil design considerations.
F. Customers should contact their board fabrication site for minimum solder mask web tolerances between signal pads.

MECHANICAL DATA

NS (R-PDSO-G\*\*)

PLASTIC SMALL-OUTLINE PACKAGE

14-PINS SHOWN

1,27 14 0,51 0,35 Ø 0,25① 8 5,60 5,00 8,20 7,40 1 7 A

0,15 NOM Gage Plane 0,25 0°-10° 1,05 0,55

2,00 MAX 0,15 0,05

Seating Plane 0.10

DIM\PINS **	14	16	20	24
A MAX	10,50	10,50	12,90	15,30
A MIN	9,90	9,90	12,30	14,70

4040062/C 03/03

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.

DGV (R-PDSO-G\*\*) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

DIM\PINS **	14		20		382416	48	56
A MAX	3,70		5,10	5,103,70	7,90	9,80	11,40
A MIN	3,50	3,50	4,90	4,90	7,70	9,60	11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 per side.
D. Falls within JEDEC: 24/48 Pins - MO-153

14/16/20/56 Pins - MO-194

D (R-PDSO-G14)
PLASTIC SMALL OUTLINE

0.344 (8,75) 0.337 (8,55) 14 8 Pin 1 Index Area 1 0.050 (1,27) 7 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,80) 0.020 (0,51) 0.012 (0,31) ⊕ 0.010 (0,25) M 0.069 (1,75) Max 0.010 (0,25) 0.004 (0,10) Gcuge Plane 0.010 (0,25) 0.005 (0,13) 0°-8° Seating Plane 0.010 (0,25) 0.050 (1,27) 0.016 (0,40) 4040047-5/M 06/11

NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.006 (0,15) each side.
Body width does not include interlead flash. Interlead flash shall not exceed 0.017 (0,43) each side.
E. Reference JEDEC MS-012 variation AB.

D (R-PDSO-G14)

4211283-3/E 08/12
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate designs.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

PW (R-PDSO-G14)

NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 each side.

Body width does not include interlead flash. Interlead flash shall not exceed 0,25 each side.

E. Falls within JEDEC MO-153

PW (R-PDSO-G14)

A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate designs.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

N (R-PDIP-T\*\*)

16 PINS SHOWN

PLASTIC DUAL-IN-LINE PACKAGE

A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) 0.045 (1,14)

C

DIM\PINS **	14	16	18	20
A MAX	0.775(19,69)	0.775(19,69)	0.920(23,37)	1.060(26,92)
A MIN	0.745(18,92)	0.745(18,92)	0.850(21,59)	0.940(23,88)
MS-001VARIATION	AA	BB	AC	AD

0.045 (1,14) 0.030 (0,76) D 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) ⊕ 0.010 (0,25) M 14/18 Pin Only 20 Pin vendor opt

0.325 (8,26) 0.300 (7,62) 0.015 (0,38) Gauge Plane 0.010 (0,25) NOM 0.430 (10,92) MAX

4040049/E 12/2002

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C Falls within JEDEC MS-001, except 18 and 20 pin minimum body length (Dim A).

The 20 pin end lead shoulder width is a vendor option, either half or full width.

DB (R-PDSO-G\*\*) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,65 28 0,38 0,22 0,15 M 15 5,60 5,00 8,20 7,40 1 14 A

0,25 0,09 Gage Plane 0°-8° 0,25 0,95 0,55

2,00 MAX 0,05 MIN

Seating Plane 0,10

DIM\PINS **	14	16	20	24	28	30	38
A MAX	6,50	6,50	7,50	8,50	10,50	10,50	12,90
A MIN		5,905,906,90			9,907,909,90		12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

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