SN74AC241PWR - Electronic component TEXAS INSTRUMENTS - Free user manual and instructions

Product Type	Octal Buffer/Line Driver with 3-State Outputs
Brand	Texas Instruments
Model	SN74AC241PWR
Package	TSSOP-20
Number of Bits	8 (Octal)
Logic Family	AC (Advanced CMOS)
Supply Voltage (Vcc)	2 V to 6 V
Operating Temperature Range	-40°C to +85°C
Propagation Delay (typical)	5.5 ns @ 5 V, 50 pF
Output Current (per output)	±24 mA
Input/Output Type	3-State Outputs
Number of Channels	2 (4-bit each) or 8-bit total
Mounting Type	Surface Mount
Dimensions (approx)	6.5 mm x 4.4 mm x 1.15 mm
Weight (approx)	0.15 g
Power Dissipation (max)	500 mW
ESD Protection	2 kV HBM
RoHS Compliant	Yes
Lead-Free	Yes
Maintenance	No maintenance required; handle with ESD precautions
Safety Precautions	Avoid exceeding absolute maximum ratings; use proper ESD grounding
Spare Parts/Repairability	Non-repairable; replace if faulty

Frequently Asked Questions - SN74AC241PWR TEXAS INSTRUMENTS

What is the function of the SN74AC241PWR?

The SN74AC241PWR is an octal buffer and line driver with 3-state outputs, used to drive buses or capacitive loads.

What is the supply voltage range?

The supply voltage Vcc ranges from 2 V to 6 V, making it compatible with various logic levels.

What package does this IC come in?

It comes in a TSSOP-20 (Thin Shrink Small Outline Package) with 20 pins.

Can the outputs be disabled?

Yes, the outputs have 3-state capability, allowing them to be set to high impedance using the output enable pins.

What is the typical propagation delay?

Typical propagation delay is 5.5 ns at 5 V supply with a 50 pF load.

Is this IC suitable for 5V logic?

Yes, it is designed for 5V operation and can also work with 3.3V systems as it accepts 2V to 6V.

What is the maximum output current?

Each output can source or sink up to ±24 mA.

Does it have ESD protection?

Yes, it includes 2 kV HBM (Human Body Model) ESD protection.

What are the temperature limits?

The operating temperature range is -40°C to +85°C.

Can I use this IC in battery-powered devices?

Yes, due to the CMOS technology and low power consumption, it is suitable for battery-powered applications.

USER MANUAL SN74AC241PWR TEXAS INSTRUMENTS

●2-V to 6-V V cc Operation
●Inputs Accept Voltages to 6 V
●Max t pd of 7.5 ns at 5 V

description/ordering information

These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The 'AC241 devices are organized as two 4-bit buffers/drivers with separate complementary output-enable (1OE and 2OE) inputs. When 1OE is low or 2OE is high, the device passes noninverted data from the A inputs to the Y outputs. When 1OE is high or 2OE is low, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, should be tied to V_CC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking or the current-sourcing capability of the driver.

SN54AC241...J OR W PACKAGE

SN54AC241 ... DB, DW, N, NS, OR PW PACKAGE (TOP VIEW)

1OE 1 20 Vcc 1A1 2 19 2OE 2Y4 3 18 1Y1 1A2 4 17 2A4 2Y3 5 16 1Y2 1A3 6 15 2A3 2Y2 7 14 1Y3 1A4 8 13 2A2 2Y1 9 12 1Y4 GND 10 11 2A1

SN54AC241 ... FK PACKAGE (TOP VIEW)

2Y4 1A1 1OE VCC 2OE 1A2 3 2 1 20 19 1Y1 4 18 2Y3 5 17 1A3 6 16 1Y2 2Y2 7 15 2A3 8 14 1Y3 9 10 11 12 13 2Y1 GND 2A1 1Y4 2A2

ORDERING INFORMATION

T_A	PACKAGE^†		ORDERABLEPART NUMBER	TOP-SIDEMARKING
-40°C to 85°C	PDIP - N Tube SN74AC	241N SN74AC2	41N
	SOIC =DW	Tube SN74AC2	41DW	AC241
		Tape and reel S	N74AC241DWR
	SOP - NS Tape and reel	SN74AC241NSR	AC241
	SSOP - DB Tape and reel	SN74AC241DBR	AC241
	TSSOP =PW	Tube SN74AC2	41PW	AC241
		Tape and reel S	N74AC241PWR
-55°C to 125°C	CDIP - J Tube SNJ54AC	C241J SNJ54AC	241J
	CFP - W Tube SNJ54AC	C241W	SNJ54AC241W
	LCCC - FK	Tube SNJ54AC	241FK SNJ54AC	241FK

^ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FUNCTION TABLES

INPUTS	OUTPUT1Y
1OE 1A
L H HL L H X Z	L

INPUTS	OUTPUT2Y
2OE 2A
HHH
HL	L
L X Z

logic diagram (positive logic)

graph TD
    A["1OE"] --> B["1"]
    B --> C["NOT"]
    D["1A1"] --> E["2"]
    E --> F["AND"]
    G["1A2"] --> H["4"]
    H --> I["AND"]
    J["1A3"] --> K["6"]
    K --> L["AND"]
    M["1A4"] --> N["8"]
    N --> O["AND"]
    P["18"] --> Q["1Y1"]
    R["16"] --> S["1Y2"]
    T["14"] --> U["1Y3"]
    V["12"] --> W["1Y4"]

graph TD
    A["2OE"] --> B["19"]
    C["2A1"] --> D["11"]
    E["2A2"] --> F["13"]
    G["2A3"] --> H["15"]
    I["2A4"] --> J["17"]
    B --> K["9"]
    D --> L["7"]
    F --> M["5"]
    H --> N["3"]
    J --> O["2Y4"]
    style A fill:#f9f,stroke:#333
    style C fill:#f9f,stroke:#333
    style E fill:#f9f,stroke:#333
    style G fill:#f9f,stroke:#333
    style I fill:#f9f,stroke:#333
    style K fill:#ccf,stroke:#333
    style L fill:#ccf,stroke:#333
    style M fill:#ccf,stroke:#333
    style N fill:#ccf,stroke:#333
    style O fill:#ccf,stroke:#333

absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ^†

Supply voltage range, V_CC -0.5 V to 7 V

Input voltage range, V_I (see Note 1) -0.5 V to V CC + 0.5 V

Output voltage range, V_O (see Note 1) -0.5 V to V CC + 0.5 V

Input clamp current, I_IK ( V_I < 0 or V_I > V_CC ) ±20 mA

Output clamp current, I_OK ( V_O < 0 or V_O > V_CC ) .... ± 20 mA

Continuous output current, I_O ( V_O = 0 to V_CC ) ±50 mA

Continuous current through V_CC or GND ± 200 mA

Package thermal impedance, _JA (see Note 2): DB package 70^ / W

DW package 58°C/W

N package 69°C/W

NS package 60°C/W

PW package 83°C/W

Storage temperature range, T_stg -65^ to 150^

^ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

		SN54AC241 SN74AC241			UNIT
		MIN MAX MIN MAX
V_CC Supply voltage 2 6 2 6 V
V_iHI High-level input voltage	V_CC=3 V 2.1 2.1				V
	V_CC=4.5 V 3.15 3.15
	V_CC=5.5 V 3.85 3.85
V_iL Low-level input voltage	V_CC=3 V 0.9 0.9				V
	V_CC=4.5 V 1.35 1.35
	V_CC=5.5 V 1.65 1.65
V_I Input voltage		0 V CC		0 V_CC	V
V_O Output voltage		0 V CC		0 V_CC	V
I_QH High-level output current	V_CC=3 V	-12		-12	mA
	V_CC=4.5 V -24	-24
	V_CC=5.5 V -24	-24
I_QL Low-level output current	V_CC=3 V	12		12	mA
	V_CC=4.5 V	24		24
	V_CC=5.5 V	24		24
t/ v Input transition rise or fall rate		8		8	ns/V
T_A Operating free-air temperature		-55 125		-40 85	°C

NOTE 3: All unused inputs of the device must be held at V_CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST		CONDITIONS V	^''CC	T_A = 25^ SN54A	C241 SN74AC241	UNIT
				MIN TYP MAX MIN MAX	MAX MIN MAX
V_OH		I_OH = -50 μA	3 V	2.9 2.9 2.9
			4.5 V	4.4 4.4 4.4
			5.5 V	5.4 5.4 5.4
		I_OH = -12 mA 3 V 2.56 2.4 2.46
		I_OH^+ = -24 mA	4.5 V	3.86 3.7 3.76
			5.5 V	4.86 4.7 4.76
		I_OH = -50 mA^†	5.5 V	3.85
		I_OH = -75 mA^†	5.5 V			3.85
V_OL		I_OL = 50 μA	3 V	0.1 0.1 0.1
			4.5 V	0.1 0.1 0.1
			5.5 V	0.1 0.1 0.1
		I_OL = 12 mA	3 V	0.36	0.5	0.44
		I_OL = 24 mA	4.5 V	0.36	0.5 0.44
			5.5 V	0.36	0.5 0.44
		I_OL = 50 mA^†	5.5 V		1.65
		I_OL = 75 mA^†	5.5 V			1.65
^''I	Data inputs	V_I = V_CC or GND	5.5 V	±0.1	±1	±1
	Control inputs	V_I = V_CC or GND		±0.1	±1	±1
I_OZ		V_O = V_CC or GND, V_I(OE) = V_IL or V_IH	5.5 V	±0.25	±5	±2.5
I_CC		V_I = V_CC or GND, I_O = 0	5.5 V	4	80	40
C_i		V_I = V_CC or GND	5 V	2.5

^ Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.

switching characteristics over recommended operating free-air temperature range, V_CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)

PARAMETER	FROM(INPUT)	TQ(OUTPUT)	T_A = 25°C SN54A			C241 SN74AC241				UNIT
			MIN TYP MAX MIN MAX			MAX MIN MAX
t_PLH	A	Y	1.5	6	9	1	12	1.5	10	ns
t_PHL			1.5	6	9	1	11.5	1	10.5
t_PZH	OE or OE	Y	1.5	6.5	12.5	1	13	1	13	ns
t_PZL			1.5	7	12	1	13	1.5	13
t_PHZ	OE or OE	Y	2	8	12	1	13	2	12.5	ns
t_PLZ			1.5	7	12.5	1	13	1	13.5

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

switching characteristics over recommended operating free-air temperature range, V_CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

PARAMETER	FROM TO(INPUT)	(OUTPUT)	T_A = 25^ SN54A	C241 SN74AC241		UNIT
			MIN TYP MAX MIN MAX	MAX MIN MAX
t_PLH	A	Y	1.5 5 7 1 9.5 1 7.5			ns
t_PHL			1.5 4.5 7 1 9 1 7.5
t_PZH	OE or OE	Y	1.5 5.5 9 1 10 1 9.5			ns
t_PZL			1.5 5.5 9 1 10 1 9.5
t_PHZ	OE or OE	Y	1.5 6.5 10 1 11.5 1 10.5			ns
t_PLZ			1.5 6 10 1 11.5 1 10.5

operating characteristics, V_CC = 5 V , T_A = 25^

PARAMETER TEST CONDITIONS TYP UNIT
C_pd	Power dissipation capacitance per buffer/driver C	_L=50 pF, f=1 MHz	45	pF

PARAMETER MEASUREMENT INFORMATION

From Output Under Test C_L = 50 pF (see Note A) 500 Ω 500 Ω S1 2 × V_CC Open

TEST	S1
t_PLH/t_PHL	Open
t_PLZ/t_PZL	2 × V_CC
t_PHZ/t_PZH	Open

LOAD CIRCUIT

Input 50% VCC 50% VCC 0 V tPLH tPHL Output 50% VCC VOH 50% VCC VOL

VOLTAGE WAVEFORMS

VOLTAGE WAVEFORMS
NOTES: A. C_L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z_0 = 50 , t_r ≤ 2.5 ns , t_f ≤ 2.5 ns .
D. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

TEXAS INSTRUMENTS

www.ti.com

PACKAGE OPTION ADDENDUM

10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status(1)		Package Type	Package Drawing	Pins	Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4-5)	Samples
SN74AC241DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC241											Samples
SN74AC241DW	ACTIVE	SOIC	DW	20	25	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	AC241	Samples
SN74AC241DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC241											Samples
SN74AC241N	ACTIVE	PDIP	N	20	20	RoHS & Non-Green	NIPDAU	N / A for Pkg Type	-40 to 85	SN74AC241N	Samples
SN74AC241NSR	ACTIVE	SO	NS	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	AC241	Samples
SN74AC241PW	ACTIVE	TSSOP	PW	20	70	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	AC241	Samples
SN74AC241PWR	ACTIVE	TSSOP	PW	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	AC241	Samples

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “-” will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

TEXAS INSTRUMENTS

www.ti.com

PACKAGE OPTION ADDENDUM

10-Dec-2020

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

Package Drawing

Pins

SPQ Reel

Diameter (mm)

Reel Width W1 (mm)

A0 (mm)

B0 (mm)

K0 (mm)

P1 (mm)

W (mm)

Pin1 Quadrant

SN74AC241DBR SSO

P DB 20 2

000 330.0

16.4 8

2.7 5 2.5

12.0 16.0

Q1

SN74AC241DWR SOI

C DW 20

2000 330.0

24.4

0.8 13.3 2

7 12.0 24

0 Q1

SN74AC241NSR SO

NS 20 2000

330.0 24

4 8.4

13.0 2.5 1

2.0 24.0

Q1

SN74AC241PWR TSS

OP PW 20

2000 330

0 16.4

6.95 7.1

1.6 8.0 16.0

Q1

TAPE AND REEL BOX DIMENSIONS W L

*All dimensions are nominal

Device	Package Type	Package Drawing	Pins	SPQ	Length (mm)	Width (mm)	Height (mm)
SN74AC241DBR SSOP	DB 20 2000 853.0	449.0 35.0
SN74AC241DWR SOIC	DW 20 2000 367.0	367.0 45.0
SN74AC241NSR SO	NS 20 2000 367.0	367.0 45.0
SN74AC241PWR	TSSOP	PW	20	2000	853.0	449.0	35.0

TUBE

T - Tube height W-Tube width L - Tube length B - Alignment groove width

*All dimensions are nominal

Device	Package Name	Package Type	Pins	SPQ	L (mm)	W (mm)	T (μm)	B (mm)
SN74AC241DW DW	SOIC 20 25 507 12.8	3 5080 6.6
SN74AC241N N PDIP	20 20 506 13.97	11230	4.32
SN74AC241PW	PW TSSOP	20 70 530	10.2 3600	3.5

N (R-PDIP-T\*\*)

16 PINS SHOWN

PLASTIC DUAL-IN-LINE PACKAGE

A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) 0.045 (1,14)

C

DIM\PINS **	14	16	18	20
A MAX	0.775(19,69)	0.775(19,69)	0.920(23,37)	1.060(26,92)
A MIN	0.745(18,92)	0.745(18,92)	0.850(21,59)	0.940(23,88)
MS-001VARIATION	AA	BB	AC	AD

0.045 (1,14) 0.030 (0,76) D 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) ⊕ 0.010 (0,25) M 14/18 Pin Only 20 Pin vendor opt

0.325 (8,26) 0.300 (7,62) 0.015 (0,38) Gauge Plane 0.010 (0,25) NOM 0.430 (10,92) MAX

4040049/E 12/2002

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C Falls within JEDEC MS-001, except 18 and 20 pin minimum body length (Dim A).

The 20 pin end lead shoulder width is a vendor option, either half or full width.

SMALL OUTLINE PACKAGE

A 6.6 TYP 6.2 PIN 1 INDEX AREA 1 20 18X 0.65 6.6 6.4 NOTE 3 2X 5.85 10 11 20X 0.30 0.19 B 4.5 4.3 NOTE 4 ⊕ 0.1@ A B

C SEATING PLANE 0.1 C 1.2 MAX

SEE DETAIL A (0.15) TYP

GAGE PLANE 0.25 0.15 0.05 0°-8° 0.75 0.50 DETAIL A TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

SMALL OUTLINE PACKAGE

20X (1.5) 1 20X (0.45) SYMM (R0.05) TYP 18X (0.65) 10 (5.8) 11 SYMM

LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN SCALE: 10X

SOLDER MASK OPENING METAL EXPOSED METAL 0.05 MAX ALL AROUND

NON-SOLDER MASK DEFINED (PREFERRED)

METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL 0.05 MIN ALL AROUND

SOLDER MASK DETAILS

4220206/A 02/2017

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SMALL OUTLINE PACKAGE

20X (1.5) 1 20X (0.45) 18X (0.65) 10 (5.8) SYMM (20) (R0.05) TYP SYMM 11

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220206/A 02/2017

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

PW (R-PDSO-G20)

Example Board Layout

18x0,65 5,6 Example Non Soldermask Defined Pad Example Solder Mask Opening (See Note E) 0,3 1,6 0,07 Pad Geometry All Around

Based on a stencil thickness of .127mm (.005inch).

20x0,25 1,55 5,6 18x0,65

4211284-5/G 08/15

NOTES:

A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate design.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

MECHANICAL DATA

NS (R-PDSO-G\*\*)

PLASTIC SMALL-OUTLINE PACKAGE

14-PINS SHOWN

1,27 14 0,51 0,35 Ø 0,25① 8 5,60 5,00 8,20 7,40 1 7 A

0,15 NOM Gage Plane 0,25 0°-10° 1,05 0,55

2,00 MAX 0,15 0,05

Seating Plane 0.10

DIM\PINS **	14	16	20	24
A MAX	10,50	10,50	12,90	15,30
A MIN	9,90	9,90	12,30	14,70

4040062/C 03/03

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.

SOIC

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

SOIC

20X (2) 1 20X (0.6) 18X (1.27) (R0.05) TYP 10 SYMM 20 SYMM 11 (9.3)

LAND PATTERN EXAMPLE SCALE:6X

SOLDER MASK OPENING METAL 0.07 MAX ALL AROUND

NON SOLDER MASK DEFINED

METAL UNDER SOLDER MASK SOLDER MASK OPENING 0.07 MIN ALL AROUND

SOLDER MASK DEFINED
SOLDER MASK DETAILS

4220724/A 05/2016

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SOIC

20X (2) 1 20X (0.6) 18X (1.27) SYMM 20 SYMM 10 (9.3) 11

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

SMALL OUTLINE PACKAGE

A 8.2 7.4 TYP PIN 1 INDEX AREA 1 20 18X 0.65 7.5 6.9 NOTE 3 2X 5.85 10 11 20X 0.38 0.22 B 5.6 5.0 NOTE 4 ⊕ 0.1@ A B

C 0.1 C SEATING PLANE

SEE DETAIL A (0.15) TYP

GAGE PLANE 0.25 0° -8° 0.95 0.55 2 MAX 0.05 MIN

DETAIL A TYPICAL

4214851/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.

SMALL OUTLINE PACKAGE

20X (1.85) SYMM (0.45) 1 20X 18X (0.65) 10 (7) (R0.05) TYP 20 SYMM 11

LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN SCALE: 10X

SOLDER MASK OPENING METAL EXPOSED METAL 0.07 MAX ALL AROUND

NON-SOLDER MASK DEFINED (PREFERRED)

METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL 0.07 MIN ALL AROUND

SOLDER MASK DETAILS

4214851/B 08/2019

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SMALL OUTLINE PACKAGE

20X (1.85) SYMM (0.45) 20X 1 18X (0.65) 10 (7) (R0.05) TYP 20 SYMM 11

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4214851/B 08/2019

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

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