SN74HCT273N - Electronic component TEXAS INSTRUMENTS - Free user manual and instructions

USER MANUAL SN74HCT273N TEXAS INSTRUMENTS

SNx4HCT273 Octal D-Type Flip-Flops With Clear

1 Features

• Operating voltage range of 4.5 V to 5.5 V
  • Outputs can drive up to 10 LSTTL loads
• Low power consumption, 80 μA maximum I cc
  • Typical t _pd = 12 ns
• ±4 mA output drive at 5 V
• Low input current of 1 A maximum
• Inputs are TTL-voltage compatible
• Contain eight D-type flip-flops
• Direct clear input

2 Applications

• Buffer or storage registers
- Shift registers
- Pattern generators

3 Description

These devices are positive-edge-triggered D-type flip-flops with a common enable input. The 'HCT273 devices are similar to the 'HCT377 devices, but feature a common clear enable (CLR) input instead of a latched clock.

Device Information ^(1)

PART NUMBER	PACKAGE BODY SIZE (NOM)
SN74HCT273DW SO	C (20) 12.80 mm	× 7.50 mm
SN74HCT273DB SSOP	(20) 7.20 mm	× 5.30 mm
SN74HCT273N PDIP	(20) 25.40 mm ×	6.35 mm
SN74HCT273NS SO	(20) 15.00 mm ×	5.30 mm
SN74HCT273PW	TSSOP (20)	6.50 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram, Each Flip Flop (positive logic)

Table of Contents

1 Features....1
2 Applications....1
3 Description....1
4 Revision History....2
5 Pin Configuration and Functions....3
6 Specifications....4
6.1 Absolute Maximum Ratings.... 4
6.2 Recommended Operating Conditions ^(1) 4
6.3 Thermal Information....4
6.4 Electrical Characteristics....5
6.5 Timing Requirements....5
6.6 Switching Characteristics....6
6.7 Switching Characteristics....6
6.8 Operating Characteristics.... 6
7 Parameter Measurement Information.... 7

8 Detailed Description....8
8.1 Overview....8
8.2 Functional Block Diagram.... 8
8.3 Device Functional Modes......8
9 Power Supply Recommendations....9
10 Layout....9
10.1 Layout Guidelines....9
11 Device and Documentation Support....10
11.1 Receiving Notification of Documentation Updates.. 10
11.2 Support Resources.... 10
11.3 Trademarks.... 10
11.4 Electrostatic Discharge Caution.... 10
11.5 Glossary.... 10
12 Mechanical, Packaging, and Orderable Information....10

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (August 2003) to Revision F (February 2022) Page

- Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standards....1

5 Pin Configuration and Functions

CLR 1 ○ 1Q 2 1D 3 2D 4 2Q 5 3Q 6 3D 7 3Q 8 3D 9 GND 10 20 Vcc 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 CLK

DB, DW, N, NS, or PW package 20-Pin SSOP, SOIC, PDIP, SO, or TSSOP (Top View)

1D 1Q CLR Vcc 8Q 2D 3 2 1 20 19 8D 2Q 4 5 17 7D 3Q 6 16 7Q 3D 7 15 6Q 4D 8 14 6D 4Q 9 10 11 12 13 GND CLK 5Q 5D

FK package 20-Pin LCCC (Top View)

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ^(1)

MIN MAX UNIT
V_CC	Supply voltage range -0.5 7 V
I_IK	Input clamp current(2)	V_I < 0 or V_I > V_CC	±20	mA
I_OK	Output clamp current(2)	V_O < 0 or V_O > V_CC	±20	mA
I_O	Continuous output current V	o = 0 to V_CC	±25	mA
	Continuous current through V_CC or GND ±50 mA
T_J	Junction temperature 150 °C
T_stg	Storage temperature range -65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 Recommended Operating Conditions ^(1)

			SN54HCT273(2)			SN74HCT273			UNIT
			MIN NOM MAX MIN			NOM	MAX
V_CC	Supply voltage		4.5	5	5.5	4.5	5	5.5	V
V_IH	High-level input voltage	V_CC=4.5V to 5.5V	2			2			V
V_IL	Low-level input voltage	V_CC=4.5V to 5.5V			0.8			0.8	V
V_I	Input voltage		0		V_CC	0		V_CC	V
V_O	Output voltage		0		V_CC	0		V_CC	V
t/ v	Input transition rise or fall rate				500			500	ns/V
T_A	Operating free-air temperature		-55		125	-40		85	°C

(1) All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

(2) Product Preview

6.3 Thermal Information

THERMAL METRIC		DW (SOIC)	DB (SSOP)	N (PDIP)	NS (SO)	PW (TSSOP)	UNIT
		20 PINS	20 PINS	20 PINS	20 PINS	20 PINS
R_ JA	Junction-to-ambient thermal resistance(1)	58	70	69	60	83	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report.

6.4 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS V		cc	T_A=25°C SN54HCT273 (1)			SN74HCT273	UNIT
				MIN TYP MAX MIN MAX MIN MAX
V_OH	V_I=V_IH or V_IL	I_OH=-20 μA 4.5 V	4.4 4.499 4.4 4.4					V
		I_OH=-4 mA 4.5 V	3.98 4.30 3.7 3.84
V_OL	V_I=V_IH or V_IL	I_OL=20 μA	4.5 V	0.001	0.1	0.1	0.1	V
		I_OL=4 mA	4.5 V	0.17	0.26	0.4	0.33
I_I	V_I=V_CC or 0		5.5 V	±0.1	±100	±1000	±1000	nA
I_CC	V_I=V_CC or 0, I O=0		5.5 V	8		160 80 μA
I_CC^(2)	One input at 0.5 V or 2.4 V,Other inputs at 0 or V_CC		5.5 V	1.4	2.4	3	2.9	mA
C_i			4.5 V to 5 V	3	10	10	10 pF

(1) Product Preview
(2) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or V_CC .

6.5 Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER			V_cc	T_A=25°C		SN54HCT273(1)		SN74HCT273		UNIT
				MIN	MAX	MIN	MAX	MIN	MAX
f_clock	Clock frequency		4.5 V		25		16		20	MHz
			5.5 V		28		19		23
t_w	Pulse duration	CLK high or low	4.5 V	20		30		25		ns
			5.5 V	18		25		22
		low	4.5 V	16		24		20
			5.5 V	14		20		17
t_su	Setup time before CLK↑	Data	4.5 V	20		30		25		ns
			5.5 V	17		25		21
		inactive	4.5 V	20		30		25
			5.5 V	17		25		21
t_h	Hold time, data after CLK↑		4.5 V	0		0		0		ns
			5.5 V	0		0		0

(1) Product Preview

6.6 Switching Characteristics

over recommended operating free-air temperature range, V_CC = 5 V ± 0.5 V (unless otherwise noted) (see Parameter Measurement Information)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	V_cc	SN54HCT273(1)		UNITT
				A=25°C	MIN MAX
				MIN TYP MAX
f_max			4.5 V 25 31 16			MHz
			5.5 V 28 37 19
t_pd	CLR Any		4.5 V 15 34 50			ns
			5.5 V 12 29 42
t_PHL	CLR Any		4.5 V 17 15 50			ns
			5.5 V 15 34 42
t_t		Any	4.5 V 8 18 22			ns
			5.5 V 7 19 21

(1) Product Preview

6.7 Switching Characteristics

over recommended operating free-air temperature range, V_CC = 5 V ± 0.5 V (unless otherwise noted) (see Parameter Measurement Information)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	V_cc	SN74HCT273		UNITT
				A=25°C	MIN MAX
				MIN TYP MAX
f_max			4.5 V 25 31 20			MHz
			5.5 V 28 37 23
t_pd	CLR Any		4.5 V 15 34 42			ns
			5.5 V 12 29 36
t_PHL	CLR Any		4.5 V 17 34 42			ns
			5.5 V 15 29 36
t_t		Any	4.5 V 8 15 19			ns
			5.5 V 7 14 17

6.8 Operating Characteristics

$$ V _ {C C} = 5 \mathrm{V}, T _ {\mathrm{A}} = 2 5 ^ {\circ} \mathrm{C} $$

PARAMETER TEST CONDITIONS TYP UNIT
C_pd	Power dissipation capacitance	No load	30	pF

7 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z_O = 50 , t_t < 6 ns.

For clock inputs, f_max is measured when the input duty cycle is 50%.

The outputs are measured one at a time with one input transition per measurement.

Test Point1 From Output Under Test C_L^(1)

(1) C_L includes probe and test-fixture capacitance.

Figure 7-1. Load Circuit for Push-Pull Outputs

Input 1.3V 1.3V tw 3V 0 V

Figure 7-2. Voltage Waveforms, TTL-Compatible CMOS Inputs Pulse Duration

Clock Input 1.3V 3V 0 V tsu tn Data Input 1.3V 1.3V 3V 0 V

Figure 7-3. Voltage Waveforms, TTL-Compatible CMOS Inputs Setup and Hold Times

(1) The greater between t_PLH and t_PHL is the same as t_pd .

Figure 7-4. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs

8 Detailed Description

8.1 Overview

These devices are positive-edge-triggered D-type flip-flops with a common enable input. The 'HCT273 devices are similar to the 'HCT377 devices, but feature a common clear enable (CLR) input instead of a latched clock.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. The circuits are designed to prevent false clocking by transitions at CLR.

8.2 Functional Block Diagram

graph LR
    CLK["CLK 11"] --> A["1D C1 R"]
    CLR["CLR 1"] --> B["1D C1 R"]
    A --> C["1D C1 R"]
    B --> D["1D C1 R"]
    C --> E["1D C1 R"]
    D --> F["1D C1 R"]
    E --> G["1D C1 R"]
    F --> H["1D C1 R"]
    G --> I["1D C1 R"]
    H --> J["1D C1 R"]
    I --> K["1D C1 R"]
    J --> L["1D C1 R"]
    K --> M["8D 18"]
    L --> N["8D 18"]
    M --> O["8D 18"]
    N --> P["8D 18"]
    O --> Q["8D 18"]
    P --> R["8D 18"]
    Q --> S["8Q 19"]
    R --> T["8Q 19"]
    S --> U["8Q 19"]

Figure 8-1. Logic Diagram (positive logic)

graph TD
    D --> TG1["TG"]
    TG1 --> C1["C"]
    C1 --> TG2["AND"]
    TG2 --> C2["C"]
    C2 --> TG3["TG"]
    TG3 --> C3["C"]
    C3 --> TG4["AND"]
    TG4 --> C4["C"]
    C4 --> TG5["TG"]
    TG5 --> C5["C"]
    C5 --> TG6["AND"]
    TG6 --> C6["C"]
    C6 --> TG7["TG"]
    TG7 --> C7["C"]
    C7 --> TG8["AND"]
    TG8 --> C8["C"]
    C8 --> TG9["TG"]
    TG9 --> C9["C"]
    C9 --> TG10["AND"]
    TG10 --> Q
    CLK(I) --> INV1["NOT"]
    INV1 --> INV2["NOT"]
    INV2 --> INV3["NOT"]
    INV3 --> INV4["NOT"]
    INV4 --> INV5["NOT"]
    INV5 --> INV6["NOT"]
    INV6 --> INV7["NOT"]
    INV7 --> INV8["NOT"]
    INV8 --> INV9["NOT"]
    INV9 --> INV10["NOT"]

Figure 8-2. Logic Diagram, each flip-flop (potitive logic)

8.3 Device Functional Modes

Table 8-1. Function Table (Each Flip-Flop)

INPUTS			OUTPUTQ
CLR CLK D
LXXL
H↑HH
H↑LL
HLXQ			0

9 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each V_CC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1- F capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1- F and 1- F capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results.

10 Layout

10.1 Layout Guidelines

When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or V CC, whichever makes more sense for the logic function or is more convenient.

11 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

11.3 Trademarks

TI E2E ^TM is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGING INFORMATION

Orderable Device Status(1)		Package Type	Package Drawing	Pins	Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4-5)	Samples
SN74HCT273DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT273											Samples
SN74HCT273DW	ACTIVE	SOIC	DW	20	25	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HCT273	Samples
SN74HCT273DWE4	ACTIVE	SOIC	DW	20	25	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HCT273	Samples
SN74HCT273DWG4	ACTIVE	SOIC	DW	20	25	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HCT273	Samples
SN74HCT273DWR	ACTIVE	SOIC	DW	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HCT273	Samples
SN74HCT273DWRG4	ACTIVE	SOIC	DW	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HCT273	Samples
SN74HCT273N	ACTIVE	PDIP	N	20	20	RoHS & Green	NIPDAU	N / A for Pkg Type	-40 to 85	SN74HCT273N	Samples
SN74HCT273NSR	ACTIVE	SO	NS	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HCT273	Samples
SN74HCT273PW	ACTIVE	TSSOP	PW	20	70	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HT273	Samples
SN74HCT273PWE4	ACTIVE	TSSOP	PW	20	70	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HT273	Samples
SN74HCT273PWR	ACTIVE	TSSOP	PW	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HT273	Samples
SN74HCT273PWT	ACTIVE	TSSOP	PW	20	250	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HT273	Samples

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "\~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package	Type	Package Drawing	Pins	SPQ Reel	Diameter (mm)	Reel Width W1 (mm)	A0 (mm)	B0 (mm)	K0 (mm)	P1 (mm)	W (mm)	Pin1 Quadrant
SN74HCT273DBR SS	OP DB 20	2000 330.0	16.4	8.2 7.5 2.5	12.0 16.0	Q1
SN74HCT273DWR SC	IC DW 20	2000 330.0	24.4	10.9 13.3	2.7 12.0 24.0	Q1
SN74HCT273NSR SO	NS 20 2000	330.0 24.4	8.4	13.0 2.5	2.0 24.0	Q1
SN74HCT273PWR TS	SOP PW 20	2000 330.0	16	4 6.95 7.0	1.4 8.0 16.0	Q1
SN74HCT273PWT TS	SOP PW	20	250 3	30.0 16.4	6.95 7.1 1.6	8.0 16.0	Q1

TAPE AND REEL BOX DIMENSIONS W L

*All dimensions are nominal

Device	Package Type	Package Drawing	Pins	SPQ	Length (mm)	Width (mm)	Height (mm)
SN74HCT273DBR SSOP	DB 20 2000 853.0	449.0 35.0
SN74HCT273DWR SO	C DW 20 2000 367.0	367.0 45.0
SN74HCT273NSR SO	NS 20 2000 367.0	367.0 45.0
SN74HCT273PWR	TSSOP	PW	20	2000	853.0	449.0	35.0
SN74HCT273PWT	TSSOP	PW	20	250	853.0	449.0	35.0

TUBE

T - Tube height L - Tube length W - Tube width B - Alignment groove width

*All dimensions are nominal

Device	Package Name	Package Type	Pins	SPQ	L (mm)	W (mm)	T (μm)	B (mm)
SN74HCT273DW DW	SOIC 20 25 507 12.83 5080 6.6
SN74HCT273DWE4 DW	SOIC 20 25 507 12.83 5080 6.6
SN74HCT273DWG4 DW	SOIC 20 25 507 12.83 5080 6.6
SN74HCT273N	N	PDIP	20	20	506	13.97	11230	4.32
SN74HCT273PW PW	TSSOP 20 70 530	10.2 3600	3.5
SN74HCT273PWE4	PW	TSSOP	20	70	530	10.2	3600	3.5

SMALL OUTLINE PACKAGE

A 8.2 7.4 TYP PIN 1 INDEX AREA 1 20 18X 0.65 7.5 6.9 NOTE 3 2X 5.85 10 11 20X 0.38 0.22 B 5.6 5.0 NOTE 4 ⊕ 0.1@ A B

C 0.1 C SEATING PLANE

SEE DETAIL A (0.15) TYP

GAGE PLANE 0.25 0° -8° 0.95 0.55 2 MAX 0.05 MIN

DETAIL A TYPICAL

4214851/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.

SMALL OUTLINE PACKAGE

20X (1.85) SYMM (0.45) 1 20X 18X (0.65) 10 (7) R0.05 TYP 20 SYMM 11

LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN SCALE: 10X

SOLDER MASK OPENING METAL EXPOSED METAL 0.07 MAX ALL AROUND

NON-SOLDER MASK DEFINED (PREFERRED)

METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL 0.07 MIN ALL AROUND

SOLDER MASK DETAILS

4214851/B 08/2019

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SMALL OUTLINE PACKAGE

20X (1.85) 1 20X (0.45) SYMM (7) 18X (0.65) 10 (R0.05) TYP 20 SYMM 11

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4214851/B 08/2019

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

MECHANICAL DATA

NS (R-PDSO-G\*\*)

PLASTIC SMALL-OUTLINE PACKAGE

14-PINS SHOWN

1,27 14 0,51 0,35 Ø 0,25① 8 5,60 5,00 8,20 7,40 1 7 A

0,15 NOM Gage Plane 0,25 0°-10° 1,05 0,55

2,00 MAX 0,15 0,05

Seating Plane 0.10

DIM\PINS **	14	16	20	24
A MAX	10,50	10,50	12,90	15,30
A MIN	9,90	9,90	12,30	14,70

4040062/C 03/03

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.

N (R-PDIP-T\*\*)

16 PINS SHOWN

PLASTIC DUAL-IN-LINE PACKAGE

A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) 0.045 (1,14)

C

DIM\PINS **	14	16	18	20
A MAX	0.775(19,69)	0.775(19,69)	0.920(23,37)	1.060(26,92)
A MIN	0.745(18,92)	0.745(18,92)	0.850(21,59)	0.940(23,88)
MS-001VARIATION	AA	BB	AC	AD

0.045 (1,14) 0.030 (0,76) D 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) ⊕ 0.010 (0,25) M 14/18 Pin Only 20 Pin vendor opt

0.325 (8,26) 0.300 (7,62) 0.015 (0,38) Gauge Plane 0.010 (0,25) NOM 0.430 (10,92) MAX

4040049/E 12/2002

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C Falls within JEDEC MS-001, except 18 and 20 pin minimum body length (Dim A).

The 20 pin end lead shoulder width is a vendor option, either half or full width.

SOIC

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

SOIC

20X (2) 1 20X (0.6) 18X (1.27) (R0.05) TYP 10 SYMM 20 SYMM 11 (9.3)

LAND PATTERN EXAMPLE SCALE:6X

SOLDER MASK OPENING METAL 0.07 MAX ALL AROUND

NON SOLDER MASK DEFINED

METAL UNDER SOLDER MASK SOLDER MASK OPENING 0.07 MIN ALL AROUND

SOLDER MASK DEFINED
SOLDER MASK DETAILS

4220724/A 05/2016

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SOIC

20X (2) 1 20X (0.6) 18X (1.27) SYMM 20 SYMM 10 (9.3) 11

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

SMALL OUTLINE PACKAGE

A 6.6 TYP 6.2 PIN 1 INDEX AREA 1 20 18X 0.65 6.6 6.4 NOTE 3 2X 5.85 10 11 20X 0.30 0.19 B 4.5 4.3 NOTE 4 ⊕ 0.1@ A B

C SEATING PLANE 0.1 C 1.2 MAX

SEE DETAIL A (0.15) TYP

GAGE PLANE 0.25 0.15 0.05 0°-8° 0.75 0.50 DETAIL A TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

SMALL OUTLINE PACKAGE

20X (1.5) 1 20X (0.45) 18X (0.65) 10 (5.8) SYMM (R0.05) TYP 20 SYMM 11

LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN SCALE: 10X

SOLDER MASK OPENING METAL EXPOSED METAL 0.05 MAX ALL AROUND

NON-SOLDER MASK DEFINED (PREFERRED)

METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL 0.05 MIN ALL AROUND

SOLDER MASK DETAILS

4220206/A 02/2017

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SMALL OUTLINE PACKAGE

20X (1.5) 1 20X (0.45) SYMM (R0.05) TYP 20 18X (0.65) SYMM 10 (5.8) 11

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220206/A 02/2017

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

PW (R-PDSO-G20)

Example Board Layout

18x0,65 5,6 Example Non Soldermask Defined Pad Example Solder Mask Opening (See Note E) 0,3 1,6 0,07 Pad Geometry All Around

Based on a stencil thickness of .127mm (.005inch).

20x0,25 1,55 5,6 18x0,65

4211284-5/G 08/15

NOTES:

A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate design.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.

TI's products are provided subject to TI's Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI's provision of these resources does not expand or otherwise alter TI's applicable warranties or warranty disclaimers for TI products.

TI objects to and rejects any additional or different terms you may have proposed.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Copyright © 2022, Texas Instruments Incorporated