SN74AHC541N - Electronic component TEXAS INSTRUMENTS - Free user manual and instructions

USER MANUAL SN74AHC541N TEXAS INSTRUMENTS

SNx4AHC541OctalBuffers/DriversWith3-StateOutputs

1Features3Description

• OperatingRange2-Vto5.5-VV cc
• Latch-UpPerformanceExceeds250mA PerJESD17
• OnProductsComplianttoMIL-PRF-38535, AllParametersAreTestedUnlessOtherwise Noted.OnAllOtherProducts,Production ProcessingDoesNotNecessarilyIncludeTesting ofAllParameters.

2Applications

• Servers
  •PCsandNotebooks
  •NetworkSwitches
  •WearableHealthandFitnessDevices
  •TelecomInfrastructures
  •ElectronicPoints-of-Sale

TheSNx4AHC541 octalbuffersanddriversareideal fordrivingbuslinesorbuffermemoryaddress registers. Thesedevicesfeatureinputsandoutputs onoppositesidesofthepackagetofacilitateprinted circuitboardlayout.

DeviceInformation (1)

PARTNUMBER	PACKAGE	BODYSIZE(NOM)
SNx4AHC541N	PDIP(20)	25.40mmx6.35mm
SNx4AHC541DB	SSOP(20)	7.50mmx5.30mm
SNx4AHC541PW	TSSOP(20)	6.50mmx4.40mm
SNx4AHC541DGV	TVSOP(20)	5.00mmx4.40mm
SNx4AHC541DW	SOIC(20)	12.80mmx7.50mm

(1) For all available packages, seetheorderable addendum at the end of the datasheet.

SimplifiedBlockDiagram

OE1 1 OE2 19 A1 2 18 Y1

To Seven Other Channels

TableofContents

1 Features.... 1
2 Applications 1
3 Description 1
4 Revision History...... 2

5PinConfigurationandFunctions....3

6 Specifications.... 4

6.1 AbsoluteMaximumRatings....4
6.2ESDRatings....4
6.3RecommendedOperatingConditions....4
6.4ThermalInformation....5
6.5 Electrical Characteristics....5
6.6SwitchingCharacteristics, V CC =3.3V±0.3V......6
6.7SwitchingCharacteristics,V CC =5V±0.5V....6
6.8NoiseCharacteristics....7
6.9OperatingCharacteristics....7
6.10TypicalCharacteristics....7

7ParameterMeasurementInformation......8

8DetailedDescription....9

8.1Overview....9
8.2FunctionalBlockDiagram....9
8.3FeatureDescription....9
8.4DeviceFunctionalModes....9

9ApplicationandImplementation....10

9.1 Application Information....10
9.2 Typical Application....10

10PowerSupplyRecommendations....11

11 Layout.... 11

11.1 LayoutGuidelines....11
11.2LayoutExample....11

12DeviceandDocumentationSupport....12

12.1 RelatedLinks....12
12.2 Community Resources....12
12.3Trademarks....12
12.4ElectrostaticDischargeCaution....12
12.5Glossary....12

13Mechanical, Packaging, and Orderable Information 12

4RevisionHistory

ChangesfromRevisionN(July2003)toRevisionOPage

• Added Pin Configuration and Functions section, ESD Ratings table, Thermal Information table, Typical Characteristics section, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.... 1
• Added Military Disclaimer to Features list. 1
• Extended operating temperature range to 125°C....4
• Added -40^ to 125^ range for SN74AHC541 in Electrical Characteristics table.... 5
• AddedT _A = -40°C to 125°C for SN74AHC541 in both Switching Characteristics tables. 6

5PinConfigurationandFunctions

N,DB,PW,DGV,orDWPackage 20-PinPDIP,SSOP,TSSOP,TVSOP,SOIC TopView

OE1 1 20 VCC A1 2 19 OE2 A2 3 18 Y1 A3 4 17 Y2 A4 5 16 Y3 A5 6 15 Y4 A6 7 14 Y5 A7 8 13 Y6 A8 9 12 Y7 GND 10 11 Y8

FKPackage 20-PinLCCC TopView A2 A1 OE1 VCC 3 2 1 20 19 A3 4 18 Y1 A4 5 17 Y2 A5 6 16 Y3 A6 7 15 Y4 A7 8 14 Y5 9 10 11 12 13 A8 GND Y8 Y7 Y6

PinFunctions

PIN		I/ODESCRIPTION
NO.NAME
1OE1	I — OutputEnable1
2	A1	I	A1Input
3	A2	I	A2Input
4	A3	I	A3Input
5	A4	I	A4Input
6	A5	I	A5Input
7	A6	I	A6Input
8	A7	I	A7Input
9	A8	I	A8Input
10	GND	—	Ground
11Y8	O Y8Output
12Y7	O Y7Output
13Y6	O Y6Output
14Y5	O Y5Output
15Y4	O Y4Output
16Y3	O Y3Output
17Y2	O Y2Output
18Y1	O Y1Output
19	2	I	OutputEnable2
20	V_CC	—	PowerPin

6Specifications

6.1 AbsoluteMaximumRatings

overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1)

			MINMAXUNIT
V_CC	Supplyvoltage-0.57V
V_I	Inputvoltage(2)		-0.57V
V_O	Outputvoltage(2)		-0.5V CC+0.5V
I_IK	InputclampcurrentV	I<0	-20	mA
I_OK	Outputclampcurrent	V_O < 0orV _O >V_CC	±20	mA
I_O	Continuousoutputcurrent	V_O = 0toV CC	±25	mA
	ContinuouscurrentthroughV CC orGND		±75	mA
T_stg	Storagetemperature		-65 150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2ESDRatings

		VALUE	UNIT
V_(ESD) Electrostaticdischarge	Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,allpins (1)	+1000	V
	Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101,allpins (2)	+2000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1)

			SN54AHC541SN74AHC541				UNIT
			MIN	MAX	MIN	MAX
V_CC	Supply voltage		2	5.5	2	5.5	V
V_IH	High-levelinputvoltage	V_CC=2V	1.5		1.5		V
		V_CC=3V	2.1		2.1
		V_CC=5.5V	3.85		3.85
V_IL	Low-levelInputvoltage	V_CC=2V		0.5		0.5	V
		V_CC=3V		0.9		0.9
		V_CC=5.5V		1.65		1.65
V_I	Input voltage		0	5.5	0	5.5	V
V_O	Output voltage		0	V_CC	0	V_CC	V
I_OH	High-leveloutputcurrent	V_CC=2V		-50		-50	μA
		V_CC=3.3V±0.3V		-4		-4	mA
		V_CC=5V±0.5V		-8		-8
I_OL	Low-leveloutputcurrent	V_CC=2V		50		50	μA
		V_CC=3.3V±0.3V		4		4	mA
		V_CC=5V±0.5V		8		8
t/ v	Input transition rise or fall rate	V_CC=3.3V±0.3V		100		100	ns/V
		V_CC=5V±0.5V		20		20
T_A	Operating free-air temperature		-55	125	-40	125	°C

(1) AllunusedinputsofthedevicemustbeheldatV CC or GNDtoensureproperdeviceoperation. RefertotheTlapplicationreport, ImplicationsofSloworFloatingCMOSInputs(SCBA004).

6.4ThermalInformation

THERMALMETRIC (1)		SN74AHC541						UNIT
		DBDGV(SSOP)(TV)	DWNNSPWVSOP)(SOIC)	(PDIP)(SO)(TSSOP)
		20PINS20	PINS20PINS	20PINS20PINS	INS20PINS
R_ JA	Junction-to-ambient thermal resistance	99.9	119.2	83.0	54.9	80.4	105.4	°C/W
R_ JC(top)	Junction-to-case (top) thermal resistance	61.7	34.5	48.9	41.7	46.9	39.5	°C/W
R_ JB	Junction-to-board thermal resistance	55.2	60.7	50.5	35.8	47.9	56.4	°C/W
_JT	Junction-to-topcharacterization parameter	22.6	1.2	21.1	27.9	19.9	3.1	°C/W
_JB	Junction-to-boardcharacterization parameter	54.8	60.0	50.1	35.7	47.5	55.8	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report(SPRA953).

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TESTCONDITIONS	V_cc	T_A=25°C			SN54AHC541SN74AHC541				SN74AHC541-40°Cto125°C		UNIT
			MIN	TYP	MAX	MIN	MAX	MIN	MAX	MIN	MAX
V_OH	I_OH=-50 μA	2 V	1.9	2		1.9		1.9		1.9		V
		3 V	2.9	3		2.9		2.9		2.9
		4.5 V	4.4	4.5		4.4		4.4		4.4
	I_OH=-4 mA	3 V	2.58			2.48		2.48		2.48
	I_OH=-8 mA	4.5 V	3.94			3.8		3.8		3.8
V_OL	I_OL=50 μA	2 V			0.1		0.1		0.1		0.1	V
		3 V			0.1		0.1		0.1		0.1
		4.5 V			0.1		0.1		0.1		0.1
	I_OH=4 mA	3 V			0.36		0.5		0.44		0.5
	I_OH=8 mA	4.5 V			0.36		0.5		0.44		0.5
I_I	V_I=5.5VorGND 0	Vto5.5V			±0.1		±1 (1)		±1		±1	μA
I_OZ^(2)	V_O=V_CC or GND V_I()=V_IL or V_IH	5.5 V			±0.25		±2.5		±2.5		±2.5	μA
I_CC	V_I=V_CC or GND I_O=0	5.5 V			4		40		40		20	μA
C_i	V_I=V_CC or GND	5 V			2 10				10			pF
C_O	V_O=V_CC or GND	5V			4							pF

(1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontestedatV CC=0V.

(2) Forinputandoutputpins, I _OZ includestheinputleakagecurrent.

6.6SwitchingCharacteristics,V cc =3.3V±0.3V

overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure2)

PARAMETERUNI	FROMTOLOAD(INPUT)(OUTPUT)CAPACITANCE			T_A=25°C SN54AHC541SN74AHC541						SN74AHC541 T_A=-40°C Cto125°C
				TYPMAXMINMAX		MINMAXMIN		MAX
t_PLH	A	Y	C_L=15pF	5^(1)	7^(1)	1^(1)	8.5^(1)	1	8.5	1	8.5	ns
t_PHL				5^(1)	7^(1)	1^(1)	8.5^(1)	1	8.5	1	8.5
t_PZH		Y	C_L=15pF	6^(1)	10.5^(1)	1^(1)	11^(1)	111		1	11	ns
t_PZL				6^(1)	10.5^(1)	1^(1)	11^(1)	111		1	11
t_PHZ		Y	C_L=15pF	7^(1)	11^(1)	1^(1)	12^(1)	112		1	12	ns
t_PLZ				7^(1)	11^(1)	1^(1)	12^(1)	112		1	12
t_PLH	A	Y	C_L=50pF	7.5	10.5	1	12	1	12	1	12	ns
t_PHL				7.5	10.5	1	12	1	12	1	12
t_PZH		Y	C_L=50pF	8	14	1	16	1	16	1	16	ns
t_PZL				8	14	1	16	1	16	1	16
t_PHZ		Y	C_L=50pF	9	15.4	1	17.5	1	17.5	1	17.5	ns
t_PLZ				9	15.4	1	17.5	1	17.5	1	17.5
t_sk(0)			C_L=50pF		1.5^(2)				1.5			ns
t_PLH	AorB	Y	C_L=50pF	6.3	8.8	1	10	1	10	1	10	ns
t_PHL				6.3	8.8	1	10	1	10	1	10

(1) OnproductscomplianttoMIL-PRF-38535, this parameter is not produced tested.
(2) OnproductscomplianttoMIL-PRF-38535, thisparameterdoesnotapply.

6.7SwitchingCharacteristics,V CC =5V±0.5V

overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure2)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	LOADCAPACITANCE	T_A =25°C		SN54AHC541		SN74AHC541		T_A =-40°Cto125°CSN74AHC541		UNIT
				TYP	MAX	MIN	MAX	MIN	MAX	MIN	MAX
t_PLH	A	Y	C_L =15pF	3.5(1)	5(1)	1(1)	6(1)	1	6	1	6	ns
t_PHL				3.5(1)	5(1)	1(1)	6(1)	1	6	1	6
t_PZH		Y	C_L =15pF	4.7(1)	7.2(1)	1(1)	8.5(1)	1	8.5	1	8.5	ns
t_PZL				4.7(1)	7.2(1)	1(1)	8.5(1)	1	8.5	1	8.5
t_PHZ		Y	C_L =15pF	5(1)	7.5(1)	1(1)	8(1)	1	8	1	8	ns
t_PLZ				5(1)	7.5(1)	1(1)	8(1)	1	8	1	8
t_PLH	A	Y	C_L =50pF	5	7	1	8	1	8	1	8	ns
t_PHL				5	7	1	8	1	8	1	8
t_PZH		Y	C_L =50pF	6.2	9.2	1	10.5	1	10.5	1	10.5	ns
t_PZL				6.2	9.2	1	10.5	1	10.5	1	10.5
t_PHZ		Y	C_L =50pF	6	8.8	1	10	1	10	1	10	ns
t_PLZ				6	8.8	1	10	1	10	1	10
t_sk(o)			C_L =50pF		1(2)	1			1			ns

(1) OnproductscomplianttoMIL-PRF-38535, this parameter is not produced tested.
(2) OnproductscomplianttoMIL-PRF-38535, thisparameterdoesnotapply.

6.8NoiseCharacteristics

$$ V _ {C C} = 5 V, C \quad_ {L} = 5 0 p F, T \quad_ {A} = 2 5 ^ {\circ} C ^ {(1)} $$

PARAMETERUNIT		SN74AHC541
		MINMAX
V_OL(P)	Quietoutput,maximumdynamicV OL	0.8V
V_OL(V)	Quietoutput,minimumdynamicV OL	-0.8V
V_OH(V)	Quietoutput,minimumdynamicV OH	4.7V
V_IH(D)	High-leveldynamicinputvoltage3.5V
V_IL(D)	Low-leveldynamicinputvoltage1.5V

(1) Characteristicsareforsurface-mountpackagesonly.

6.9 Operating Characteristics

$$ V _ {C C} = 5 V, T _ {A} = 2 5 ^ {\circ} C $$

PARAMETER		TESTCONDITIONS	TYP	UNIT
C_pd	Power dissipation capacitance	No load, f = 1 MHz	12	pF

6.10 Typical Characteristics

Figure1.T PD (Typical) vs V CC at CL = 15pF&T A = 25°C

7ParameterMeasurementInformation

From Output Under Test Test Point CL (see Note A)

LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS

From Output Under Test CL (see Note A) RL = 1 kΩ S1 VCC Open GND

LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS

TEST S1
_LH/_PHL	Open
_LZ/_PZL	V_CC
_HZ/_PZH	GND
Open Drain	V_CC

Input 50% VCC tw 50% VCC VCC 0 V

Timing Input 50% VCC VCC 0 V tsu th Data Input 50% VCC 50% VCC VCC 0 V

VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

Input 50% VCC 50% VCC VCC 0 V tPLH tPHL In-Phase Output 50% VCC 50% VCC VOH VOL tPHL tPLH Out-of-Phase Output 50% VCC 50% VCC VOH VOL

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS

Output Control 50% VCC 50% VCC VCC 0 V tPZL tPLZ ≈VCC Output Waveform 1 S1 at VCC (see Note B) 50% VCC VOL + 0.3 V VOL tPZH tPHZ Output Waveform 2 S1 at GND (see Note B) 50% VCC VOH - 0.3 V VOH ≈0 V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z O = 50 Ω, t r ≤ 3 ns, t _f ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.

Figure2.LoadCircuitandVoltageWaveforms

8DetailedDescription

8.1Overview

TheSNx4AHC541 octalbuffers/driversareidealfordrivingbuslinesorbuffermemoryaddressregisters. These devicesfeatureinputsandoutputsonoppositesidesofthepackagetofacilitateprintedcircuitboardlayout.

The3-statecontrolgateisatwo-inputANDgatewithactive-lowinputs.lfeitheroutput-enable(OE1orOE2) inputishigh,allcorrespondingoutputsareinthehigh-impedancestate.Theoutputsprovidenoninverteddata whentheyarenotinthehigh-impedancestate.

Toensurethehigh-impedancestateduringpoweruporpowerdown,OEshouldbetiedtoV resistor. Theminimumvalueoftheresistorisdeterminedbythecurrent-sinkingcapabilityofthedriver. CC throughapullup

8.2FunctionalBlockDiagram

OE1 1 OE2 19 A1 2 18 Y1

To Seven Other Channels

8.3FeatureDescription

TheSNx4AHC541hasawideoperatingvoltagerangeof2Vto5.5V.Itallowsdownvoltageetranslationswhile acceptinginputvoltagesofupto5.5V.TheslowedgesoftheSNx4AHC541enablesthereductionofoutput ringing.

8.4DeviceFunctionalModes

Table1 list the functional modes for the SNx4AHC541 devices.

Table1.FunctionTable (EachBuffer/Driver)

INPUTS			OUTPUT Y
OE1OE2A
LL	L		L
LL	H		H
H	X	X	Z
X	H	X	Z

9ApplicationandImplementation

NOTE

InformationinthefollowingapplicationssectionsisnotpartoftheTlcomponent specification,andTldoesnotwarrantitsaccuracyorcompleteness.TI'scustomersare responsiblefordeterminingsuitabilityofcomponentsfortheirpurposes.Customersshould validateandtesttheirdesignimplementationtoconfirmsystemfunctionality.

9.1 Application Information

TheSN74AHC541isalow-driveCMOSdevicethatcanbeusedforamultitudeofbusinterfacetypeapplications whereoutputringingisaconcern. Thelowdriveandslowedgerateswillminimizeovershootandundershooton theoutputs. Theinputsacceptvoltagesupto5.5V, which allowsdowntranslationtotheV CC level. Figure4 showshowthesloweredgescanreducingingontheoutputcomparedtohigherdrivepartslikeAC.

9.2 Typical Application

graph TD
    A["Regulated 5.0 V"] --> B["μC or System Logic"]
    B --> C["OE"]
    C --> D["Vcc"]
    D --> E["5-V μC System logic LEDs"]
    B --> F["A1"]
    B --> G["A8"]
    B --> H["Y1"]
    B --> I["Y8"]
    B --> J["GND"]
    D --> K["Ground"]

Figure3.TypicalApplicationSchematic

9.2.1 DesignRequirements

This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive current that would exceed maximum limits. The high drivewill also create fasted edges into light loads, so routing and load condition should be considered to prevent ringing.

9.2.2 Detailed Design Procedure

1. Recommended Input Conditions:

2. For rise time and fall time specifications, see t / V in the Recommended Operating Conditions table.
   -Forspecifiedhighandlowlevels,seeV IH andV IL intheRecommendedOperatingConditionstable.
   -Inputsareovervoltage-tolerantallowingthemtogoashighas5.5VatanyvalidV cc.

3. RecommendedOutputConditions:

-Loadcurrentsshouldnotexceed25mAperoutputand75mAtotalforthepart.
-OutputsshouldnotbepulledaboveV cc.

TypicalApplication(continued)

9.2.3ApplicationCurve

$$ V _ {c c} = 3. 3 V, C \quad_ {L} = 1 5 p F, T \quad_ {A} = 2 5 ^ {\circ} C $$

Figure4.SimulatedPropagationDelayFromInput(A1)toOutput(Y1)

10 Power Supply Recommendations

The powersupply can be any voltage between the minimum and maximum supply voltage, operating in the Recommended Operating Condition stable. Each V CC terminal should have good bypass capacitortoprevent power disturbance. For devices with a single supply, 0.1 μF is recommended. If there are multiple Vcc terminals then 0.01 μF or 0.022 μF is recommended for each power terminal. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results.

11 Layout

11.1 LayoutGuidelines

When using multiple bit logic devices, input should not float. In many cases, functions or part so function of digital logic devices are unused. Some examples are when only two input so at triple-input AND gate are used, or when only 3 of the 4 buffer gates are used. Such input pin should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in the Figure 5 are rule that must be observed under all circumstances. All unused input so of digital logic devices must be connected to a high or low biastoprevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or V CC, whichever makes more sensorism more convenient. It is acceptable to float outputs unless the part is transceiver. If the transceiver has an output enable pin, it will disable the output section of the part when asserted. This will not disable the input section of the I/Osso they also cannot float when disabled.

11.2LayoutExample

Vcc Unused Input Input Output

Input Unused Input Output

Figure5.LayoutDiagram

12DeviceandDocumentationSupport

12.1 RelatedLinks

Thetablebelowlistsquickaccesslinks. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.

Table2.RelatedLinks

PARTSPRODU	CTFOLDERSAMPLE&	BUY	TECHNICALTOOLS&SUPPORT& DOCUMENTSSOFTWARECOMMUNITY
SN74AHC541	Click here	Click here	Click here	Click here	Click here
SN54AHC541	Click here	Click here	Click here	Click here	Click here

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contactinformationfortechnicalsupport.

12.3 Trademarks

E2EisatrademarkofTexasInstruments.

Allothertrademarksarethepropertyoftheirrespectiveowners.

12.4ElectrostaticDischargeCaution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.5Glossary

SLYZ022 — TIGlossary.

This glossarylistsandexplainsterms,acronyms,anddefinitions.

13Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this datasheet, refertothe left-hand navigation.

PACKAGING INFORMATION

Orderable Device Status(1)		Package Type	Package Drawing	Pins	Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4,5)	Samples
5962-9685701Q2A ACTIVE LCCC FK 20 1 Non-RoHS						& Green	SNPB N / A for Pkg Type -55 to 125 5962-			9685701Q2A SNJ54AHC 541FK	Samples
5962-9685701QRA ACTIVE CDIP J 20 1 Non-RoHS						& Green	SNPB N / A for Pkg Type -55 to 125 5962-9685701QR			A SNJ54AHC541J	Samples
5962-9685701QSA ACTIVE CFP W 20 1 Non-RoHS						& Green	SNPB N / A for Pkg Type -55 to 125 5962-9685701QS			A SNJ54AHC541W	Samples
SN74AHC541DBR	ACTIVE	SSOP	DB	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	HA541	Samples
SN74AHC541DBRG4	ACTIVE	SSOP	DB	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	HA541	Samples
SN74AHC541DGVR	ACTIVE	TVSOP	DGV	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	HA541	Samples
SN74AHC541DGVRG4	ACTIVE	TVSOP	DGV	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	HA541	Samples
SN74AHC541DW	ACTIVE	SOIC	DW	20	25	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	AHC541	Samples
SN74AHC541DWR	ACTIVE	SOIC	DW	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	AHC541	Samples
SN74AHC541DWRE4	ACTIVE	SOIC	DW	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	AHC541	Samples
SN74AHC541N	ACTIVE	PDIP	N	20	20	RoHS & Green	NIPDAU	N / A for Pkg Type	-40 to 125	SN74AHC541N	Samples
SN74AHC541NSR	ACTIVE	SO	NS	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	AHC541	Samples
SN74AHC541PW	ACTIVE	TSSOP	PW	20	70	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	HA541	Samples
SN74AHC541PWG4	ACTIVE	TSSOP	PW	20	70	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	HA541	Samples
SN74AHC541PWR	ACTIVE	TSSOP	PW	20	2000	RoHS & Green	NIPDAU | SN	Level-1-260C-UNLIM	-40 to 125	HA541	Samples
SN74AHC541PWRE4	ACTIVE	TSSOP	PW	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	HA541	Samples
SN74AHC541PWRG4	ACTIVE	TSSOP	PW	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	HA541	Samples

Orderable Device Status(1)	Package Type Package Drawing	Pins Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4-5)	Samples
SNJ54AHC541FK ACTIVE LCCC FK 20 1 Non-RoHS			& Green	SNPB N / A for Pkg Type -55 to 125 5962-			9685701Q2ASNJ54AHC541FK	Samples
SNJ54AHC541J ACTIVE CDIP J 20 1 Non-RoHS			& Green	SNPB N / A for Pkg Type -55 to 125 5962-9685701QR			ASNJ54AHC541J	Samples
SNJ54AHC541W ACTIVE CFP W 20 1 Non-RoHS			& Green	SNPB N / A for Pkg Type -55 to 125 5962-9685701QS			ASNJ54AHC541W	Samples

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "-" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54AHC541, SN74AHC541 :

Catalog : SN74AHC541

• Automotive : SN74AHC541-Q1, SN74AHC541-Q1

• Military : SN54AHC541

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package	Type	Package Drawing	Pins	SPQ Reel	Diameter (mm)	Reel Width W1 (mm)	A0 (mm)	B0 (mm)	K0 (mm)	P1 (mm)	W (mm)	Pin1 Quadrant
SN74AHC541DBR SSOP DB 20	2000 330.0	16.4	8.2 7.5 2.5	12.0 16.0	Q1
SN74AHC541DGVR TVSOP DGV	20 2000 3	30.0 1	2.4 6.9 5.6	1.6 8.0 12.0	Q1
SN74AHC541DWR SOIC DW 20	2000 330.0	24.4	10.9 13.3	2.7 12.0 24.0	Q1
SN74AHC541NSR	SO	NS 20	2000 330.0 24.4	8.4 13.0 25	12.0 24.0	Q1
SN74AHC541PWR	TSSOP PW 20	2000	330.0 16.4	6.95 7.0	1.4 8.0 16.0	Q1
SN74AHC541PWR	TSSOP PW 20	2000	330.0 16.4	6.95 7.1	1.6 8.0 16.0	Q1
SN74AHC541PWRG4	TSSOP	PW	20	2000	330.0	16.4	6.95	7.0	1.4	8.0	16.0	Q1

TAPE AND REEL BOX DIMENSIONS W L

*All dimensions are nominal

Device	Package Type	Package Drawing	Pins	SPQ	Length (mm)	Width (mm)	Height (mm)
SN74AHC541DBR SSOP DB 20 2000 853	0 449.0 35.0
SN74AHC541DGVR TVSOP DGV 20 2000	853.0 449.0 35.0
SN74AHC541DWR SO C DW 20 2000 367	0 367.0 45.0
SN74AHC541NSR SO NS	20 2000 367.0 367.0 45.0
SN74AHC541PWR	TSSOP	PW	20	2000	853.0	449.0	35.0
SN74AHC541PWR	TSSOP	PW	20	2000	364.0	364.0	27.0
SN74AHC541PWRG4	TSSOP	PW	20	2000	853.0	449.0	35.0

TUBE

T - Tube height L - Tube length W - Tube width B - Alignment groove width

*All dimensions are nominal

Device	Package Name	Package Type	Pins	SPQ	L (mm)	W (mm)	T (μm)	B (mm)
5962-9685701Q2A FK	CCC 20 1 506.98	12.06 2030 NA
SN74AHC541DW	DW	SOIC	20	25	507	12.83	5080	6.6
SN74AHC541N	N	PDIP	20	20	506	13.97	11230	4.32
SN74AHC541PW	PW	TSSOP	20	70	530	10.2	3600	3.5
SN74AHC541PWG4	PW	TSSOP	20	70	530	10.2	3600	3.5
SNJ54AHC541FK FK	CCC 20 1 506.98	12.06 2030 NA

B 14 8 C 1 0.065 (1,65) 0.045 (1,14)

PINS **DIM	14	16	18	20
A	0.300(7,62)BSC	0.300(7,62)BSC	0.300(7,62)BSC	0.300(7,62)BSC
B MAX	0.785(19,94)	.840(21,34)	0.960(24,38)	1.060(26,92)
B MIN	—	—	—	—
C MAX	0.300(7,62)	0.300(7,62)	0.310(7,87)	0.300(7,62)
C MIN	0.245(6,22)	0.245(6,22)	0.220(5,59)	0.245(6,22)

0.005 (0,13) MIN 0.060 (1,52) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.026 (0,66) 0.014 (0,36) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) A 0°-15°

4040083/F 03/03

NOTES:

A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package is hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18 and GDIP1-T20.

DGV (R-PDSO-G\*\*) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

DIM\PINS **	14		20		382416	48	56
A MAX	3,70		5,10	5,103,70	7,90	9,80	11,40
A MIN	3,50	3,50	4,90	4,90	7,70	9,60	11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 per side.
D. Falls within JEDEC: 24/48 Pins - MO-153

14/16/20/56 Pins - MO-194

N (R-PDIP-T\*\*)

16 PINS SHOWN

PLASTIC DUAL-IN-LINE PACKAGE

A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) 0.045 (1,14)

C

DIM\PINS **	14	16	18	20
A MAX	0.775(19,69)	0.775(19,69)	0.920(23,37)	1.060(26,92)
A MIN	0.745(18,92)	0.745(18,92)	0.850(21,59)	0.940(23,88)
MS-001VARIATION	AA	BB	AC	AD

0.045 (1,14) 0.030 (0,76) D 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) ⊕ 0.010 (0,25) M 14/18 Pin Only 20 Pin vendor opt

0.325 (8,26) 0.300 (7,62) 0.015 (0,38) Gauge Plane 0.010 (0,25) NOM 0.430 (10,92) MAX

4040049/E 12/2002

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C Falls within JEDEC MS-001, except 18 and 20 pin minimum body length (Dim A).

The 20 pin end lead shoulder width is a vendor option, either half or full width.

SOIC

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

SOIC

20X (2) 1 20X (0.6) 18X (1.27) (R0.05) TYP 10 SYMM 20 SYMM 11 (9.3)

LAND PATTERN EXAMPLE SCALE:6X

SOLDER MASK OPENING METAL 0.07 MAX ALL AROUND

NON SOLDER MASK DEFINED

METAL UNDER SOLDER MASK SOLDER MASK OPENING 0.07 MIN ALL AROUND

SOLDER MASK DEFINED
SOLDER MASK DETAILS

4220724/A 05/2016

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SOIC

20X (2) 1 20X (0.6) 18X (1.27) SYMM 20 SYMM 10 (9.3) 11

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

FK (S-CQCC-N**)

28 TERMINAL SHOWN

LEADLESS CERAMIC CHIP CARRIER

NO. OF TERMINALS**	A		B
	MIN	MAX	MIN	MAX
20	0.342(8,69)	0.358(9,09)	0.307(7,80)	0.358(9,09)
28	0.442(11,23)	0.458(11,63)	0.406(10,31)	0.458(11,63)
44	0.640(16,26)	0.660(16,76)	0.495(12,58)	0.560(14,22)
52	0.740(18,78)	0.761(19,32)	0.495(12,58)	0.560(14,22)
68	0.938(23,83)	0.962(24,43)	0.850(21,6)	0.858(21,8)
84	1.141(28,99)	1.165(29,59)	1.047(26,6)	1.063(27,0)

4040140/D 01/11
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. Falls within JEDEC MS-004

SMALL OUTLINE PACKAGE

A 8.2 7.4 TYP PIN 1 INDEX AREA 1 20 18X 0.65 7.5 6.9 NOTE 3 2X 5.85 10 11 20X 0.38 0.22 B 5.6 5.0 NOTE 4 ⊕ 0.1@ A B

C 0.1 C SEATING PLANE

SEE DETAIL A (0.15) TYP

GAGE PLANE 0.25 0° -8° 0.95 0.55 2 MAX 0.05 MIN

DETAIL A TYPICAL

4214851/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.

SMALL OUTLINE PACKAGE

20X (1.85) SYMM (0.45) 1 20X 18X (0.65) 10 (7) (R0.05) TYP 20 SYMM 11

LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN SCALE: 10X

SOLDER MASK OPENING METAL EXPOSED METAL 0.07 MAX ALL AROUND

NON-SOLDER MASK DEFINED (PREFERRED)

METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL 0.07 MIN ALL AROUND

SOLDER MASK DETAILS

4214851/B 08/2019

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SMALL OUTLINE PACKAGE

20X (1.85) SYMM (0.45) 20X 1 18X (0.65) 10 (7) (R0.05) TYP 20 SYMM 11

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4214851/B 08/2019

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

MECHANICAL DATA

NS (R-PDSO-G\*\*)

PLASTIC SMALL-OUTLINE PACKAGE

14-PINS SHOWN

1,27 14 0,51 0,35 Ø 0,25① 8 5,60 5,00 8,20 7,40 1 7 A

0,15 NOM Gage Plane 0,25 0°-10° 1,05 0,55

2,00 MAX 0,15 0,05

Seating Plane 0.10

DIM\PINS **	14	16	20	24
A MAX	10,50	10,50	12,90	15,30
A MIN	9,90	9,90	12,30	14,70

4040062/C 03/03

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.

W (R-GDFP-F20)

CERAMIC DUAL FLATPACK

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification only.

E. Falls within Mil-Std 1835 GDFP2-F20

SMALL OUTLINE PACKAGE

A 6.6 TYP 6.2 PIN 1 INDEX AREA 1 20 18X 0.65 6.6 6.4 NOTE 3 2X 5.85 10 11 20X 0.30 0.19 B 4.5 4.3 NOTE 4 ⊕ 0.1@ A B

C SEATING PLANE 0.1 C 1.2 MAX

SEE DETAIL A (0.15) TYP

GAGE PLANE 0.25 0.15 0.05 0°-8° 0.75 0.50 DETAIL A TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

SMALL OUTLINE PACKAGE

20X (1.5) 1 20X (0.45) 18X (0.65) 10 (5.8) SYMM (R0.05) TYP 20 SYMM 11

LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN SCALE: 10X

SOLDER MASK OPENING METAL EXPOSED METAL 0.05 MAX ALL AROUND

NON-SOLDER MASK DEFINED (PREFERRED)

METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL 0.05 MIN ALL AROUND

SOLDER MASK DETAILS

4220206/A 02/2017

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SMALL OUTLINE PACKAGE

20X (1.5) 1 20X (0.45) SYMM (R0.05) TYP 20 18X (0.65) SYMM 10 (5.8) 11

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220206/A 02/2017

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

PW (R-PDSO-G20)

Example Board Layout

18x0,65 5,6 Example Non Soldermask Defined Pad Example Solder Mask Opening (See Note E) 0,3 1,6 0,07 Pad Geometry All Around

Based on a stencil thickness of .127mm (.005inch).

20x0,25 1,55 5,6 18x0,65

4211284-5/G 08/15

NOTES:

A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate design.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

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