SN74AS161N - Electronic component TEXAS INSTRUMENTS - Free user manual and instructions

USER MANUAL SN74AS161N TEXAS INSTRUMENTS

• Internal Look-Ahead Circuitry for Fast Counting
• Carry Output for n-Bit Cascading
• Synchronous Counting
• Synchronously Programmable
  ● Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N) and Ceramic (J) DIPs

description

These synchronous, presettable, 4-bit decade and binary counters feature an internal carry look-ahead circuitry for application in high-speed counting designs. The SN54ALS162B is a 4-bit decade counter. The 'ALS161B, 'ALS163B, 'AS161, and 'AS163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform.

These counters are fully programmable; they can be preset to any number between 0 and 9 or 15. Because presetting is synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163...J PACKAGE SN74ALS161B, SN74AS161,

SN74AS163...D OR N PACKAGE

SN74ALS163B ... D, DB, OR N PACKAGE (TOP VIEW)

CLR 1 16 VCC CLK 2 15 RCO A 3 14 QA B 4 13 QB C 5 12 QC D 6 11 QD ENP 7 10 ENT GND 8 9 LOAD

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 ... FK PACKAGE (TOP VIEW)

CLK CLR NC Vcc RCO A 4 B 5 NC 6 C 7 D 8 9 1 0 1 1 1 2 3 ENP GND NC LOAD ENT QA 18 QB 17 NC 16 QC 15 QD 14

NC – No internal connection

The clear function for the 'ALS161B and 'AS161 devices is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD, or enable inputs. The clear function for the SN54ALS162B, 'ALS163B, and 'AS163 devices is synchronous, and a low level at CLR sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000 (LLLL).

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled,

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

description (continued)

produces a high-level pulse while the count is maximum (9 or 15, with Q_A high). The high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.

These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for operation over the full military temperature range of -55^ to 125^ . The SN74ALS161B, SN74ALS163B, SN74AS161, and SN74AS163 are characterized for operation from 0^ to 70^ .

logic symbolst

'ALS161B AND 'AS161 BINARY COUNTERS WITH DIRECT CLEAR

CLR LOAD ENT ENP CLK 1 9 10 7 2 3 A B C D CTRDIV16 CT=0 M1 M2 G3 G4 C5/2,3,4+ 3CT=15 15 RCO 1, 5D [1] [2] [4] [8] 14 QA 13 QB 12 QC 11 QD

'ALS163B AND 'AS163 BINARY COUNTERS WITH SYNCHRONOUS CLEAR

CLR LOAD ENT ENP CLK 1 9 10 7 2 3 A B C D CTRDIV16 5CT=0 M1 M2 G3 G4 C5/2,3,4+ 3CT=15 15 RCO 1, 5D [1] [2] [4] [8] 14 QA 13 QB 12 QC 11 QD

SN54ALS162B DECADE COUNTER WITH SYNCHRONOUS CLEAR

CLR LOAD ENT ENP CLK 1 9 10 7 2 3 A B C D CTRDIV10 5CT=0 M1 M2 G3 G4 C5/2,3,4+ 3CT=9 15 RCO 1, 5D [1] [2] [4] [8] 14 QA 13 QB 12 QC 11 QD

^ These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, and N packages.

logic diagram (positive logic)

graph TD
    LOAD["LOAD 9"] --> AND1["AND"]
    ENT["ENT 10"] --> AND1
    ENP["ENP 7"] --> AND1
    CLR["CLR 1"] --> NOT1["NOT"]
    NOT1 --> AND1
    CLK["CLK 2"] --> AND2["AND"]
    A["A 3"] --> AND3["AND"]
    B["B 4"] --> AND4["AND"]
    C["C 5"] --> AND5["AND"]
    D["D 6"] --> AND6["AND"]
    AND1 --> OR1["OR"]
    AND2 --> OR1
    AND3 --> OR1
    AND4 --> OR1
    AND5 --> OR1
    AND6 --> OR1
    OR1 --> C1C["C1 1D"]
    C1C --> OR2["OR"]
    OR2 --> QA["QA 14"]
    OR2 --> QB["QB 13"]
    OR2 --> QC["QC 12"]
    OR2 --> QD["QD 11"]
    QD --> C1D["C1 1D"]
    C1D --> OR3["OR"]
    OR3 --> QA
    QD --> OR4["OR"]
    OR4 --> QB
    QD --> OR5["OR"]
    OR5 --> QA
    QD --> OR6["OR"]
    OR6 --> QA
    RCO["RCO"] --> AND1
    QA --> OR1
    QB --> OR2
    QC --> OR3
    QD --> OR4
    QD --> OR5

Pin numbers shown are for the J package.

logic diagram (positive logic)

graph TD
    subgraph Input Lines
        CLR["CLR"] -->|1| AND1["AND"]
        LOAD["LOAD"] -->|9| AND1
        ENT["ENT"] -->|10| AND2["AND"]
        ENP["ENP"] -->|7| AND2
        CLK["CLK"] -->|2| AND3["AND"]
        A["A"] -->|3| AND4["AND"]
        B["B"] -->|4| AND5["AND"]
        C["C"] -->|5| AND6["AND"]
        D["D"] -->|6| AND7["AND"]
    end

    AND1 --> OR1["OR"]
    AND2 --> OR1
    AND3 --> OR1
    AND4 --> OR1
    AND5 --> OR1
    AND6 --> OR1
    AND7 --> OR1
    OR1 --> C1_1D["C1 1D"]
    C1_1D --> QA["QA"]
    OR1 --> C1_1D_C1_1D
    C1_1D_C1_1D --> QB["QB"]
    OR1 --> C1_1D_C1_1D
    C1_1D_C1_1D --> QC["QC"]
    OR1 --> C1_1D_C1_1D
    C1_1D_C1_1D --> QD["QD"]
    OR1 --> C1_1D_C1_1D
    C1_1D_C1_1D --> RCO["RCO"]
    QA --> OR1
    QB --> OR1
    QC --> OR1
    QD --> OR1
    RCO --> OR1
    style CLK fill:#f9f,stroke:#333
    style A fill:#ccf,stroke:#333
    style B fill:#cfc,stroke:#333
    style C fill:#fcc,stroke:#333
    style D fill:#cff,stroke:#333
    style OR1 fill:#ffc,stroke:#333
    style C1_1D fill:#cfc,stroke:#333
    style QC fill:#fcc,stroke:#333

Pin numbers shown are for the D, DB, J, and N packages.
'ALS161B and 'AS161 synchronous binary counters are similar; however, CLR is asynchronous.

typical clear, preset, count, and inhibit sequences

SN54ALS162B

The following sequence is illustrated below:

1. Clear outputs to zero (SN54ALS162B is synchronous)
2. Preset to BCD 7
3. Count to 8, 9, 0, 1, 2, and 3
4. Inhibit

typical clear, preset, count, and inhibit sequences

'ALS161B, 'AS161, 'ALS163B, and 'AS163

The following sequence is illustrated below:

1. Clear outputs to zero ('ALS161B and 'AS161 are asynchronous; 'ALS163B and 'AS163 are synchronous.)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit

absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ^†

Supply voltage range, V_CC -0.5 V to 7 V

Input voltage range, V_I -0.5 V to 7 V

Package thermal impedance, _JA (see Note 1): D package 73°C/W

DB package 82°C/W

N package 67°C/W

Storage temperature range, T_stg –65°C to 150°C

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions

		SN54ALS161BSN54ALS162BSN54ALS163B			SN74ALS161BSN74ALS163B			UNIT
		MIN	NOM	MAX	MIN	NOM	MAX
V_CC	Supply voltage	4.5	5	5.5	4.5	5	5.5	V
V_IH	High-level input voltage	2			2			V
V_IL	Low-level input voltage			0.7			0.8	V
I_OH	High-level output current			-0.4			-0.4	mA
I_OL	Low-level output current			4			8	mA
T_A	Operating free-air temperature	-55		125	0		70	°C

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS		SN54ALS161BSN54ALS162BSN54ALS163B			SN74ALS161BSN74ALS163B			UNIT
			MIN	TYP‡	MAX	MIN	TYP‡	MAX
V_IK	V_CC = 4.5 V, I_I = -18 mA				-1.5			-1.5	V
V_OH	V_CC = 4.5 V to 5.5 V, I_OH = -0.4 mA		V_CC - 2			V_CC - 2			V
V_OL	V_CC = 4.5 V	I_OL = 4 mA		0.25	0.4		0.25	0.4	V
		I_OL = 8 mA					0.35	0.5
I_I	V_CC = 5.5 V, V_I = 7 V				0.1			0.1	mA
I_IH	V_CC = 5.5 V, V_I = 2.7 V				20			20	A
I_IL	V_CC = 5.5 V, V_I = 0.4 V				-0.2			-0.2	mA
I_O^S	V_CC = 5.5 V, V_O = 2.25 V		-20		-112	-30		-112	mA
I_CC	V_CC = 5.5 V			12	21		12	21	mA

All typical values are at V_CC = 5 V, T_A = 25^ .
§ The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, .

timing requirements over recommended operating conditions (unless otherwise noted) (see Figure 1)

				SN54ALS161BSN54ALS162BSN54ALS163B	SN74ALS161BSN74ALS163B	UNIT
				MIN MAX MIN	MAX
f_clock	Clock frequency 22 40 MHz
t_w	Pulse duration	CLR high or low 20 12.5				ns
		'ALS161B CLR low 20 15
t_su	Setup time, before CLK↑	A, B, C, D 50 15				ns
		LOAD 20 15
		'ALS161B	ENP, ENT	25 15
		SN54ALS162B, 'ALS163B		20 15
		'ALS161B CLR inactive 10 10
		SN54ALS162B, 'ALS163B	CLR low 20 15
			CLR high 20 10
t_h	Hold time, all synchronous inputs after CLK↑			0	0	ns

switching characteristics over recommended operating conditions (unless otherwise noted) (see Figure 1)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	SN54ALS161B		SN74ALS161B		UNIT
			MIN MAX MIN		MAX
f_max			22 40		MHz
t_PLH	CLK	RCO	5	34	5	20	ns
t_PHL			5	27	5	20
t_PLH	CLK	Any Q	4	19	4	15	ns
t_PHL			6	25	6	20
t_PLH	ENT	RCO	3	18	3	13	ns
t_PHL			3	17	3	13
t_PHL		Any Q	8	27	8	24	ns
		RCO	11	32	11	23

switching characteristics over recommended operating conditions (unless otherwise noted) (see Figure 1)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	SN54ALS162BSN54ALS163B		SN74ALS163B		UNIT
			MIN MAX MIN		MAX
f_max			22 40		MHz
tPLH	CLK	RCO	5	25	5	20	ns
tPHL			5	25	5	20
tPLH	CLK	Any Q	4	18	4	15	ns
tPHL			6	25	6	20
tPLH	ENT	RCO	3	16	3	13	ns
tPHL			3	16	3	13

recommended operating conditions

		SN54AS161SN54AS163	SN74AS161SN74AS163	UNIT
		MIN NOM MAX MIN N	NOM MAX
V_CC	Supply voltage 4.5 5 5.5 4.5 5 5.5 V
V_IH	High-level input voltage 2 2 V
V_IL	Low-level input voltage 0.8 0.8 V
I_OH	High-level output current -2 -2 mA
I_OL	Low-level output current 20 20 mA
T_A	Operating free-air temperature	-55 125	0 70	°C

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		SN54AS161SN54AS163			SN74AS161SN74AS163			UNIT
				MIN	TYP†	MAX	MIN	TYP	† MAX
V_IK		V_CC=4.5 V, I_I=-18 mA		-1.2			-1.2			V
V_OH		V_CC=4.5 V to 5.5 V, I_OH=-2 mA		V_CC-2			V_CC-2			V
V_OL		V_CC=4.5 V, I_OL=20 mA		0.25	0.5		0.25	0.5 V
I_I		V_CC=5.5 V, V_I=7 V		0.3			0.3			mA
	ENT			0.2			0.2
	All others			0.1			0.1
I_IH		V_CC=5.5 V, V_I=2.7 V		60			60			A
	ENT			40			40
	All others			20			20
I_IL		V_CC=5.5 V, V_I=0.4 V		-1.5			-1.5			mA
	ENT			-1			-1
	All others			-0.5			-0.5
I_O^		V_CC=5.5 V, V_O=2.25 V		-30	-112		-30	-112		mA
I_CC		V_CC=5.5 V		35	53		35	53		mA

All typical values are at V_CC = 5 V, T_A = 25^ .
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.

timing requirements over recommended operating conditions (see Figure 1)

				SN54AS161SN54AS163	SN74AS161SN74AS163	UNIT
				MIN MAX MIN	MAX
f_clock	Clock frequency 65 75 MHz
t_w	Pulse duration	high or low 7.7 6.7				ns
		'AS161 CLR low 10 8
t_su	Setup time, before CLK↑	A, B, C, D 10 8				ns
		10 8
		ENP, ENT		10 8
		'AS161 CLR inactive 10 8
		'AS163	low 14 12
			high (inactive)	10 9
t_h	Hold time, all synchronous inputs after CLK↑			2	0	ns

switching characteristics over recommended operating conditions (see Figure 1)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	SN54AS161		SN74AS161		UNIT
			MIN MAX MIN		MAX
f_max			65* 75		MHz
tPLH	CLK	RCO (with high)	1	8.5	1	8	ns
		RCO (with low)	3	17.5	3	16.5
tPHL	CLK	RCO	2	14	2	12.5	ns
tPLH	CLK	Any Q	1	7.5	1	7	ns
tPHL			2	14	2	13
tPLH	ENT	RCO	1.5	10	1.5	9	ns
tPHL			1	9.5	1	8.5
tPHL		Any Q	2	14	2	13	ns
		RCO	2	14	2	12.5

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

switching characteristics over recommended operating conditions (see Figure 1)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	SN54AS163		SN74AS163		UNIT
			MIN MAX MIN		MAX
f_max			65° 75		MHz
t_PLH	CLK	RCO (with LOAD high)	1	8.5	1	8	ns
		RCO (with LOAD low)	3	17.5	3	16.5
t_PHL	CLK	RCO	2	14	2	12.5	ns
t_PLH	CLK	Any Q	1	7.5	1	7	ns
t_PHL			2	14	2	13
t_PLH	ENT	RCO	1.5	10	1.5	9	ns
t_PHL			1	9.5	1	8.5

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES

NOTES: A. C L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t_r = t_f = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

APPLICATION INFORMATION

n-bit synchronous counters

This application demonstrates how the ripple-mode carry circuit (see Figure 2) and the carry look-ahead circuit (see Figure 3) can be used to implement a high-speed n-bit counter. The SN54ALS162B counts in BCD. The 'ALS161B,'AS161,'ALS163B, and 'AS163 devices count in binary. When additional stages are added, the f_max decreases in Figure 2, but remains unchanged in Figure 3.

graph TD
    A["Clear (L)"] --> B["LSB"]
    C["Count (H)"] --> B
    D["Disable (L)"] --> B
    E["Clock"] --> B
    B --> F["To More Significant Stages"]
    subgraph LSB
        G1["CLK"] --> H1["1,5D"]
        H1 --> I1["QA"]
        H1 --> J1["QB"]
        H1 --> K1["QC"]
        H1 --> L1["QD"]
        M1["ENP"] --> N1["1,5D"]
        N1 --> O1["QA"]
        N1 --> P1["QB"]
        N1 --> Q1["QC"]
        N1 --> R1["QD"]
        S1["CLK"] --> T1["1,5D"]
        T1 --> U1["QA"]
        T1 --> V1["QB"]
        T1 --> W1["QC"]
        T1 --> X1["QD"]
        Y1["ENP"] --> Z1["1,5D"]
        Z1 --> AA1["QA"]
        Z1 --> AB1["QB"]
        Z1 --> AC1["QC"]
        Z1 --> AD1["QD"]
        AE["CLK"] --> AF["1,5D"]
        AF --> AG1["QA"]
        AF --> AH1["QB"]
        AF --> AI1["QC"]
        AF --> AJ1["QD"]
        AK["ENP"] --> AL["1,5D"]
        AL --> AM1["QA"]
        AL --> AN1["QB"]
        AL --> AO1["QC"]
        AL --> AP1["QD"]
        AQ["CLK"] --> AR["1,5D"]
        AR --> AS1["QA"]
        AR --> AT1["QB"]
        AR --> AU1["QC"]
        AR --> AV1["QD"]
    end

Figure 2. Ripple-Mode Carry Circuit

graph TD
    A["Clock"] --> B["AND"]
    C["Count (H)"] --> D["AND"]
    E["Disable (L)"] --> F["AND"]
    G["Clear (L)"] --> H["AND"]
    I["Load (L)"] --> J["AND"]
    K["CLK"] --> L["AND"]
    M["ENP"] --> N["AND"]
    O["ENT"] --> P["AND"]
    Q["CONT"] --> R["AND"]
    S["CLR"] --> T["AND"]
    U["LOAD"] --> V["AND"]
    W["LSB"] --> X["3CT=MAX"]
    Y["To More Significant Stages"] --> Z["1/CLK to RCO tPLH + (ENP tsu)"]
    style A fill:#f9f,stroke:#333
    style C fill:#f9f,stroke:#333
    style I fill:#f9f,stroke:#333
    style K fill:#f9f,stroke:#333
    style U fill:#f9f,stroke:#333
    style S fill:#f9f,stroke:#333
    style M fill:#f9f,stroke:#333
    style Y fill:#f9f,stroke:#333
    style Z fill:#f9f,stroke:#333

Figure 3. Carry Look-Ahead Circuit

PACKAGING INFORMATION

Orderable Device Status(1)	Package Type Package Drawing	Pins Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4/5)	Samples
83022012A ACTIVE LCCC FK 20 1 Non-RoHS			& Green	SNPB N / A for Pkg Type -55 to 125 83022012A			SNJ54ALS161BFK	Samples
8302201EA ACTIVE CDIP J 16 1 Non-RoHS			& Green	SNPB N / A for Pkg Type -55 to 125 8302201EA			SNJ54ALS161BJ	Samples
8302201FA ACTIVE CFP W 16 1 Non-RoHS			& Green	SNPB N / A for Pkg Type -55 to 125 8302201FA			SNJ54ALS161BW	Samples
83022022A ACTIVE LCCC FK 20 1 Non-RoHS			& Green	SNPB N / A for Pkg Type -55 to 125 83022022A			SNJ54ALS163BFK	Samples
8302202EA ACTIVE CDIP J 16 1 Non-RoHS			& Green	SNPB N / A for Pkg Type -55 to 125 8302202EA			SNJ54ALS163BJ	Samples
JM38510/38001B2A ACTIVE LCCC FK 20 1 Non-RoHS			& Green	SNPB N / A for Pkg Type -55 to 125 JM38510/			38001B2A	Samples
JM38510/38001BEA	ACTIVE CDIP J 16 1 Non-RoHS		& Green	SNPB N / A for Pkg Type -55 to 125 JM38510/			38001BEA	Samples
JM38510/38002B2A ACTIVE LCCC FK 20 1 Non-RoHS			& Green	SNPB N / A for Pkg Type -55 to 125 JM38510/			38002B2A	Samples
JM38510/38002BEA	ACTIVE CDIP J 16 1 Non-RoHS		& Green	SNPB N / A for Pkg Type -55 to 125 JM38510/			38002BEA	Samples
M38510/38001B2A	ACTIVE LCCC FK 20 1 Non-RoHS		& Green	SNPB N / A for Pkg Type -55 to 125 JM38510/			38001B2A	Samples
M38510/38001BEA	ACTIVE CDIP J 16 1 Non-RoHS		& Green	SNPB N / A for Pkg Type -55 to 125 JM38510/			38001BEA	Samples
M38510/38002B2A	ACTIVE LCCC FK 20 1 Non-RoHS		& Green	SNPB N / A for Pkg Type -55 to 125 JM38510/			38002B2A	Samples
M38510/38002BEA	ACTIVE CDIP J 16 1 Non-RoHS		& Green	SNPB N / A for Pkg Type -55 to 125 JM38510/			38002BEA	Samples
SN54ALS161BJ	ACTIVE CDIP J 16 1 Non-RoHS		& Green	SNPB N / A for Pkg Type -55 to 125 SN54ALS161BJ				Samples
SN54ALS163BJ	ACTIVE CDIP J 16 1 Non-RoHS		& Green	SNPB N / A for Pkg Type -55 to 125 SN54ALS163BJ				Samples
SN74ALS161BD	ACTIVE SOIC D	16	40 RoHS & Green	NIPDAU	Level-1-260C-UNLIM	0 to 70	ALS161B	Samples

Addendum-Page 1

Orderable Device Status(1)		Package Type	Package Drawing	Pins	Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4-5)	Samples
SN74ALS161BDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ALS161B											Samples
SN74ALS161BDRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ALS161B											Samples
SN74ALS161BN	ACTIVE	PDIP	N	16	25	RoHS & Green	NIPDAU	N / A for Pkg Type	0 to 70	SN74ALS161BN	Samples
SN74ALS161BNSR	ACTIVE	SO	NS	16	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	0 to 70	ALS161B	Samples
SN74ALS163BD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ALS163B											Samples
SN74ALS163BDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ALS163B											Samples
SN74ALS163BDRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ALS163B											Samples
SN74ALS163BN	ACTIVE	PDIP	N	16	25	RoHS & Green	NIPDAU	N / A for Pkg Type	0 to 70	SN74ALS163BN	Samples
SN74ALS163BNSR	ACTIVE	SO	NS	16	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	0 to 70	ALS163B	Samples
SN74AS161N	ACTIVE	PDIP	N	16	25	RoHS & Green	NIPDAU	N / A for Pkg Type	0 to 70	SN74AS161N	Samples
SN74AS161NSR	ACTIVE	SO	NS	16	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	0 to 70	74AS161	Samples
SN74AS163D	ACTIVE	SOIC	D	16	40	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	0 to 70	AS163	Samples
SN74AS163N	ACTIVE	PDIP	N	16	25	RoHS & Green	NIPDAU	N / A for Pkg Type	0 to 70	SN74AS163N	Samples
SN74AS163NE4	ACTIVE	PDIP	N	16	25	RoHS & Green	NIPDAU	N / A for Pkg Type	0 to 70	SN74AS163N	Samples
SNJ54ALS161BFK	ACTIVE	LCCC	FK	20	1	Non-RoHS & Green	SNPB N / A for Pkg Type	-55 to 125	83022012A SNJ54ALS 161BFK	SNJ54ALS 161BFK	Samples
SNJ54ALS161BJ ACTIVE CDIP J 16	1 Non-RoHS						SNPB N / A for Pkg Type	-55 to 125	8302201EA SNJ54ALS161BJ	SNJ54ALS161BJ	Samples
SNJ54ALS161BW	ACTIVE	CFP	W	16	1	Non-RoHS & Green	SNPB N / A for Pkg Type	-55 to 125	8302201FA SNJ54ALS161BW	SNJ54ALS161BW	Samples
SNJ54ALS163BFK	ACTIVE	LCCC	FK	20	1	Non-RoHS & Green	SNPB N / A for Pkg Type	-55 to 125	83022022A SNJ54ALS 163BFK	SNJ54ALS 163BFK	Samples
SNJ54ALS163BJ ACTIVE CDIP J 16	1 Non-RoHS						SNPB N / A for Pkg Type	-55 to 125	8302202EA SNJ54ALS163BJ	SNJ54ALS163BJ	Samples

Orderable Device Status(1)	Package Type Package Drawing	Pins Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4-5)	Samples
SNJ54AS161J ACTIVE CDIP J 16 1 Non-RoHS			& Green	SNPB N / A for Pkg Type -55 to 125 SNJ54AS161J				Samples

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "-" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54ALS161B, SN54ALS163B, SN54AS161, SN74ALS161B, SN74ALS163B, SN74AS161 :

TEXAS

INSTRUMENTS

www.ti.com

PACKAGE OPTION ADDENDUM

21-Aug-2021

• Catalog : SN74ALS161B, SN74ALS163B, SN74AS161
• Military : SN54ALS161B, SN54ALS163B, SN54AS161

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

Package Drawing

Pins

SPQ Reel

Diameter (mm)

Reel Width W1 (mm)

A0 (mm)

B0 (mm)

K0 (mm)

P1 (mm)

W (mm)

Pin1 Quadrant

SN74ALS161BDR SO

C D 16 25

00 330.0 1

6.4 6.5

10.3 2.1

8.0 16.0 Q1

SN74ALS161BNSR SO

NS 16 20

00 330.0 1

6.4 8.2

10.5 2.5

12.0 16.0 Q1

SN74ALS163BDR SO

C D 16 25

00 330.0 1

6.4 6.5

10.3 2.1

8.0 16.0 Q1

SN74ALS163BNSR SO

NS 16 20

00 330.0 1

6.4 8.2

10.5 2.5

12.0 16.0 Q1

SN74AS161NSR SO

NS 16 200

00 330.0 16

4.8.2

10.5 2.5

12.0 16.0 Q1

TAPE AND REEL BOX DIMENSIONS W L

*All dimensions are nominal

Device	Package Type	Package Drawing	Pins	SPQ	Length (mm)	Width (mm)	Height (mm)
SN74ALS161BDR SOIC	D 16 2500 340.5	336.1 32.0
SN74ALS161BNSR SO	NS 16 2000 853.0	449.0 35.0
SN74ALS163BDR SOIC	D 16 2500 340.5	336.1 32.0
SN74ALS163BNSR SO	NS 16 2000 853.0	449.0 35.0
SN74AS161NSR	SO NS 16	2000 853.0 449.0 35.0

TUBE

T - Tube height W-Tube width L - Tube length B - Alignment groove width

*All dimensions are nominal

Device	Package Name	Package Type	Pins	SPQ	L (mm)	W (mm)	T (μm)	B (mm)
83022012A FK LCQ	C 20 1 506.98 12.06	2030 NA
83022022A FK LCQ	C 20 1 506.98 12.06	2030 NA
JM38510/38001B2A FK	LCCC 20 1 506.98	12.06 2030 NA
JM38510/38002B2A FK	LCCC 20 1 506.98	12.06 2030 NA
M38510/38001B2A FK	LCCC 20 1 506.98	12.06 2030 NA
M38510/38002B2A FK	LCCC 20 1 506.98	12.06 2030 NA
SN74ALS161BD	D	SOIC	16	40	507	8	3940	4.32
SN74ALS161BN	N	PDIP	16	25	506	13.97	11230	4.32
SN74ALS161BN	N	PDIP	16	25	506	13.97	11230	4.32
SN74ALS163BD	D	SOIC	16	40	507	8	3940	4.32
SN74ALS163BN	N	PDIP	16	25	506	13.97	11230	4.32
SN74ALS163BN	N	PDIP	16	25	506	13.97	11230	4.32
SN74AS161N	N	PDIP	16	25	506	13.97	11230	4.32
SN74AS161N	N	PDIP	16	25	506	13.97	11230	4.32
SN74AS163D	D	SOIC	16	40	507	8	3940	4.32
SN74AS163N	N	PDIP	16	25	506	13.97	11230	4.32
SN74AS163N	N	PDIP	16	25	506	13.97	11230	4.32
SN74AS163NE4	N	PDIP	16	25	506	13.97	11230	4.32
SN74AS163NE4	N	PDIP	16	25	506	13.97	11230	4.32
SNJ54ALS161BFK FK	LCCC 20 1 506.98	12.06 2030 NA
SNJ54ALS163BFK FK	LCCC 20 1 506.98	12.06 2030 NA

SOP

4220735/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

SOP

16X (1.85) 1 16X (0.6) SYMM SEE DETAILS 16 SYMM 14X (1.27) 8 (R0.05) TYP (7)

LAND PATTERN EXAMPLE SCALE:7X

METAL SOLDER MASK OPENING 0.07 MAX ALL AROUND

NON SOLDER MASK DEFINED

SOLDER MASK OPENING METAL 0.07 MIN ALL AROUND

SOLDER MASK DEFINED
SOLDER MASK DETAILS

4220735/A 12/2021

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SOP

16X (1.85) 1 16X (0.6) 14X (1.27) 8 (R0.05) TYP SYMM 16 SYMM 9 (7)

SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X

4220735/A 12/2021

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

FK (S-CQCC-N**)

28 TERMINAL SHOWN

LEADLESS CERAMIC CHIP CARRIER

NO. OF TERMINALS**	A		B
	MIN	MAX	MIN	MAX
20	0.342(8,69)	0.358(9,09)	0.307(7,80)	0.358(9,09)
28	0.442(11,23)	0.458(11,63)	0.406(10,31)	0.458(11,63)
44	0.640(16,26)	0.660(16,76)	0.495(12,58)	0.560(14,22)
52	0.740(18,78)	0.761(19,32)	0.495(12,58)	0.560(14,22)
68	0.938(23,83)	0.962(24,43)	0.850(21,6)	0.858(21,8)
84	1.141(28,99)	1.165(29,59)	1.047(26,6)	1.063(27,0)

4040140/D 01/11
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. Falls within JEDEC MS-004

D (R-PDSO-G16)
PLASTIC SMALL OUTLINE

0.394 (10,00) 0.386 (9,80) 16 9 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,80) Pin 1 Index Area 1 8 0.050 (1,27) 0.020 (0,51) 0.012 (0,31) ⊕ 0.010 (0,25) M 0.069 (1,75) Max 0.010 (0,25) 0.004 (0,10) Gcuge Plane 0.010 (0,25) 0.005 (0,13) 0'-8" Seating Plane 0.010 (0,25) 0.050 (1,27) 0.016 (0,40) 4040047-6/M 06/11

NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.006 (0,15) each side.
Body width does not include interlead flash. Interlead flash shall not exceed 0.017 (0,43) each side.
E. Reference JEDEC MS-012 variation AC.

D (R-PDSO-G16)

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate designs.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

MECHANICAL DATA

NS (R-PDSO-G\*\*)

PLASTIC SMALL-OUTLINE PACKAGE

14-PINS SHOWN

1,27 14 0,51 0,35 Ø 0,25① 8 5,60 5,00 8,20 7,40 1 7 A

0,15 NOM Gage Plane 0,25 0°-10° 1,05 0,55

2,00 MAX 0,15 0,05

Seating Plane 0.10

DIM\PINS **	14	16	20	24
A MAX	10,50	10,50	12,90	15,30
A MIN	9,90	9,90	12,30	14,70

4040062/C 03/03

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.

W (R-GDFP-F16)

CERAMIC DUAL FLATPACK

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification only.

E. Falls within MIL STD 1835 GDFP2-F16

B 14 8 C 1 0.065 (1,65) 0.045 (1,14)

PINS **DIM	14	16	18	20
A	0.300(7,62)BSC	0.300(7,62)BSC	0.300(7,62)BSC	0.300(7,62)BSC
B MAX	0.785(19,94)	.840(21,34)	0.960(24,38)	1.060(26,92)
B MIN	—	—	—	—
C MAX	0.300(7,62)	0.300(7,62)	0.310(7,87)	0.300(7,62)
C MIN	0.245(6,22)	0.245(6,22)	0.220(5,59)	0.245(6,22)

0.005 (0,13) MIN 0.060 (1,52) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.026 (0,66) 0.014 (0,36) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) A 0°-15°

4040083/F 03/03

NOTES:

A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package is hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18 and GDIP1-T20.

N (R-PDIP-T\*\*)

16 PINS SHOWN

PLASTIC DUAL-IN-LINE PACKAGE

A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) 0.045 (1,14)

C

DIM\PINS **	14	16	18	20
A MAX	0.775(19,69)	0.775(19,69)	0.920(23,37)	1.060(26,92)
A MIN	0.745(18,92)	0.745(18,92)	0.850(21,59)	0.940(23,88)
MS-001VARIATION	AA	BB	AC	AD

0.045 (1,14) 0.030 (0,76) D 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) ⊕ 0.010 (0,25) M 14/18 Pin Only 20 Pin vendor opt

0.325 (8,26) 0.300 (7,62) 0.015 (0,38) Gauge Plane 0.010 (0,25) NOM 0.430 (10,92) MAX

4040049/E 12/2002

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C Falls within JEDEC MS-001, except 18 and 20 pin minimum body length (Dim A).

The 20 pin end lead shoulder width is a vendor option, either half or full width.

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