SN74HC241N - Electronic component TEXAS INSTRUMENTS - Free user manual and instructions

USER MANUAL SN74HC241N TEXAS INSTRUMENTS

SNx4HC241 Octal Buffers and Line Drivers With 3-State Outputs

1 Features

• Wide operating voltage range of 2 V to 6 V
  • High-current outputs drive up to 15 LSTTL loads
• Low power consumption, 80-μA max I cc
  • Typical t _pd =11 ns
• ±6-mA output drive at 5 V
• Low input current of 1 A max
  • 3-state outputs drive bus lines or buffer memory address registers

2 Description

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The 'HC241 devices are organized as two 4-bit buffers/drivers with separate output-enable (1OE and 2OE) inputs. When 1OE is low or 2OE is high, the device passes noninverted data from the A inputs to the Y outputs. When 1OE is high or 2OE is low, the outputs for the respective buffers/drivers are in the high-impedance state.

Device Information

PART NUMBER PACKAGE (1)		BODY SIZE (NOM)
SN74HC241DW SOIC (20) 12.80 mm × 7.50 mm
SN74HC241N PDIP (20) 25.40 mm × 6.35 mm
SN74HC241NSR	SO (20)	15.00 mm × 5.30 mm
SN74HC241PW	TSSOP (20)	6.50 mm × 4.40 mm
SN54HC241J	CDIP (20)	26.92 mm × 6.92 mm
SNJ54HC241FK	LCCC (20)	8.89 mm × 8.45 mm

(1) For all available packages, see the orderable addendum at the end of the data sheet.

graph TD
    A["1OE"] -->|1| B["NOT"]
    C["1A1"] -->|2| D["NOT"]
    E["1A2"] -->|4| F["NOT"]
    G["1A3"] -->|6| H["NOT"]
    I["1A4"] -->|8| J["NOT"]
    B --> K["18"]
    D --> L["16"]
    F --> M["14"]
    H --> N["12"]
    J --> O["1Y4"]
    style A fill:#f9f,stroke:#333
    style C fill:#f9f,stroke:#333
    style E fill:#f9f,stroke:#333
    style G fill:#f9f,stroke:#333
    style I fill:#f9f,stroke:#333
    style K fill:#ccf,stroke:#333
    style L fill:#ccf,stroke:#333
    style M fill:#ccf,stroke:#333
    style N fill:#ccf,stroke:#333
    style O fill:#ccf,stroke:#333

graph TD
    A["2OE"] --> B["19"]
    C["2A1"] --> D["11"]
    E["2A2"] --> F["13"]
    G["2A3"] --> H["15"]
    I["2A4"] --> J["17"]
    B --> K["9"]
    D --> L["7"]
    F --> M["5"]
    H --> N["3"]
    J --> O["2Y4"]
    K --> P["2Y1"]
    L --> Q["2Y2"]
    M --> R["2Y3"]
    N --> S["2Y4"]

Functional Block Diagram

Table of Contents

1 Features....1
2 Description....1
3 Revision History....2
4 Pin Configuration and Functions....3
5 Specifications....4
5.1 Absolute Maximum Ratings.... 4
5.2 Recommended Operating Conditions ^(1) 4
5.3 Thermal Information....4
5.4 Electrical Characteristics....5
5.5 Switching Characteristics .... 5
5.6 Switching Characteristics....6
5.7 Operating Characteristics.... 6
6 Parameter Measurement Information....7
7 Detailed Description....8

7.1 Overview....8
7.2 Functional Block Diagram....8
7.3 Device Functional Modes......8

8 Power Supply Recommendations....9

9 Layout....9

9.1 Layout Guidelines.... 9

10 Device and Documentation Support....10

10.1 Receiving Notification of Documentation Updates..10
10.2 Support Resources.... 10
10.3 Trademarks....10
10.4 Electrostatic Discharge Caution....10
10.5 Glossary....10

11 Mechanical, Packaging, and Orderable Information.... 10

3 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (August 2003) to Revision D (January 2022) Page

- Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standards....1

4 Pin Configuration and Functions

1OE 1 20 VCC 1A1 2 19 2OE 2Y4 3 18 1Y1 1A2 4 17 2A4 2Y3 5 16 1Y2 1A3 6 15 2A3 2Y2 7 14 1Y3 1A4 8 13 2A2 2Y1 9 12 1Y4 GND 10 11 2A1

J, DW, N, NS, or PW package 20-Pin CDIP, SOIC, PDIP, SO, or TSSOP Top View

2Y4 1A1 1OE VCC 2OE 1A2 3 2 1 20 19 1Y1 4 18 2Y3 5 17 1A3 6 16 2Y2 7 15 2A3 8 14 1A4 9 10 11 12 13 1Y3 2Y1 GND 2A1 1Y4 2A2

FK Package
20-Pin LCCC
Top View

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ^(1)

			MIN MAX UNIT
V_CC	Supply voltage range -0.5 7 V
I_IK	Input clamp current(2)	V_I < 0 or V_I > V_CC	±20 mA
I_OK	Output clamp current(2)	V_O < 0 or V_O > V_CC	±20 mA
I_O	Continuous output current V	_O = 0 to V_CC	±35 mA
	Continuous current through V_CC or GND ±70 mA
T_J	Junction temperature 150 °C
T_stg	Storage temperature range -65 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

5.2 Recommended Operating Conditions ^(1)

			SN54HC241 SN74HC241					UNIT
			MIN NOM MAX	MIN	NOM MAX
V_CC	Supply voltage		2	5	6	2	5	6
V_IH	High-level input voltage	V_CC=2 V	1.5			1.5
		V_CC=4.5 V	3.15			3.15
		V_CC=6 V	4.2			4.2
V_IL	Low-level input voltage	V_CC=2 V			0.5			0.5
		V_CC=4.5 V			1.35			1.35
		V_CC=6 V			1.8			1.8
V_I	Input voltage		0		V_CC	0		V_CC
V_O	Output voltage		0		V_CC	0		V_CC
t/ v	Input transition rise/fall time	V_CC=2 V			1000			1000
		V_CC=4.5 V			500			500
		V_CC=6 V			400			400
T_A	Operating free-air temperature		-55		125	-40		85

(1) All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

5.3 Thermal Information

THERMAL METRIC		DW (SOIC)	N (PDIP)	NS (SO)	PW (TSSOP)	UNIT
		20 PINS	20 PINS	20 PINS	20 PINS
R_ JA	Junction-to-ambient thermal resistance(1)	58	69	60	83	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report.

5.4 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS V		cc	T_A=25°C SN54HC241 SN74HC241			UNIT
				MIN TYP MAX MIN MAX MIN MAX
V_OH	V_I=V_IH or V_IL	I_OH=-20 μA	2 V 1.9 1.998 1.9 1.9				V
			4.5 V 4.4 4.499 4.4 4.4
			6 V 5.9 5.999 5.9 5.9
		I_OH=-6 mA 4.5	V 3.98 4.3 3.7 3.84
		I_OH=-7.8 mA 6	V 5.48 5.8 5.2 5.34
V_OL	V_I=V_IH or V_IL	I_OL=20 μA	2 V	0.002 0.1 0.1 0.1			V
			4.5 V	0.001 0.1 0.1 0.1
			6 V	0.001 0.1 0.1 0.1
		I_OL=6 mA	4.5 V	0.17 0.26 0.4 0.33
		I_OL=7.8 mA	6 V	0.15 0.26 0.4 0.33
I_I	V_I=V_CC or 0		6 V	±0.1 ±100	±1000	±1000	nA
I_OZ	V_O=V_CC or 0		6 V	±0.01 ±0.5	±10	±5	μA
I_CC	V_I=V_CC or 0,	I_O=0	6 V	8	160	80	μA
C_I			2 V to 6 V	3 10	10	10	pF

5.5 Switching Characteristics

over recommended operating free-air temperature range, C_L = 50 pF (unless otherwise noted) (see Parameter Measurement Information)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	V_cc	T_A=25°C			SN54HC241		SN74HC241		UNIT
				MIN	TYP	MAX	MIN	MAX	MIN	MAX
t_pd	A	Y	2 V		39 115		170		145		ns
			4.5 V		12	23		34		29
			6 V		11 20		29		25
t_en	or OE	Y	2 V		60	150		225		190	ns
			4.5 V		17	30		45		38
			6 V		15 26		38		32
t_dis	or OE	Y	2 V		40	150		225		190	ns
			4.5 V		18	30		45		38
			6 V		17 26		38		32
t_t		Y	2 V		28 60		90		75		ns
			4.5 V		8	12		18		15
			6 V		6 10		15		13

5.6 Switching Characteristics

over recommended operating free-air temperature range, C_L = 150 pF (unless otherwise noted) (see Parameter Measurement Information)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	V_cc	T_A = 25°C SN54HC241 SN74HC241			UNIT
				MIN TYP MAX MIN MAX	MIN MAX
t_pd	A	Y	2 V 50	165 245 210			ns4.5 V 16 33 49 42
			6 V 14	28 42 35
t_en	OE or OE Y		2 V 100	200 300 250			ns4.5 V 20 40 60 50
			6 V 17	34 51 43
t_t		Y	2 V 45	210 315 265			ns4.5 V 17 42 63 53
			6 V 13	36 53 45

5.7 Operating Characteristics

T_A = 25^

PARAMETER		TEST CONDITIONS	TYP	UNIT
C_pd	Power dissipation capacitance per buffer/driver	No load	35	pF

6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z_O = 50 , t_t < 6 ns.

For clock inputs, f_max is measured when the input duty cycle is 50%.

The outputs are measured one at a time with one input transition per measurement.

From Output Under Test Test Point Vcc RL CL(1) S1 S2

(1) C_L includes probe and test-fixture capacitance.

Figure 6-1. Load Circuit for 3-State Outputs

50%Input 50% Output 50% 50% tPLH(1) tPHL(1) VCC 0 V VOH VOL tPHL(1) tPLH(1) VOH Output 50% 50% VOL

(1) The greater between t_PLH and t_PHL is the same as t_pd .

Figure 6-2. Voltage Waveforms, Propagation Delays for Standard CMOS Inputs

(1) t_PLZ and t_PHZ are the same as t_dis .
(2) t_PZL and t_PZH are the same as t_en .

Figure 6-3. Voltage Waveforms, Standard CMOS Inputs Propagation Delays

Input 90% 90% VCC 10% t_r^(1) 10% t_f^(1) 0 V Output 90% 90% VCH 10% t_r^(1) 10% t_f^(1) VOL

(1) The greater between t_r and t_f is the same as t_t .

Figure 6-4. Voltage Waveforms, Input and Output Transition Times for Standard CMOS Inputs

7 Detailed Description

7.1 Overview

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The 'HC241 devices are organized as two 4-bit buffers/drivers with separate output-enable (1OE and 2OE) inputs. When 1OE is low or 2OE is high, the device passes noninverted data from the A inputs to the Y outputs. When 1OE is high or 2OE is low, the outputs for the respective buffers/drivers are in the high-impedance state.

7.2 Functional Block Diagram

graph TD
    A["10E"] -->|1| B["NOT"]
    C["1A1"] -->|2| D["AND"]
    E["1A2"] -->|4| F["AND"]
    G["1A3"] -->|6| H["AND"]
    I["1A4"] -->|8| J["AND"]
    D -->|18| K["1Y1"]
    F -->|16| L["1Y2"]
    H -->|14| M["1Y3"]
    J -->|12| N["1Y4"]

graph TD
    A["2OE"] --> B["19"]
    C["2A1"] --> D["11"]
    E["2A2"] --> F["13"]
    G["2A3"] --> H["15"]
    I["2A4"] --> J["17"]
    B --> K["9"]
    D --> L["7"]
    F --> M["5"]
    H --> N["3"]
    J --> O["2Y4"]
    K --> P["2Y1"]
    L --> Q["2Y2"]
    M --> R["2Y3"]
    N --> S["2Y4"]

7.3 Device Functional Modes

Table 7-1. Function Table

INPUTS		OUTPUT1Y
1OE 1A
LHH
LLL
HXZ

Table 7-2. Function Table

INPUTS		OUTPUT2Y
2OE 2A
H H H
H L L
L X Z

8 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each V_CC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1- F capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1- F and 1- F capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results.

9 Layout

9.1 Layout Guidelines

When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or V CC, whichever makes more sense for the logic function or is more convenient.

10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

10.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.3 Trademarks

TI E2E ^TM is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

10.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGING INFORMATION

Orderable Device Status(1)		Package Type	Package Drawing	Pins	Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4/5)	Samples
JM38510/65704BRA ACTIVE CDIP J 20 1 Non-RoHS						& Green	SNPB N / A for Pkg Type -55 to 125 JM38510/			65704BRA	Samples
M38510/65704BRA ACTIVE CDIP J 20 1 Non-RoHS						& Green	SNPB N / A for Pkg Type -55 to 125 JM38510/			65704BRA	Samples
SN54HC241J ACTIVE CDIP J 20 1 Non-RoHS						& Green	SNPB N / A for Pkg Type -55 to 125 SN54HC241J				Samples
SN74HC241DW	ACTIVE	SOIC	DW	20	25	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HC241	Samples
SN74HC241DWE4	ACTIVE	SOIC	DW	20	25	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HC241	Samples
SN74HC241DWR	ACTIVE	SOIC	DW	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HC241	Samples
SN74HC241DWRG4	ACTIVE	SOIC	DW	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HC241	Samples
SN74HC241N	ACTIVE	PDIP	N	20	20	RoHS & Non-Green	NIPDAU	N / A for Pkg Type	-40 to 85	SN74HC241N	Samples
SN74HC241NSR	ACTIVE	SO	NS	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HC241	Samples
SN74HC241PW	ACTIVE	TSSOP	PW	20	70	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HC241	Samples
SN74HC241PWG4	ACTIVE	TSSOP	PW	20	70	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HC241	Samples
SN74HC241PWR	ACTIVE	TSSOP	PW	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HC241	Samples
SN74HC241PWRE4	ACTIVE	TSSOP	PW	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	HC241	Samples
SNJ54HC241FK	ACTIVE LCCC FK 20 1 Non-RoHS					& Green	SNPB N / A for Pkg Type -55 to 125 SNJ54HC			241FK	Samples
SNJ54HC241J	ACTIVE CDIP J 20 1 Non-RoHS					& Green	SNPB N / A for Pkg Type -55 to 125 SNJ54HC241J				Samples

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".
RoHS Exempt: Ti defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "\~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54HC241, SN74HC241 :

• Catalog : SN74HC241

• Military : SN54HC241

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

Package Drawing

Pins

SPQ Reel

Diameter (mm)

Reel Width W1 (mm)

A0 (mm)

B0 (mm)

K0 (mm)

P1 (mm)

W (mm)

Pin1 Quadrant

SN74HC241DWR SO

C DW 20

2000 330.0

24.4

10.8 13.3 2

2.7 12.0 24

0 Q1

SN74HC241NSR SO

NS 20 2000

330.0 24

4.8.4

13.0 2.5 1

2.0 24.0 Q1

SN74HC241PWR TSS

OP PW 20

2000 330

0 16.4

6.95 7.1

1.6 8.0

16.0 Q1

TAPE AND REEL BOX DIMENSIONS W L

*All dimensions are nominal

Device	Package Type	Package Drawing	Pins	SPQ	Length (mm)	Width (mm)	Height (mm)
SN74HC241DWR SOIC	DW 20 2000 367.0	367.0 45.0
SN74HC241NSR SO	NS 20 2000 367.0	367.0 45.0
SN74HC241PWR TSSOP	PW 20 2000 853.0	449.0 35.0

TUBE

T - Tube height L - Tube length W-Tube width B - Alignment groove width

*All dimensions are nominal

Device	Package Name	Package Type	Pins	SPQ	L (mm)	W (mm)	T (μm)	B (mm)
SN74HC241DW DW	SOIC 20 25 507 12.8	3 5080 6.6
SN74HC241DWE4 DW	SOIC 20 25 507 12	83 5080 6.6
SN74HC241N	N	PDIP	20	20	506	13.97	11230	4.32
SN74HC241PW	PW TSSOP	20 70 530	10.2 3600	3.5
SN74HC241PWG4 PW	TSSOP 20 70 530	10.2 3600	3.5
SNJ54HC241FK	FK	LCCC	20	1	506.98	12.06	2030	NA

SMALL OUTLINE PACKAGE

A 6.6 TYP 6.2 PIN 1 INDEX AREA 1 20 18X 0.65 6.6 6.4 NOTE 3 2X 5.85 10 11 20X 0.30 0.19 B 4.5 4.3 NOTE 4 ⊕ 0.1@ A B

C SEATING PLANE 0.1 C 1.2 MAX

SEE DETAIL A (0.15) TYP

GAGE PLANE 0.25 0.15 0.05 0°-8° 0.75 0.50 DETAIL A TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

SMALL OUTLINE PACKAGE

20X (1.5) 1 20X (0.45) 18X (0.65) 10 (5.8) SYMM (R0.05) TYP 20 SYMM 11

LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN SCALE: 10X

SOLDER MASK OPENING METAL EXPOSED METAL 0.05 MAX ALL AROUND

NON-SOLDER MASK DEFINED (PREFERRED)

METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL 0.05 MIN ALL AROUND

SOLDER MASK DETAILS

4220206/A 02/2017

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SMALL OUTLINE PACKAGE

20X (1.5) 1 20X (0.45) 18X (0.65) 10 (5.8) SYMM (20) (R0.05) TYP SYMM 11

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220206/A 02/2017

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

PW (R-PDSO-G20)

Example Board Layout

18x0,65 5,6 Example Non Soldermask Defined Pad Example Solder Mask Opening (See Note E) 0,3 1,6 0,07 Pad Geometry All Around

Based on a stencil thickness of .127mm (.005inch).

20x0,25 1,55 5,6 18x0,65

4211284-5/G 08/15

NOTES:

A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate design.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

B 14 8 C 1 0.065 (1,65) 0.045 (1,14)

PINS **DIM	14	16	18	20
A	0.300(7,62)BSC	0.300(7,62)BSC	0.300(7,62)BSC	0.300(7,62)BSC
B MAX	0.785(19,94)	.840(21,34)	0.960(24,38)	1.060(26,92)
B MIN	—	—	—	—
C MAX	0.300(7,62)	0.300(7,62)	0.310(7,87)	0.300(7,62)
C MIN	0.245(6,22)	0.245(6,22)	0.220(5,59)	0.245(6,22)

0.005 (0,13) MIN 0.060 (1,52) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.026 (0,66) 0.014 (0,36) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) A 0°-15°

4040083/F 03/03

NOTES:

A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package is hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18 and GDIP1-T20.

N (R-PDIP-T\*\*)

16 PINS SHOWN

PLASTIC DUAL-IN-LINE PACKAGE

A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) 0.045 (1,14)

C

DIM\PINS **	14	16	18	20
A MAX	0.775(19,69)	0.775(19,69)	0.920(23,37)	1.060(26,92)
A MIN	0.745(18,92)	0.745(18,92)	0.850(21,59)	0.940(23,88)
MS-001VARIATION	AA	BB	AC	AD

0.045 (1,14) 0.030 (0,76) D 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) ⊕ 0.010 (0,25) M 14/18 Pin Only 20 Pin vendor opt

0.325 (8,26) 0.300 (7,62) 0.015 (0,38) Gauge Plane 0.010 (0,25) NOM 0.430 (10,92) MAX

4040049/E 12/2002

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C Falls within JEDEC MS-001, except 18 and 20 pin minimum body length (Dim A).

The 20 pin end lead shoulder width is a vendor option, either half or full width.

SOIC

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

SOIC

20X (2) 1 20X (0.6) 18X (1.27) (R0.05) TYP 10 SYMM 20 SYMM 11 (9.3)

LAND PATTERN EXAMPLE SCALE:6X

SOLDER MASK OPENING METAL 0.07 MAX ALL AROUND

NON SOLDER MASK DEFINED

METAL UNDER SOLDER MASK SOLDER MASK OPENING 0.07 MIN ALL AROUND

SOLDER MASK DEFINED
SOLDER MASK DETAILS

4220724/A 05/2016

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SOIC

20X (2) 1 20X (0.6) 18X (1.27) SYMM 20 SYMM 10 (9.3) 11

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

FK (S-CQCC-N**)

28 TERMINAL SHOWN

LEADLESS CERAMIC CHIP CARRIER

NO. OF TERMINALS**	A		B
	MIN	MAX	MIN	MAX
20	0.342(8,69)	0.358(9,09)	0.307(7,80)	0.358(9,09)
28	0.442(11,23)	0.458(11,63)	0.406(10,31)	0.458(11,63)
44	0.640(16,26)	0.660(16,76)	0.495(12,58)	0.560(14,22)
52	0.740(18,78)	0.761(19,32)	0.495(12,58)	0.560(14,22)
68	0.938(23,83)	0.962(24,43)	0.850(21,6)	0.858(21,8)
84	1.141(28,99)	1.165(29,59)	1.047(26,6)	1.063(27,0)

4040140/D 01/11
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. Falls within JEDEC MS-004

MECHANICAL DATA

NS (R-PDSO-G\*\*)

PLASTIC SMALL-OUTLINE PACKAGE

14-PINS SHOWN

1,27 14 0,51 0,35 Ø 0,25① 8 5,60 5,00 8,20 7,40 1 7 A

0,15 NOM Gage Plane 0,25 0°-10° 1,05 0,55

2,00 MAX 0,15 0,05

Seating Plane 0.10

DIM\PINS **	14	16	20	24
A MAX	10,50	10,50	12,90	15,30
A MIN	9,90	9,90	12,30	14,70

4040062/C 03/03

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.

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