SN74AHC125D - Electronic component TEXAS INSTRUMENTS - Free user manual and instructions

USER MANUAL SN74AHC125D TEXAS INSTRUMENTS

SNx4AHC125QuadrupleBusBufferGatesWith3-StateOutputs

1Features

• OperatingRange:2Vto5.5V
  •Latch-UpPerformanceExceeds250mAPer JESD17
  •FourIndividualOutputEnablePins
  •AllInputsHaveSchmitt-TriggerAction

2Applications

• FlowMeters
  •ProgrammableLogicControllers
  •PowerOverEthernet(PoE)
  •MotorDrivesandControls
  •ElectronicPoint-of-Sale

3Description

TheSNx4AHC125devicesarequadruplebusbuffer gatesfeaturingindependentlinedriverswith3-state outputs.Eachoutputisdisabledwhentheassociated output-enable(OE)inputishigh.WhenOEislow,the respectivegatepassethedatafromtheAinputto itsYoutput.

Toensurethehigh-impedancestateduringpowerup orpowerdown,OEmustbetiedtoV cc througha pullupresistor;theminimumvalueoftheresistoris determined by the current-sinking capability of the driver.

DeviceInformation (1)

PARTNUMBERPACKAGE(PINS)		BODYSIZE(NOM)
SNx4AHC125FK	LCCC(20)	8.89mm8.89mm
SNx4AHC125DB	SSOP(14)	6.20mm5.30mm
SNx4AHC125D	SOIC(14)	8.65mm×3.91mm
SNx4AHC125NS	SO(14)	10.30mm×5.30mm
SNx4AHC125W	CFP(14)	9.21mm×5.97mm
SNx4AHC125DGV	TVSOP(14)	3.60mm×4.40mm
SNx4AHC125PW	TSSOP(14)	5.00mm×4.40mm
SNx4AHC125N	PDIP(14)	19.30mm×6.35mm
SNx4AHC125RGY	VQFN(14)	3.50mm×3.50mm
SNx4AHC125J	CDIP(14)	19.56mm×6.67mm

(1) For all available packages, see the orderable addendum at the endofthedatasheet.

LogicDiagram(PositiveLogic)

graph TD
    A["1OE"] -->|1| B["NOT"]
    C["1A"] -->|2| D["NOT"]
    E["2OE"] -->|4| F["NOT"]
    G["2A"] -->|5| H["NOT"]
    B --> I["3"]
    D --> J["6"]
    F --> K["6"]

3OE 10 3A 3Y 9 4OE 13 4A 4Y 12 8 11

PinnumbersshownarefortheD,DB,DGV,J,N,NS,PW,RGY,andWpackages.

TableofContents

1 Features.... 1
2 Applications 1
3 Description 1
4 Revision History...... 2

5PinConfigurationandFunctions....3

6 Specifications.... 5

6.1 AbsoluteMaximumRatings....5
6.2ESDRatings....5
6.3RecommendedOperatingConditions....5
6.4ThermalInformation....6
6.5 Electrical Characteristics....6
6.6SwitchingCharacteristics:V CC =3.3V±0.3V......8
6.7SwitchingCharacteristics:V CC =5V±0.5V....9
6.8NoiseCharacteristics....10
6.9OperatingCharacteristics....10
6.10 Typical Characteristics....10

7ParameterMeasurementInformation....11

8DetailedDescription....12

8.1Overview....12

8.2FunctionalBlockDiagram....12
8.3FeatureDescription....12
8.4DeviceFunctionalModes....12

9ApplicationandImplementation....13

9.1 Application Information....13
9.2 Typical Application....13

10PowerSupplyRecommendations....15

11 Layout.... 15

11.1 LayoutGuidelines....15
11.2LayoutExample....15

12DeviceandDocumentationSupport....16

12.1 DocumentationSupport....16
12.2RelatedLinks....16
12.3ReceivingNotificationofDocumentationUpdates16
12.4CommunityResources....16
12.5Trademarks....16
12.6ElectrostaticDischargeCaution....16
12.7Glossary....16

13Mechanical, Packaging, and Orderable Information 16

4RevisionHistory

NOTE: Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion.

ChangesfromRevisionK(June2013)toRevisionL

Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. 1
• Deleted Ordering Information table; see Package Option Addendum at the end of the data sheet.... 1
• ChangedPackagethermalimpedance, R 0JA, value in Thermal Information table From: 86°C/W To: 92.6°C/W (D), From: 96°C/W To: 107.3°C/W (DB), From: 127°C/W To: 134.6°C/W (DGV), From: 80°C/W To: 56.3°C/W (N), From: 76°C/W To: 89.9°C/W (NS), and From: 113°C/W To: 121.5°C/W (PW) .... 6

ChangesfromRevisionJ(December1995)toRevisionK

Page

• Changed document format from Quicksilver to DocZone .... 1
• Extended operating temperature range to 125°C....5

5 Pin Configuration and Functions

D, DB, DGV, N, NS, J, W, or PW Package 14-Pin SOIC, SSOP, TVSOP, PDIP, SO, CDIP, CFP, or TSSOP Top View

11OE 14 V 21A 13 4OE 31Y 12 4A 42OE 11 4Y 52A 10 3OE 62Y 9 3A 7GND 8 3Y Not to scale

RGY Package 14-Pin VQFN Top View 1OE VCC 1 14 1A 2 13 4OE 1Y 3 12 4A 2OE 4 4 11 4Y 2A 5 10 3OE 2Y 6 9 3A 7 8 GND 3Y

PinFunctions

PIN			I/ODESCRIPTION
NAME	SOIC,SSOP,TVSOP,PDIP, SO,CDIP,CFP,TSSOP,VQFN	LCCC
1OE12IO	Outputenableforgate1
1A23IGate1input
1Y34OGate1output
2OE46IO	Outputenableforgate2
2A58IGate2input
2Y69OGate2output
3OE10	14IOutputenableforgate3
3A9	13IGate3input
3Y8	12 OGate3output
4OE13	19IOutputenableforgate4
4A12	18 IGate4input
4Y11	16 OGate4output
GND	7	10	— Ground pin
NC	—	1,5,7, 11,15,17	— Nointernalconnection
VCC	14	20	— Powerpin

6Specifications

6.1 AbsoluteMaximumRatings

overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1)

		MINMAXUNIT
Supplyvoltage-0.57V
Inputvoltage^(2)		-0.57V
Outputvoltage^(2)		-0.5	V_CC+0.5	V
Inputclampcurrent	V_I<0		-20	mA
Outputclampcurrent	V_O<0orV_O>V_CC		±20	mA
Continuousoutputcurrent	V_O=0toV_CC		±25	mA
Continuouscurrentthrough V_CC orGND			±50	mA
Virtualoperatingjunctiontemperature, T_J			150	°C
Storagetemperature, T_stg		-65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2ESDRatings

		VALUE	UNIT
V_(ESD) Electrostaticdischarge	Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001 (1)	±1500	V
	Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101 (2)	±1000

(1)JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.

(2)JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.

6.3 Recommended Operating Conditions

overoperatingfree-airtemperaturerange(unlessotherwisenoted)

			MIN	MAX	UNIT
V_CC	Supplyvoltage		2	5.5	V
V_IH	High-levelinputvoltage	V_CC=2V	1.5		V
		V_CC=3V	2.1
		V_CC=5.5V	3.85
V_IL	Low-levelInputvoltage	V_CC=2V		0.5	V
		V_CC=3V		0.9
		V_CC=5.5V		1.65
V_I	Inputvoltage		0	5.5	V
V_O	Outputvoltage		0	V_CC	V
I_OH	High-leveloutputcurrent	V_CC=2V		-50	μA
		V_CC=3.3V±0.3V		-4	mA
		V_CC=5V±0.5V		-8
I_OL	Low-leveloutputcurrent	V_CC=2V		50	μA
		V_CC=3.3V±0.3V		4	mA
		V_CC=5V±0.5V		8
t/ v	InputTransitionriseorfallrate	V_CC=3.3V±0.3V		100	ns/V
		V_CC=5V±0.5V		20
T_A	Operating free-air temperature		-40	125	°C

6.4ThermalInformation

THERMALMETRIC (1)		SNx4AHC125							UNITD(S)
		14 PINS	14 PINS	14 PINS	14 PINS	14 PINS	14 PINS	14 PINS
R_ JA	Junction-to-ambientthermal resistance	92.6	107.3	89.9	134.6	121.5	56.3	55.1	°C/W
R_ JC(top)	Junction-to-case (top)thermal resistance	52.7	59.3	47.7	53.9	50.2	43.9	52.3	°C/W
R_ JB	Junction-to-boardthermal resistance	46.8	54.7	48.6	63.8	63.2	36.1	30.9	°C/W
v_JT	Junction-to-top characterization parameter	19.7	24	17.5	6.3	6.1	29.2	2.4	°C/W
v_JB	Junction-to-board characterization parameter	46.6	54.1	48.3	63.2	62.7	36	31	°C/W
R_ JC(bot)	Junction-to-case (bottom)thermal resistance	—	—	—	—	—	—	12.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS			MIN	TYP	MAX	UNIT
V_OH	I_OH=-50μA	V_CC=2V	T_A=25°C	1.9	2		V
			T_A=-55°Cto125°C(SN54AHC125)	1.9
			T_A=-40°Cto85°C(SN74AHC125)	1.9
			T_A=-40°Cto125°C(recommendedSN74AHC125)	1.9
		V_CC=3V	T_A=25°C	2.9	3
			T_A=-55°Cto125°C(SN54AHC125)	2.9
			T_A=-40°Cto85°C(SN74AHC125)	2.9
			T_A=-40°Cto125°C(recommendedSN74AHC125)	2.9
		V_CC=4.5V	T_A=25°C	4.4	4.5
			T_A=-55°Cto125°C(SN54AHC125)	4.4
			T_A=-40°Cto85°C(SN74AHC125)	4.4
			T_A=-40°Cto125°C(recommendedSN74AHC125)	4.4
	I_OH=-4mAandV CC=3V		T_A=25°C	2.58
			T_A=-55°Cto125°C(SN54AHC125)	2.48
			T_A=-40°Cto85°C(SN74AHC125)	2.48
			T_A=-40°Cto125°C(recommendedSN74AHC125)	2.48
	I_OH=-8mAandV CC=4.5V		T_A=25°C	3.94
			T_A=-55°Cto125°C(SN54AHC125)	3.8
			T_A=-40°Cto85°C(SN74AHC125)	3.8
			T_A=-40°Cto125°C(recommendedSN74AHC125)	3.8

ElectricalCharacteristics(continued)

overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)

PARAMETERTESTCONDITIONSMINTYPMAXUNIT
V_OL	I_OL=50μA	V_CC=2V	T_A=25°C0.1			V
			T_A=-55°Cto125°C(SN54AHC125)0.1
			T_A=-40°Cto85°C(SN74AHC125)	0.1
			T_A=-40°Cto125°C(recommendedSN74AHC125)	0.1
		V_CC=3V	T_A=25°C0.1
			T_A=-55°Cto125°C(SN54AHC125)0.1
			T_A=-40°Cto85°C(SN74AHC125)	0.1
			T_A=-40°Cto125°C(recommendedSN74AHC125)		0.1
		V_CC=4.5V	T_A=25°C0.1
			T_A=-55°Cto125°C(SN54AHC125)0.1
			T_A=-40°Cto85°C(SN74AHC125)	0.1
			T_A=-40°CTo125°C(recommendedSN74AHC125)	0.1
	I_OH=4mAandV CC=3V		T_A=25°C	0.36
			T_A=-55°Cto125°C(SN54AHC125)0.5
			T_A=-40°Cto85°C(SN74AHC125)0.44
			T_A=-40°CTo125°C(recommendedSN74AHC125)	0.5
	I_OH=8mAandV CC=4.5V		T_A=25°C	0.36
			T_A=-55°CTo125°C(SN54AHC125)0.5
			T_A=-40°CTo85°C(SN74AHC125)0.44
			T_A=-40°CTo125°C(recommendedSN74AHC125)	0.5
I_I	V_I=5.5VorGNDandV CC=0Vto5.5V		T_A=25°C	±0.1		μA
			T_A=-55°CTo125°C(SN54AHC125)	±1 (1)
			T_A=-40°CTo85°C(SN74AHC125)	±1
			T_A=-40°CTo125°C(recommendedSN74AHC125)	±1
I_OZ	V_O=V_CC orGNDandV CC=5.5V		T_A=25°C	±0.25		μA
			T_A=-55°CTo125°C(SN54AHC125)	±2.5
			T_A=-40°CTo85°C(SN74AHC125)±2.5
			T_A=-40°CTo125°C(recommendedSN74AHC125)	±2.5
I_CC	V_I=V_CC orGND,I_O=0.andV CC=5.5V		T_A=25°C	4		μA
			T_A=-55°CTo125°C(SN54AHC125)	40
			T_A=-40°CTo85°C(SN74AHC125)	40
			T_A=-40°CTo125°C(recommendedSN74AHC125)	40
C_I	V_I=V_CC orGNDandV CC=5V		T_A=25°C	4	10	pF
			T_A=-40°CTo85°C(SN74AHC125)	10

(1) OnproductscomplianttoMIL-PRF-38535, this parameter is not produced tested at V
cc = 0V.

6.6SwitchingCharacteristics:V cc =3.3V±0.3V

overrecommendedoperatingfree-airtemperaturerangeandV _cc=3.3V±0.3V (unless otherwise noted; see Figure2)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	TESTCONDITIONSMINTYPMAXUNIT
t_PHL, t_PLH	AY	C	L=15pF	T_A=25°C	5.6 (1)	8(1)	ns
				T_A=-55°Cto125°C(SN54AHC125)	1(1)	9.5(1)
				T_A=-40°Cto85°C(SN74AHC125)	1	9.5
				T_A=-40°Cto125°C(recommendedSN74AHC125)	1	9.5
t_PZL, t_PZH		Y	C_L=15pF	T_A=25°C	5.4 (1)	8(1)	ns
				T_A=-55°Cto125°C(SN54AHC125)	1(1)	9.5(1)
				T_A=-40°Cto85°C(SN74AHC125)		9.5
				T_A=-40°Cto125°C(recommendedSN74AHC125)		9.5
t_PLZ, t_PHZ		Y	C_L=15pF	T_A=25°C	7.0 (1)	9.7(1)	ns
				T_A=-55°Cto125°C(SN54AHC125)	1(1)	11.5(1)
				T_A=-40°Cto85°C(SN74AHC125)	1 (1)	11.5(1)
				T_A=-40°Cto125°C(recommendedSN74AHC125)	1(1)	11.5(1)
t_PHL, t_PLH	AY	C	L=50pF	T_A=25°C	8.1	11.5	ns
				T_A=-55°Cto125°C(SN54AHC125)	1	13
				T_A=-40°Cto85°C(SN74AHC125)	1	13
				T_A=-40°Cto125°C(recommendedSN74AHC125)	1	13
t_PZL, t_PZH		Y	C_L=50pF	T_A=25°C	7.9	11.5	ns
				T_A=-55°Cto125°C(SN54AHC125)	1	13
				T_A=-40°Cto85°C(SN74AHC125)	1	13
				T_A=-40°Cto125°C(recommended SN74AHC125)	1	13
t_PLZ, t_PHZ		Y	C_L=50pF	T_A=25°C	9.5	13.2	ns
				T_A=-55°Cto125°C(SN54AHC125)	1	15
				T_A=-40°Cto85°C(SN74AHC125)	1	15
				T_A=-40°Cto125°C(recommendedSN74AHC125)	1	15
tsk(o)		Y	C_L=50pF	T_A=25°C		1.5 (2)	ns
				T_A=-40°Cto85°C(SN74AHC125)		1.5

(1) OnproductscomplianttoMIL-PRF-38535, this parameter is not produced tested.
(2) OnproductscomplianttoMIL-PRF-38535, this parameter does not apply.

6.7SwitchingCharacteristics: V cc =5V±0.5V

overrecommendedoperatingfree-airtemperaturerangeandV cc =5V±0.5V(unlessotherwisenoted;seeFigure2)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	TESTCONDITIONSMINTYPMAXUNIT
t_PLH, t_PHL	AY	C	L=15pF	T_A=25°C	3.8 (1)	5.5 (1)	ns
				T_A=-55°Cto125°C(SN54AHC125)	1 (1)	6.5 (1)
				T_A=-40°Cto85°C(SN74AHC125)	1	6.5
				T_A=-40°Cto125°C(recommendedSN74AHC125)	1	6.5
t_PZH, t_PZL		Y	C_L=15pF	T_A=25°C	3.6 (1)	5.1 (1)	ns
				T_A=-55°Cto125°C(SN54AHC125)	1 (1)	6 (1)
				T_A=-40°Cto85°C(SN74AHC125)	1	6
				T_A=-40°Cto125°C(recommendedSN74AHC125)	1	6
t_PHZ, t_PLZ		Y	C_L=15pF	T_A=25°C	4.6 (1)	6.8 (1)	ns
				T_A=-55°Cto125°C(SN54AHC125)	1 (1)	8 (1)
				T_A=-40°Cto85°C(SN74AHC125)	1 (1)	8 (1)
				T_A=-40°Cto125°C(recommendedSN74AHC125)	1 (1)	8 (1)
t_PLH, t_PHL	AY	C	L=50pF	T_A=25°C	5.3	7.5	ns
				T_A=-55°Cto125°C(SN54AHC125)	1	8.5
				T_A=-40°Cto85°C(SN74AHC125)	1	8.5
				T_A=-40°Cto125°C(recommendedSN74AHC125)	1	8.5
t_PZH, t_PZL		Y	C_L=50pF	T_A=25°C	5.1	7.1	ns
				T_A=-55°Cto125°C(SN54AHC125)	1	8
				T_A=-40°Cto85°C(SN74AHC125)	1	8
				T_A=-40°Cto125°C(recommendedSN74AHC125)	1	8
t_PHZ, t_PLZ		Y	C_L=50pF	T_A=25°C	6.1	8.8	ns
				T_A=-55°Cto125°C(SN54AHC125)	1	10
				T_A=-40°Cto85°C(SN74AHC125)	1	10
				T_A=-40°Cto125°C(recommendedSN74AHC125)	1	10
tsk(o)		Y	C_L=50pF	T_A=25°C	1 (2)		ns
				T_A=-40°Cto85°C(SN74AHC125)	1

(1) OnproductscomplianttoMIL-PRF-38535, this parameter is not produced tested.
(2) OnproductscomplianttoMIL-PRF-38535, this parameter does not apply.

6.8 Noise Characteristics

$$ V _ {C C} = 5 V, C \quad_ {L} = 5 0 p F, a n d T \quad_ {A} = 2 5 ^ {\circ} C ^ {(1)} $$

PARAMETERMINMAXUNIT
V_OL(P)	Quietoutput,maximumdynamic( V_OL )0.8V
V_OL(V)	Quietoutput,minimumdynamic( V_OL )	-0.8V
V_OH(V)	Quietoutput,minimumdynamic( V_OH )	4.4	V
V_IH(D)	High-leveldynamicinputvoltage	3.5	V
V_IL(D)	Low-leveldynamicinputvoltage	1.5V

(1) Characteristics are for surface-mount packages only.

6.9 Operating Characteristics

$$ V _ {C C} = 5 \text { VandT } \quad_ {A} = 2 5 ^ {\circ} \text { C } $$

PARAMETER		TESTCONDITIONS	TYP	UNIT
C_pd	Powerdissipationcapacitance	Noloadandf=1MHz	9.5pF

6.10 Typical Characteristics

Figure1 shows I CC for varying V IN values when V CC is 5V±0.5V and T A =25°C.

Figure 1. V_IN vs I_CC

7ParameterMeasurementInformation

From Output Under Test Test Point CL (see Note A)

LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS

From Output Under Test CL (see Note A) RL = 1 kΩ S1 VCC Open GND

LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS

TEST S1
t_PLH/t_PHL	Open
t_PLZ/t_PZL	V_CC
t_PHZ/t_PZH	GND
Open Drain	V_CC

Input 50% VCC tW 50% VCC 0 V VCC

Timing Input 50% VCC VCC 0 V tsu th Data Input 50% VCC 50% VCC VCC 0 V

VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

Input 50% VCC 50% VCC 0 V tPLH tPHL In-Phase Output 50% VCC 50% VCC VOL tPHL tPLH Out-of-Phase Output 50% VCC 50% VCC VOL

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
A. C_L includesprobeandjigcapacitance.
B. Waveform1 is foranoutput with internal condition such that the output is slow except when disabled by the output control. Waveform2 is foranoutput with internal condition such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z_O=50 , t_r ≤ 3ns , t_f ≤ 3ns .
D. The outputs are measured one at timewith one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.

Figure2.LoadCircuitandVoltageWaveforms

8DetailedDescription

8.1 Overview

TheSNx4AHC125deviceshavefourintegratedbusbuffergates.Eachgatecanbeindividuallycontrolledfrom theirrespectiveoutputenablepinsortiedtogetherandcontrolledsimultaneously.Thisallowsforcontrolofupto fourdifferentlinesfromonedevice.Oftentimesamicrocontrollerhavemultiplefunctionoptionsforasinginglepin. ByusingGPIOpinstoenablespecificbuffers,theSNx4AHC125canactasamultiplexertoselectaspecificdata linedependingonwhatpinfunctionisselectedonthemicrocontroller.Atthesametime,thelinestatarenot selectedareisolatedfromthepin.

8.2 FunctionalBlockDiagram

1OE 1 1A 1Y 2 2OE 4 2A 2Y 5 3 6

3OE 10 3A 3Y 9 4OE 13 4A 4Y 12 8 11

PinnumbersshownarefortheD,DB,DGV,J,N,NS,PW,RGY,andWpackages.

8.3FeatureDescription

Eachbufferhasitsownoutputenable. This allows for control of each buffer individually. When the output enable is LOW, the input is passed to the output. When the output enable is HIGH, the output is high impedance. This feature is useful in application that might require isolation.

8.4DeviceFunctionalModes

Table1 liststhefunctionalmodesoftheSNx4AHC125.

Table1.FunctionTable (EachBuffer)

INPUTSOUTPUT
	A	Y
L	H	H
L	L	L
H	X	Z

9ApplicationandImplementation

NOTE

InformationinthefollowingapplicationssectionsisnotpartoftheTlcomponent specification,andTldoesnotwarrantitsaccuracyorcompleteness.TI'scustomersare responsiblefordeterminingsuitabilityofcomponentsfortheirpurposes.Customersshould validateandtesttheirdesignimplementationtoconfirmsystemfunctionality.

9.1 Application Information

ThewideoperatingrangeoftheSNx4AHC125devicesallowsforimplementationintoavarietyofapplications.In additiontothewideoperatingrange,thesedevicesdifferentiatefromsimilardevicesbecausetheyhavefour buffersthatcanbeindividuallycontrolledthroughtheirindependentoutputenable(OE)pins.Eachbufferiseither enabledandpassesdatafromAtoY,ordisabledandsettoahigh-impedancestate.

9.2 Typical Application

graph TD
    MCU["MCU"] -->|UART TX| UART1["1"]
    MCU -->|UART TX/ SPI Out| UART2["2"]
    MCU -->|UART RX/ SPI In| UART3["3"]
    UART1 -->|SPI OUT| UART4["4"]
    UART2 -->|SPI OUT| UART5["5"]
    UART3 -->|SPI OUT| UART6["6"]
    UART4 -->|SPI OUT| UART7["7"]
    UART5 -->|GND| UART8["8"]
    UART6 -->|GND| UART9["9"]
    UART7 -->|GND| UART10["10"]
    UART8 -->|SPI OUT| UART11["11"]
    UART9 -->|SPI OUT| UART12["12"]
    UART10 -->|SPI OUT| UART13["13"]
    UART11 -->|SPI OUT| UART14["14"]
    UART12 -->|SPI OUT| UART15["15"]
    UART13 -->|SPI OUT| UART16["16"]
    UART14 -->|SPI OUT| UART17["17"]
    UART15 -->|SPI OUT| UART18["18"]
    UART16 -->|SPI OUT| UART19["19"]
    UART17 -->|SPI OUT| UART20["20"]
    UART18 -->|SPI OUT| UART21["21"]
    UART19 -->|SPI OUT| UART22["22"]
    UART20 -->|SPI OUT| UART23["23"]
    UART21 -->|SPI OUT| UART24["24"]
    UART22 -->|SPI OUT| UART25["25"]
    UART23 -->|SPI OUT| UART26["26"]
    UART24 -->|SPI OUT| UART27["27"]
    UART25 -->|SPI OUT| UART28["28"]
    UART26 -->|SPI OUT| UART29["29"]
    UART27 -->|SPI OUT| UART30["30"]
    UART28 -->|SPI OUT| UART31["31"]
    UART29 -->|SPI OUT| UART32["32"]
    UART30 -->|SPI OUT| UART33["33"]
    UART31 -->|SPI OUT| UART34["34"]
    UART32 -->|SPI OUT| UART35["35"]
    UART33 -->|SPI OUT| UART36["36"]
    UART34 -->|SPI OUT| UART37["37"]
    UART35 -->|SPI OUT| UART38["38"]
    UART36 -->|SPI OUT| UART39["39"]
    UART37 -->|SPI OUT| UART40["40"]
    UART38 -->|SPI OUT| UART41["41"]
    UART39 -->|SPI OUT| UART42["42"]
    UART40 -->|SPI OUT| UART43["43"]
    UART41 -->|SPI OUT| UART44["44"]
    UART42 -->|SPI OUT| UART45["45"]
    UART43 -->|SPI OUT| UART46["46"]
    UART44 -->|SPI OUT| UART47["47"]
    UART45 -->|SPI OUT| UART48["48"]
    UART46 -->|SPI OUT| UART49["49"]
    UART47 -->|SPI OUT| UART50["50"]
    UART48 -->|SPI OUT| UART51["51"]
    UART49 -->|SPI OUT| UART52["52"]
    UART50 -->|SPI OUT| UART53["53"]
    UART51 -->|SPI OUT| UART54["54"]
    UART52 -->|SPI OUT| UART55["55"]
    UART53 -->|SPI OUT| UART56["56"]
    UART54 -->|SPI OUT| UART57["57"]
    UART55 -->|SPI OUT| UART58["58"]
    UART56 -->|SPI OUT| UART59["59"]
    UART57 -->|SPI OUT| UART60["60"]
    UART58 -->|SPI OUT| UART61["61"]
    UART59 -->|SPI OUT| UART62["62"]
    UART60 -->|SPI OUT| UART63["63"]
    UART61 -->|SPI OUT| UART64["64"]
    UART62 -->|SPI OUT| UART65["65"]
    UART63 -->|SPI OUT| UART66["66"]
    UART64 -->|SPI OUT| UART67["67"]
    UART65 -->|SPI OUT| UART68["68"]
    UART66 -->|SPI OUT| UART69["69"]
    UART67 -->|SPI OUT| UART70["70"]
    UART68 -->|SPI OUT| UART71["71"]
    UART69 -->|SPI OUT| UART72["72"]
    UART70 -->|SPI OUT| UART73["73"]
    UART71 -->|SPI OUT| UART74["74"]
    UART72 -->|SPI OUT| UART75["75"]
    UART73 -->|SPI OUT| UART76["76"]
    UART74 -->|SPI OUT| UART77["77"]
    UART75 -->|SPI OUT| UART78["78"]
    UART76 -->|SPI OUT| UART79["79"]
    UART77 -->|SPI OUT| UART80["80"]
    UART78 -->|SPI OUT| UART81["81"]
    UART79 -->|SPI OUT| UART82["82"]
    UART80 -->|SPI OUT| UART83["83"]
    UART81 -->|SPI OUT| UART84["84"]
    UART82 -->|SPI OUT| UART85["85"]
    UART83 -->|SPI OUT| UART86["86"]
    UART84 -->|SPI OUT| UART87["87"]
    UART85 -->|SPI OUT| UART88["88"]
    UART86 -->|SPI OUT| UART89["89"]
    UART87 -->|SPI OUT| UART90["90"]
    UART88 -->|SPI OUT| UART91["91"]
    UART89 -->|SPI OUT| UART92["92"]
    UART90 -->|SPI OUT| UART93["93"]
    UART91 -->|SPI OUT| UART94["94"]
    UART92 -->|SPI OUT| UART95["95"]
    UART93 -->|SPI OUT| UART96["96"]
    UART94 -->|SPI OUT| UART97["97"]
    UART95 -->|SPI OUT| UART98["98"]
    UART96 -->|SPI OUT| UART99["99"]
    UART97 -->|SPI OUT| UART100["100"]

        1OE
        1A
        1Y
        2OE
        2A
        2Y
        GND
        4OE
        4A
        4Y
        3OE
        3A
        3Y
        Vcc
        SPI_IN
        SPI_RX
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_IN
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPI_OUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIOUT
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPIIN
        SPII IN
        SPIIN RX
        SPIIN RXTX
        SPIIN RXTXTXXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXTXRX

Copyright © 2016, Texas Instruments Incorporated

Figure3.DigitalMUX

9.2.1 DesignRequirements

ItisbesttosetV CC fortheSN74AHC125tothesamelevelasthemicrocontrollerlogic levels. This allows for optimal performance. The SN74AHC125 cansafely handle input levels from -0.5V to 7V. However, if the logic level that are being received by the V CC level of the device then error scan occur. Forexample, if V 5.5V thentheminimum high-level input voltage (V IH) level is 3.85V. This means if the microcontroller issuing a HIGH signal, but HIGH = 3.3V, it would be too low level for the SNx4AHC125 to register it as what it must be. In this case V CC would need to be lowered in order to lower the V_IH minimum. The opposite is also true for low-level input voltage (V IL). If VCCissetto2V, then V IL maximum is 0.5V. Depending on the microcontroller logic levels, a LOW signal may not golowenough for the SNx4AHC125 to register it.

Typical Application (continued)

9.2.2 Detailed Design Procedure

1. RecommendedInputConditions:

-ForV IH andV IL levelsatvaryingV CC , seeRecommendedOperatingConditions.
-Bemindfulofrisetimeandfalltimespecificationsfortheoutputenablepinstoensurethattheright buffers are enabled and the others are disabled in time. This minimizes interference on the microcontroller pin and to exterior circuitry. See Switching Characteristics: VCC = 3.3 V ± 0.3 V and SwitchingCharacteristics: V_CC = 5V ± 0.5V tableformoredetails.

2. RecommendedOutputConditions:

-Load currentsmust not exceed I_0 maximum per output and must not exceed continuous current through V_CC or GND total current for the part. These limits are located in the Absolute Maximum Ratings.
-OutputsmustnotbepulledaboveV cc.

9.2.3 ApplicationCurves

Typicaldeviceat25°C

10PowerSupplyRecommendations

The powersupply can be any voltage between the minimum and maximum supply voltage, ranging in the Recommended Operating Conditions.

EachV CC pinmusthaveagoodbypasscapacitortopreventpowerdisturbance. Fordeviceswithasinglesupply, a0.1-μFcapacitorisrecommendedandiftherearemultipleV CC pinstthena0.01-μFor0.022-μFcapacitoris recommendedforeachpowerpin.Itisoktoparallelmultiplebypasscapacitorstorejectdifferentfrequenciesof noise. 0.1-μFand1-μFcapacitorsarecommonlyusedinparallel.Thebypasscapacitormustbeinstalledas closetothepowerpinaspossibleforbestresults.

11Layout

11.1 LayoutGuidelines

When using multiple bitlogic devices, input must not ever float. In many cases, functions or part so function of digital logic devices are unused; example, when only two input to a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below a therule that must be observed under all circumstances. All unused input so of digital logic devices must be connected to a high or low biastoprevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, they are tied to GNDorV CC (whichever makemoresense or is more convenient).

11.2 LayoutExample

VCC Unused Input Input Output Output

Input Unused Input

Figure6.LayoutDiagram

12DeviceandDocumentationSupport

12.1 DocumentationSupport

12.1.1 RelatedDocumentation

Forrelateddocumentationseethefollowing: ImplicationsofSloworFloatingCMOSInputs(SCBA004)

12.2RelatedLinks

Thetablebelowlistsquickaccesslinks. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.

Table2.RelatedLinks

PARTSPRODU	CTFOLDERSAMPLE&	BUY	TECHNICAL DOCUMENTS	TOOLS& SOFTWARE	SUPPORT& COMMUNITY
SN54AHC125	Click here	Click here	Click here	Click here	Click here
SN74AHC125	Click here	Click here	Click here	Click here	Click here

12.3ReceivingNotificationofDocumentationUpdates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. Forchangedetails, reviewtherevisionhistoryincludedinanyreviseddocument.

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.5Trademarks

E2EisattrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners.

12.6ElectrostaticDischargeCaution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.

12.7 Glossary

SLYZ022 — TIGlossary. This glossary lists and explain terms, acronyms, and definitions.

13Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this datasheet, refertothe left-hand navigation.

PACKAGING INFORMATION

Orderable Device Status(1)		Package Type	Package Drawing	Pins	Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4,5)	Samples
5962-9686801Q2A ACTIVE LCCC FK 20 1 Non-RoHS						& Green	SNPB N / A for Pkg Type -55 to 125 5962-			9686801Q2A SNJ54AHC 125FK	Samples
5962-9686801QCA ACTIVE CDIP J 14 1 Non-RoHS						& Green	SNPB N / A for Pkg Type -55 to 125 5962-9686801QC			A SNJ54AHC125J	Samples
5962-9686801QDA ACTIVE CFP W 14 1 Non-RoHS						& Green	SNPB N / A for Pkg Type -55 to 125 5962-9686801QD			A SNJ54AHC125W	Samples
SN74AHC125D	ACTIVE	SOIC	D	14	50	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	AHC125	Samples
SN74AHC125DBR	ACTIVE	SSOP	DB	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	HA125	Samples
SN74AHC125DG4	ACTIVE	SOIC	D	14	50	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	AHC125	Samples
SN74AHC125DGVR	ACTIVE	TVSOP	DGV	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	HA125	Samples
SN74AHC125DR	ACTIVE	SOIC	D	14	2500	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	AHC125	Samples
SN74AHC125DRG4	ACTIVE	SOIC	D	14	2500	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	AHC125	Samples
SN74AHC125N	ACTIVE	PDIP	N	14	25	RoHS & Green	NIPDAU	N / A for Pkg Type	-40 to 125	SN74AHC125N	Samples
SN74AHC125NE4	ACTIVE	PDIP	N	14	25	RoHS & Green	NIPDAU	N / A for Pkg Type	-40 to 125	SN74AHC125N	Samples
SN74AHC125NSR	ACTIVE	SO	NS	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	AHC125	Samples
SN74AHC125PW	ACTIVE	TSSOP	PW	14	90	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	HA125	Samples
SN74AHC125PWR	ACTIVE	TSSOP	PW	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	HA125	Samples
SN74AHC125PWRE4	ACTIVE	TSSOP	PW	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	HA125	Samples
SN74AHC125PWRG4	ACTIVE	TSSOP	PW	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	HA125	Samples
SN74AHC125RGYR	ACTIVE	VQFN	RGY	14	3000	RoHS & Green	NIPDAU	Level-2-260C-1 YEAR	-40 to 125	HA125	Samples
Orderable Device Status(1)		Package Type	Package Drawing	Pins	Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4-5)	Samples
SN74AHC125RGYRG4 ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 HA125											Samples
SNJ54AHC125FK ACTIVE LCCC FK 20 1		Non-RoHS				& Green	SNPB N / A for Pkg Type	-55 to 125 5962-		9686801Q2A SNJ54AHC 125FK	Samples
SNJ54AHC125J	ACTIVE	CDIP	J	14	1	Non-RoHS & Green	SNPB N / A for Pkg Type	-55 to 125 5962-9686801QC		A SNJ54AHC125J	Samples
SNJ54AHC125W ACTIVE	CFP W	14 1	Non-RoHS			& Green	SNPB N / A for Pkg Type	-55 to 125 5962-9686801QD		A SNJ54AHC125W	Samples

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "\~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(5) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54AHC125, SN74AHC125 :

• Catalog : SN74AHC125
• Automotive : SN74AHC125-Q1, SN74AHC125-Q1
• Enhanced Product : SN74AHC125-EP, SN74AHC125-EP
• Military : SN54AHC125

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package	Type	Package Drawing	Pins	SPQ Reel	Diameter (mm)	Reel Width W1 (mm)	A0 (mm)	B0 (mm)	K0 (mm)	P1 (mm)	W (mm)	Pin1 Quadrant
SN74AHC125DBR SSOP DB 14	OP DB 14	2000 330.0	16.4	8.35 6.6 2	4 12.0 16.0	Q1
SN74AHC125DGVR TVSOP DGV	14 2000 3	30.0 1	2.4 6.8 4.0	1.6 8.0 12.0	Q1
SN74AHC125DR SOIC D 14 2500	0 330.0 1	6.4 6.5	9.0 2.1 8.0	16.0	Q1
SN74AHC125DR SOIC D 14 2500	0 330.0 1	6.4 6.5	9.0 2.1 8.0	16.0	Q1
SN74AHC125NSR	SO	NS 14	2000 3	30.0 16.4	8.2 10.5 2	5 12.0 16.0	Q1
SN74AHC125PWR	TSSOP PW	14	2000	330.0 12.4	6.9 5.6 1.6	8.0 12.0	Q1
SN74AHC125RGYR	VQFN R	GY 14 300	0 330	0 12.4 3.75	3.75 1.15	8.0 12.0	Q1

TAPE AND REEL BOX DIMENSIONS W L

*All dimensions are nominal

Device	Package Type	Package Drawing	Pins	SPQ	Length (mm)	Width (mm)	Height (mm)
SN74AHC125DBR SSOP DB 14 2000 853.0	449.0 35.0
SN74AHC125DGVR TVSOP DGV 14 2000	853.0 449.0 35.0
SN74AHC125DR SOIC	D	14 2500	853.0 449.0 35.0
SN74AHC125DR SOIC	D	14 2500	840.5 336.1 32.0
SN74AHC125NSR SO	NS	14 2000 853.0 449.0 35.0
SN74AHC125PWR	TSSOP	PW	14	2000	853.0	449.0	35.0
SN74AHC125RGYR	VQFN	RGY 14 3000	853.0	449.0 35.0

TUBE

T - Tube height L - Tube length W-Tube width B - Alignment groove width

*All dimensions are nominal

Device	Package Name	Package Type	Pins	SPQ	L (mm)	W (mm)	T (μm)	B (mm)
5962-9686801Q2A FK	CCC 20 1 506.98	12.06 2030 NA
SN74AHC125D	D	SOIC	14	50	506.6	8	3940	4.32
SN74AHC125DG4	D	SOIC	14	50	506.6	8	3940	4.32
SN74AHC125N	N	PDIP	14	25	506	13.97	11230	4.32
SN74AHC125N	N	PDIP	14	25	506	13.97	11230	4.32
SN74AHC125NE4	N	PDIP	14	25	506	13.97	11230	4.32
SN74AHC125NE4	N	PDIP	14	25	506	13.97	11230	4.32
SN74AHC125PW	PW	TSSOP	14	90	530	10.2	3600	3.5
SNJ54AHC125FK FK	CCC 20 1 506.98	12.06 2030 NA

FK (S-CQCC-N**)

28 TERMINAL SHOWN

LEADLESS CERAMIC CHIP CARRIER

NO. OF TERMINALS**	A		B
	MIN	MAX	MIN	MAX
20	0.342(8,69)	0.358(9,09)	0.307(7,80)	0.358(9,09)
28	0.442(11,23)	0.458(11,63)	0.406(10,31)	0.458(11,63)
44	0.640(16,26)	0.660(16,76)	0.495(12,58)	0.560(14,22)
52	0.740(18,78)	0.761(19,32)	0.495(12,58)	0.560(14,22)
68	0.938(23,83)	0.962(24,43)	0.850(21,6)	0.858(21,8)
84	1.141(28,99)	1.165(29,59)	1.047(26,6)	1.063(27,0)

4040140/D 01/11
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. Falls within JEDEC MS-004

RGY (S-PVQFN-N14)

PLASTIC QUAD FLATPACK NO-LEAD

3,65 3,35 A 13 9 B 3,65 3,35 Pin 1 Index Area Top and Bottom 1 2 6 F 1,00 0,80 0,20 Nominal Lead Frame Seating Plane 0,08 C 0,05 0,00 C Seating Height 2,00 0,50 14X 0,50 0,30 2 6 1 THERMAL PAD 7 1,50 SIZE AND SHAPE SHOWN ON SEPRATE SHEET 8 14X 0,30 0,18 13 9 ⊕ 0,10 M C A B 0,05 M C

Bottom View

4203539-2/1 06/2011

NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.
C. QFN (Quad Flatpack No-Lead) package configuration.
D. The package thermal pad must be soldered to the board for thermal and mechanical performance.
E. See the additional figure in the Product Data Sheet for details regarding the exposed thermal pad features and dimensions.

Pin 1 identifiers are located on both top and bottom of the package and within the zone indicated.

The Pin 1 identifiers are either a molded, marked, or metal feature.

G. Package complies to JEDEC MO-241 variation BA.

RGY (S-PVQFN-N14)

PLASTIC QUAD FLATPACK NO-LEAD

THERMAL INFORMATION

This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB). After soldering, the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC).

For information on the Quad Flatpack No-Lead (QFN) package and its advantages, refer to Application Report, QFN/SON PCB Attachment, Texas Instruments Literature No. SLUA271. This document is available at www.ti.com.

The exposed thermal pad dimensions for this package are shown in the following illustration.

2 6 Exposed Thermal Pad 1 7 2,05±0,10 14 8 13 9 2,05±0,10

Bottom View

Exposed Thermal Pad Dimensions

4206353-2/P 03/14

NOTE: All linear dimensions are in millimeters

RGY (S-PVQFN-N14)
PLASTIC QUAD FLATPACK NO-LEAD

Example Board Layout 4,30 Note D 4,30 2,60 1,50 2,05 2,05 8x0,50 0,28 Example Stencil Design 0.125mm Stencil Thickness (Note E) 4,25 4,25 2,65 1,50 0,82 50 0,30 0,80 x 14 PL 8x0,50 0,23 x 14 PL. 64% solder coverage by printed area on center thermal pad Non Solder Mask Defined Pad Example Solder Mask Opening (Note F) 0,08 R0,14 0,85 0,28 Example Pad Geometry (Note C) 0,07 All Around Example Via Layout Design may vary depending on constraints (Note D, F) 6xØ0,3 1,00 1,00 4208122-2/P 03/14

NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate designs.
D. This package is designed to be soldered to a thermal pad on the board. Refer to Application Note, Quad Flat-Pack QFN/SON PCB Attachment, Texas Instruments Literature No. SLUA271, and also the Product Data Sheets for specific thermal information, via requirements, and recommended board layout. These documents are available at www.ti.com http://www.ti.com.
E. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC 7525 for stencil design considerations.
F. Customers should contact their board fabrication site for minimum solder mask web tolerances between signal pads.

MECHANICAL DATA

NS (R-PDSO-G\*\*)

PLASTIC SMALL-OUTLINE PACKAGE

14-PINS SHOWN

1,27 14 0,51 0,35 Ø 0,25① 8 5,60 5,00 8,20 7,40 1 7 A

0,15 NOM Gage Plane 0,25 0°-10° 1,05 0,55

2,00 MAX 0,15 0,05

Seating Plane 0.10

DIM\PINS **	14	16	20	24
A MAX	10,50	10,50	12,90	15,30
A MIN	9,90	9,90	12,30	14,70

4040062/C 03/03

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.

W (R-GDFP-F14)

CERAMIC DUAL FLATPACK

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification only.

E. Falls within MIL STD 1835 GDFP1-F14

DGV (R-PDSO-G\*\*) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

DIM\PINS **	14		20		382416	48	56
A MAX	3,70		5,10	5,103,70	7,90	9,80	11,40
A MIN	3,50	3,50	4,90	4,90	7,70	9,60	11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 per side.
D. Falls within JEDEC: 24/48 Pins - MO-153

14/16/20/56 Pins - MO-194

Illustration of a purple and maroon interconnect integrated circuit chip (no text or symbols on body)

Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details.

4040083-5/G

CERAMIC DUAL IN LINE PACKAGE

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

CERAMIC DUAL IN LINE PACKAGE

SEE DETAIL A 1 (.300) TYP [7.62] 14 SEE DETAIL B 12X (.100) [2.54] SYMM 14X (Ø39) [1] 7 8 SYMM

LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED

SCALE: 5X

MAX.002 [0.05] ALL AROUND (.063) [1.6] SOLDER MASK OPENING METAL (R.002) TYP [0.05] DETAIL A SCALE: 15X

METAL (2063) [1.6] SOLDER MASK OPENING .002 MAX [0.05] ALL AROUND DETAIL B 13X, SCALE: 15X

4214771/A 05/2017

D (R-PDSO-G14)
PLASTIC SMALL OUTLINE

0.344 (8,75) 0.337 (8,55) 14 8 Pin 1 Index Area 1 0.050 (1,27) 7 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,80) 0.020 (0,51) 0.012 (0,31) ⊕ 0.010 (0,25) M 0.069 (1,75) Max 0.010 (0,25) 0.004 (0,10) Gcuge Plane 0.010 (0,25) 0.005 (0,13) 0°-8° Seating Plane 0.010 (0,25) 0.050 (1,27) 0.016 (0,40) 4040047-5/M 06/11

NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.006 (0,15) each side.
Body width does not include interlead flash. Interlead flash shall not exceed 0.017 (0,43) each side.
E. Reference JEDEC MS-012 variation AB.

D (R-PDSO-G14)

4211283-3/E 08/12
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate designs.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

PW (R-PDSO-G14)

NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 each side.

Body width does not include interlead flash. Interlead flash shall not exceed 0,25 each side.

E. Falls within JEDEC MO-153

PW (R-PDSO-G14)

A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate designs.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

N (R-PDIP-T\*\*)

16 PINS SHOWN

PLASTIC DUAL-IN-LINE PACKAGE

A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) 0.045 (1,14)

C

DIM\PINS **	14	16	18	20
A MAX	0.775(19,69)	0.775(19,69)	0.920(23,37)	1.060(26,92)
A MIN	0.745(18,92)	0.745(18,92)	0.850(21,59)	0.940(23,88)
MS-001VARIATION	AA	BB	AC	AD

0.045 (1,14) 0.030 (0,76) D 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) ⊕ 0.010 (0,25) M 14/18 Pin Only 20 Pin vendor opt

0.325 (8,26) 0.300 (7,62) 0.015 (0,38) Gauge Plane 0.010 (0,25) NOM 0.430 (10,92) MAX

4040049/E 12/2002

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C Falls within JEDEC MS-001, except 18 and 20 pin minimum body length (Dim A).

The 20 pin end lead shoulder width is a vendor option, either half or full width.

DB (R-PDSO-G\*\*) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,65 28 0,38 0,22 0,15 M 15 5,60 5,00 8,20 7,40 1 14 A

0,25 0,09 Gage Plane 0°-8° 0,25 0,95 0,55

2,00 MAX 0,05 MIN

Seating Plane 0,10

DIM\PINS **	14	16	20	24	28	30	38
A MAX	6,50	6,50	7,50	8,50	10,50	10,50	12,90
A MIN		5,905,906,90			9,907,909,90		12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

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