SN74LVC573AN - Electronic component TEXAS INSTRUMENTS - Free user manual and instructions

USER MANUAL SN74LVC573AN TEXAS INSTRUMENTS

SNx4LVC573AOctalTransparentD-TypeLatchesWith3-StateOutputs

1Features2Applications

•TypicalV OLP (OutputGroundBounce)•Health&Fitness/Wearables <0.8VatV CC=3.3V,T A=25°C •Telecor

•OperateFrom1.65Vto3.6V
- InputsAcceptVoltagesto5.5V•PC,Notebook
•Maxt pd of6.9nsat3.3V•NetworkSwitch
•TypicalV OHV (OutputV OH Undershoot)

2VatV CC = 3.3V, T A = 25°C
•SupportMixed-ModeSignalOperationonAll Ports(5-VInput/OutputVoltageWith3.3-VV cc)
- I_off SupportsLiveInsertion, PartialPowerDown Mode, and BackDriveProtection
•Latch-UpPerformanceExceeds250mA PerJESD17
•ESDProtectionExceedsJESD22

• 2000-VHuman-BodyModel(A114-A)
• 200-VMachineModel(A115-A)
• 1000-VCharged-DeviceModel(C101)

- Servers

•TelecomInfrastructure

•ElectronicPointofSales

3Description

TheSN54LVC573AoctaltransparentD-typelatchis designedfor2.7-Vto3.6-VV CC operation,andthe SN74LVC573A octal transparent D-type latch is designedfor1.65-Vto3.6-V V CC operation.These devices feature 3-state outputs designed specifically fordrivinghighly capacitive orrelativelylow-impedance loads. They are particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectionalbusdrivers,andworkingregisters.

DeviceInformation (1)

PARTNUMBER	PACKAGE	BODYSIZE(NOM)
SN74LVC573A	PDIP(20)	25.40x6.35mm
	VQGN(20)	4.50x3.50mm
	SOIC(20)	12.80x7.50mm
	SSOP(20)	7.20x5.30mm
	TVSOP(20)	5.00x4.40mm

(1) For all available packages, see the orderable addendum at the end of the datasheet.

4Simplified Schematic

graph TD
    OE["OE"] -->|1| NOT1["NOT"]
    LE["LE"] -->|11| NOT2["NOT"]
    1D["1D"] -->|2| C1["C1 1D"]
    C1 --> NOT3["NOT"]
    NOT1 --> AND1["AND"]
    NOT2 --> AND1
    NOT3 --> AND2["AND"]
    AND1 --> C1
    AND2 --> C1
    C1 --> 19["19"]
    19 --> 1Q["1Q"]
    C1 --> ToSevenOtherChannels["To Seven Other Channels"]

Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages.

TableofContents

1 Features.... 1

2 Applications 1

3 Description 1

4SimplifiedSchematic....1

5 Revision History...... 2

6PinConfigurationandFunctions....3

7 Specifications.... 4

7.1 AbsoluteMaximumRatings....4

7.2HandlingRatings....4

7.3RecommendedOperatingConditions....5

7.4ThermalInformation....5

7.5 Electrical Characteristics....6

7.6TimingRequirements,SN54LVC573A....6

7.7TimingRequirements,SN74LVC573A....6

7.8SwitchingCharacteristics,SN54LVC573A 7

7.9SwitchingCharacteristics,SN74LVC573A....7

7.10OperatingCharacteristics....7

7.11 TypicalCharacteristics....7

8ParameterMeasurementInformation......8

9 Detailed Description 9

9.1Overview....9

9.2FunctionalBlockDiagram....9

9.3FeatureDescription....9

9.4DeviceFunctionalModes....9

10ApplicationsandImplementation....10

10.1 Application Information....10

10.2TypicalApplication....10

11PowerSupplyRecommendations....11

12 Layout.... 11

12.1 LayoutGuidelines....11

12.2LayoutExample....11

13DeviceandDocumentationSupport....12

13.1 RelatedLinks....12

13.2Trademarks....12

13.3ElectrostaticDischargeCaution....12

13.4Glossary....12

14Mechanical, Packaging, and Orderable Information 12

5 RevisionHistory

ChangesfromRevisionR(September2005)toRevisionS

Page

• Removed Ordering Information table. 1
• Updated device temperature ratings. 4
• Added Handling Ratings. 4
• Added Typical Characteristics. 7
• Added Detailed Description section. 9
• Added Applications and Implementation section. 10
• Added Power Supply Recommendations section.... 11
• Added Layout section. 11

6PinConfigurationandFunctions

SN54LVC573A...J OR W PACKAGE

SN74LVC573A...DB, DGV, DW, N,

NS, OR PW PACKAGE

(TOP VIEW)

OE 1 20 VCC 1D 2 19 1Q 2D 3 18 2Q 3D 4 17 3Q 4D 5 16 4Q 5D 6 15 5Q 6D 7 14 6Q 7D 8 13 7Q 8D 9 12 8Q GND 10 11 LE

SN74LVC573A...RGY PACKAGE

(TOP VIEW)

OE VCC 1 20 1D 2 19 1Q 2D 3 18 2Q 3D 4 17 3Q 4D 5 16 4Q 5D 6 15 5Q 6D 7 14 6Q 7D 8 13 7Q 8D 9 12 8Q GND LE

SN54LVC573A...FK PACKAGE

(TOP VIEW)

2D 1D OE VCC 3D 4 3 2 1 20 19 4D 5 18 2Q 5D 6 17 3Q 6D 7 16 4Q 7D 8 15 5Q 8D 9 14 6Q GND LE 11 12 13 8Q 7Q

GQN OR ZQN PACKAGE

(TOP VIEW)

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) ThevalueofV CC is provided in therecommended operating condition stable.
(4) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7.
(5) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-5.

7.2HandlingRatings

			MIN	MAX	UNIT
T_stg	Storagetemperaturerange		-65	150	°C
V_(ESD)	Electrostaticdischarge	Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,all pins ^(1)	0	2000	V
		Chargeddevicemodel(CDM),perJEDECspecification JESD22-C101,allpins ^(2)	0	1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 500 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.

7.3RecommendedOperatingConditions (1)

			SN54LVC573ASN74LVC573A			UNIT
			MINMAXMINMAX
V_CC	SupplyvoltageV	Operating23.61.653.6
		Dataretentiononly1.5	1.5
V_IH	High-levelinputvoltage	V_CC=1.65Vto1.95V	0.65× V_CC			V
		V_CC=2.3Vto2.7V		1.7
		V_CC=2.7Vto3.6V	2	2
V_IL	Low-levelinputvoltage	V_CC=1.65Vto1.95V		0.35× V_CC		V
		V_CC=2.3Vto2.7V		0.7
		V_CC=2.7Vto3.6V	0.8	0.8
V_I	Inputvoltage		05.505.5	V
V_O	Outputvoltage	Highorlowstate	0 V_CC	0	V_CC	V
		3-state	05.505.5
I_OH	High-leveloutputcurrent	V_CC=1.65V		-4		mA
		V_CC=2.3V		-8
		V_CC=2.7V	-12	-12
		V_CC=3V	-24	-24
I_OL	Low-leveloutputcurrent	V_CC=1.65V		4		mA
		V_CC=2.3V		8
		V_CC=2.7V	12	12
		V_CC=3V	24	24
t/ v	Input transition rise or fall rate		6	6		ns/V
T_A	Operating free-air temperature		-55 125	-40	85	°C

(1) AllunusedinputsofthedevicemustbeheldatV CC or GNDtoensureproperdeviceoperation. RefertotheTIapplicationreport, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

7.4ThermalInformation

THERMALMETRIC (1)		SN74LVC573A	UNIT
		PW
		20PINS
R_ JA	Junction-to-ambientthermalresistance	102.5	°C/W
R_ JCtop	Junction-to-case(top)thermalresistance	35.9
R_ JB	Junction-to-boardthermalresistance	53.5
_JT	Junction-to-topcharacterizationparameter	2.2
_JB	Junction-to-boardcharacterizationparameter	52.9

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)

PARAMETERTESTCONDITIONSV			cc	SN54LVC573ASN74LVC573A				UNIT
				MINTYP (1) MAX		MINTYP (1) MAX
V_OH	I_OH = -100μA		1.65Vto3.6VV			cc-0.2		V
			2.7Vto3.6VV	cc-0.2
	I_OH = -4mA		1.65V			1.2
	I_OH = -8mA		2.3V			1.7
	I_OH = -12mA		2.7V	2.2		2.2
			3V	2.4		2.4
	I_OH = -24mA		3V	2.2		2.2
V_OL	I_OL = 100μA		1.65Vto3.6V				0.2	V
			2.7Vto3.6V	0.2
	I_OL = 4mA		1.65V				0.45
	I_OL = 8mA		2.3V				0.7
	I_OL = 12mA		2.7V0.4	0.4
	I_OL = 24mA		3V	0.55		0.55
I_I	V_I = 0 to 5.5 V		3.6 V	±5		±5		μA
I_off	V_I or V_O = 5.5V		0			±10		μA
I_bz	V_O = 0 to 5.5 V		3.6 V	±15		±10		μA
I_CC	V_I = V_CC or GND	I_O = 0	3.6V	10		10		μA
	3.6V≤ V_I ≤ 5.5V^2)			10		10
I_CC	Oneinputat V_CC -0.6V ,Otherinputsat V_CC or GND		2.7Vto3.6V	500		500		μA
C_i	V_I = V_CC or GND		3.3V	4		4pF
C_o	V_O = V_CC or GND		3.3V	5.5		5.5pF

(1) AlltypicalvaluesareatV CC=3.3V,TA=25^.
(2) This applies in the disabled state only.

7.6TimingRequirements,SN54LVC573A

overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3)

		SN54LVC573A		UNIT
		V_CC=2.7V	V_CC=3.3V±0.3V
		MIN MAX	MIN MAX
t_w	Pulseduration,LEhigh	3.3	3.3ns
t_su	Setuptime,databeforeLE↓	22ns
t_h	Holdtime,dataafterLE↓	2.5	2.5ns

7.7TimingRequirements,SN74LVC573A

overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3)

		SN74LVC573A						UNIT
		V_CC=1.8V±0.15V	V_CC=2.5V±0.2V		V_CC=2.7V		V_CC=3.3V±0.3V
		MIN MAX	MIN MAX		MIN MAX		MIN MAX
t_w	Pulseduration,LEhigh	94	3.3		3.3ns
t_su	Setuptime,databeforeLE↓	6422ns
t_n	Hold time, data after LE↓	4	2		1.5		1.5	ns

7.8SwitchingCharacteristics, SN54LVC573A

overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3)

PARAMETER	FROMTOV(INPUT)	(OUTPUT)	SN54LVC573A				UNIT
			V_CC=2.7V		cc=3.3V±0.3V
			MIN	MAX	MIN	MAX
t_pd	D	Q		7.71	6.9		ns
	LE			8.41	7.7
t_en	OE	Q		8.5	1	7.5	ns
t_dis	OE	Q		7	0.5	6.7	ns

7.9 Switching Characteristics, SN74LVC573A

overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	SN74LVC573A								UNIT
			V_CC=1.8V ± 0.15V		V_CC=2.5V ± 0.2V		V_CC=2.7V		V_CC=3.3V ± 0.3V
			MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX
t_pd	D	Q	1	19.1	1	9.6	1	7.7	1.5	6.9	ns
	LE		1	22.8	1	10.5	1	8.4	2	7.7
t_en		Q	1	20	1	10.5	1	8.5	1.5	7.5	ns
t_dis		Q	1	19.3	1	7.8	1	7	1.6	6.5	ns
t_sk(o)										1	ns

7.10 Operating Characteristics

T_A=25^

PARAMETER			TEST CONDITIONS	V_CC=1.8V	V_CC=2.5V	V_CC=3.3V	UNIT
				TYP	TYP	TYP
C_pd	Powerdissipation capacitance perlatch	Outputs enabled	f=10MHz	61	56	37	pF
		Outputs disabled		3	3	4

7.11 Typical Characteristics

Figure 1. SN74LVC573A LE to Q TDP Vcc vs TPD at 25°C

Figure 2. SN74LVC573A LE to Q Across Temp 3.3V Vcc

8ParameterMeasurementInformation

From Output Under Test CL (see Note A) RL RL S1 VLOAD Open GND

LOAD CIRCUIT

TEST S1
t_PLH/t_PHL	Open
t_PLZ/t_PZL	V_LOAD
t_PHZ/t_PZH	GND

V_CC	INPUTS		V_M	V_LOAD	C_L	R_L	V_
	V_I	t_r/t_f
1.8 V ± 0.15 V	V_CC	≤2 ns	V_CC/2	2 · V_CC	30 pF	1 kΩ	0.15 V
2.5 V ± 0.2 V	V_CC	≤2 ns	V_CC/2	2 · V_CC	30 pF	500 Ω	0.15 V
2.7 V	2.7 V	≤2.5 ns	1.5 V	6 V	50 pF	500 Ω	0.3 V
3.3 V ± 0.3 V	2.7 V	≤2.5 ns	1.5 V	6 V	50 pF	500 Ω	0.3 V

Input V_M t_W V_I V_M 0 V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O = 50 .
D. The outputs are measured one at a time, with one transition per measurement.
E. t_PLZ and t_PHZ are the same as t_dis .
F. t_PZL and t_PZH are the same as t_en .
G. t_PLH and t_PHL are the same as t_pd .
H. All parameters and waveforms are not applicable to all devices.

Figure3.LoadCircuitandVoltageWaveforms

9DetailedDescription

9.1 Overview

TheSN54LVC573AoctaltransparentD-typelatchisdesignedfor2.7-Vto3.6-VV CC operation,andthe SN74LVC573AoctaltransparentD-typelatchisdesignedfor1.65-Vto3.6-VV CC operation.Thesedevices feature3-stateoutputsdesignedspecificallyfordrivinghighlycapacitiveorrelativelylow-impedanceloads.They areparticularlysuitableforimplementingbufferregisters,input/output(I/O)ports,bidirectionalbusdrivers,and workingregisters.Whilethelatch-enable(LE)inputishigh,theQoutputsfollowthedata(D)inputs.WhenLEis____takenlow,theQoutputsarelatchedatthelogiclevelsattheDinputs.Abufferedoutput-enable(OE)inputcan beusedtoplacetheeightoutputsineitheranormallogicstate(highorlowlogiclevels)orthehigh-impedance state.Inthehigh-impedancestate,theoutputsneitherloadnordrivethebuslinessignificantly.Thehigh- impedancestateandincreaseddriveprovidethecapabilitytodrivebuslineswithoutinterfaceorpullup components.OEdoesnotaffecttheinternaloperationsofthelatches.Olddatacanberetainedornewdatacan beenteredwhiletheoutputsareinthehigh-impedancestate.Thesedevicesarefullyspecifiedforpartial-powerdownapplicationsusingl off.Thel off circuitrydisablestheoutputs,preventingdamagingcurrentbackflowthrough thedevicewhenitispowereddown.

9.2 FunctionalBlockDiagram

graph TD
    OE["OE"] -->|1| A["NOT"]
    LE["LE"] -->|11| B["NOT"]
    1D["1D"] -->|2| C["C1 1D"]
    C --> D["NOT"]
    D --> E["19"]
    E --> F["1Q"]
    C --> G["To Seven Other Channels"]
    style C1 fill:#f9f,stroke:#333
    style D fill:#ccf,stroke:#333
    style E fill:#cfc,stroke:#333

Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages.

9.3FeatureDescription

•Wideoperatingvoltagerange
- Operatesfrom1.65Vto3.6V
- Allowsdownvoltagetranslation
- Inputsacceptvoltagesto5.5V
- I_off Feature
- Allows voltages on the inputs and outputs when V CC is 0V

9.4DeviceFunctionalModes

FunctionTable (EachLatch)

INPUTS			OUTPUTQ
	LE	D
L	H	H	H
L	H	L	L
L	L	X	Q_0
H	X	X	Z

10ApplicationsandImplementation

10.1 Application Information

TheSN74LVC573AisahighdriveCMOSdevicethatcanbeusedforamultitudeofbusinterfacetype applicationswherethedataneedstoberetainedorlatched.Itcanproduce24mAofdrivecurrentat3.3V makingitIdealfordrivingmultipleoutputsandgoodforhighspeedapplicationsupto100MHz.Theinputsare 5.5VtolerantallowingittotranslatedowntoV CC.

10.2 Typical Application

graph TD
    A["Regulated 3.6 V"] --> B["uC or System Logic"]
    B --> C["OE"]
    B --> D["LE"]
    B --> E["1D"]
    B --> F["2D"]
    B --> G["3D"]
    B --> H["4D"]
    B --> I["5D"]
    B --> J["6D"]
    B --> K["GND"]
    L["uC System Logic LEDs"] --> M["Output"]
    style A fill:#f9f,stroke:#333
    style L fill:#ccf,stroke:#333

10.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Careshould be takento avoid bus contention because it can drive current that would exceed maximum limits. The high drivewill also create fast edges into light loadssorouting and load condition should be considered to prevent ringing.

10.2.2 Detailed Design Procedure

1. Recommended Input conditions

2. Rise time and fall time specifications. See ( t / V) in Recommended Operating Conditions table.
   -Specifiedhighandlowlevels.See(V IH andV IL )inRecommendedOperatingConditionstable.
   -Inputsareovervoltagetolerantallowingthemtogoashighas5.5VatanyvalidV cc-

3. Recommend output conditions

-Loadcurrentsshouldnotexceed25mAperoutputand50mAtotalforthepart.
-OutputsshouldnotbepulledaboveV cc-

TypicalApplication(continued)

10.2.3 ApplicationCurves

Figure4.SN74LVC573AI cc vsFrequency

11 Power Supply Recommendations

The powersupply can be any voltage between the Min and Max supply voltage rating located in the Recommended Operating Condition stable.

EachV _cc pinshouldhaveagoodbypasscapacitortopreventpowerdisturbance. For devices with a single supply, a 0.1- F capacitor is recommended. If there are multiple VCC pins, then a 0.01- F or 0.022- F capacitor is recommended for each powerpin. It is a parallel multiple bypass capacitor store reject different frequencies of noise. A 0.1- F and 1- F capacitors are commonly used in parallel. The bypass capacitor should be installed as closetothepowerpin as possible for best results.

12 Layout

12.1 LayoutGuidelines

When using multiple bit logic devices input should not be overweight. In many cases, functions or part so functions of digital logic devices are unused, for example, when only two input to a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pin should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused input to digital logic devices must be connected to a high or low biastoprevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GNDorV CC whichever makemoresense or is more convenient. It is generally OK to float outputs unless the part is a transceiver. If the transceiver has an output enable pinit will disable the output section of the part when asserted. This will not disable the input section of the Osso they also cannot float when disabled.

12.2 LayoutExample

VCC Unused Input Input Output Output

Input Unused Input

13DeviceandDocumentationSupport

13.1 RelatedLinks

Thetablebelowlistsquickaccesslinks. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.

Table1.RelatedLinks

PARTSPRODU	CTFOLDERSAMPLE&	BUY	TECHNICALTOOLS&SUPPORT& DOCUMENTSSOFTWARE	COMMUNITY
SN54LVC573A	Click here	Click here	Click here	Click here
SN74LVC573A	Click here	Click here	Click here	Click here

13.2 Trademarks

Alltrademarksarethepropertyoftheirrespectiveowners.

13.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.

13.4 Glossary

SLYZ022 — TIGlossary.

This glossarylistsandexplainsterms,acronymsanddefinitions.

14Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this datasheet, refertotheleft-handnavigation.

PACKAGING INFORMATION

Orderable Device Status(1)		Package Type	Package Drawing	Pins	Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4/5)	Samples
5962-9757501Q2A ACTIVE LCCC FK 20 1 Non-RoHS						& Green	SNPB N / A for Pkg Type -55 to 125 5962-			9757501Q2A SNJ54LVC 573AFK	Samples
5962-9757501QRA ACTIVE CDIP J 20 1 Non-RoHS						& Green	SNPB N / A for Pkg Type -55 to 125 5962-9757501QR			A SNJ54LVC573AJ	Samples
5962-9757501QSA ACTIVE CFP W 20 1 Non-RoHS						& Green	SNPB N / A for Pkg Type -55 to 125 5962-9757501QS			A SNJ54LVC573AW	Samples
SN74LVC573ADBR	ACTIVE	SSOP	DB	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LC573A	Samples
SN74LVC573ADBRG4	ACTIVE	SSOP	DB	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LC573A	Samples
SN74LVC573ADGVR	ACTIVE	TVSOP	DGV	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LC573A	Samples
SN74LVC573ADW	ACTIVE	SOIC	DW	20	25	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LVC573A	Samples
SN74LVC573ADWR	ACTIVE	SOIC	DW	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LVC573A	Samples
SN74LVC573ADWRG4	ACTIVE	SOIC	DW	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LVC573A	Samples
SN74LVC573AN	ACTIVE	PDIP	N	20	20	RoHS & Non-Green	NIPDAU	N / A for Pkg Type -40 to 125 SN74LVC573AN			Samples
SN74LVC573ANSR	ACTIVE	SO	NS	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LVC573A	Samples
SN74LVC573ANSRE4	ACTIVE	SO	NS	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LVC573A	Samples
SN74LVC573APW	ACTIVE	TSSOP	PW	20	70	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LC573A	Samples
SN74LVC573APWG4	ACTIVE	TSSOP	PW	20	70	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LC573A	Samples
SN74LVC573APWR	ACTIVE	TSSOP	PW	20	2000	RoHS & Green	NIPDAU | SN	Level-1-260C-UNLIM	-40 to 125	LC573A	Samples
SN74LVC573APWRE4	ACTIVE	TSSOP	PW	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LC573A	Samples
SN74LVC573APWRG4	ACTIVE	TSSOP	PW	20	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LC573A	Samples
Orderable Device Status(1)		Package Type	Package Drawing	Pins	Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4-5)	Samples
SN74LVC573APWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC573A											Samples
SN74LVC573APWTG4 ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC573A											Samples
SN74LVC573ARGYR	ACTIVE	VQFN	RGY	20	3000	RoHS & Green	NIPDAU	Level-2-260C-1 YEAR	-40 to 125	LC573A	Samples
SNJ54LVC573AFK	ACTIVE	LCCC FK	20 1 Non-RoHS			& Green	SNPB N / A for Pkg Type	-55 to 125	5962-	9757501Q2ASNJ54LVC573AFK	Samples
SNJ54LVC573AJ	ACTIVE	CDIP	J	20	1	Non-RoHS & Green	SNPB N / A for Pkg Type	-55 to 125	5962-9757501QRASNJ54LVC573AJ	Samples
SNJ54LVC573AW	ACTIVE	CFP	W	20	1	Non-RoHS & Green	SNPB N / A for Pkg Type	-55 to 125	5962-9757501QASNJ54LVC573AW	Samples

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be Inside parentheses. Only one Device Marking contained in parentheses and separated by a "\~" will appear on a device. If a line is Indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54LVC573A, SN74LVC573A :

• Catalog : SN74LVC573A
• Automotive : SN74LVC573A-Q1, SN74LVC573A-Q1
• Enhanced Product : SN74LVC573A-EP, SN74LVC573A-EP
• Military : SN54LVC573A

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package	Type	Package Drawing	Pins	SPQ Reel	Diameter (mm)	Reel Width W1 (mm)	A0 (mm)	B0 (mm)	K0 (mm)	P1 (mm)	W (mm)	Pin1 Quadrant
SN74LVC573ADBR SS	OP DB 20	2000 330.0	16.4	8.2 7.5 2.5	12.0 16.0	Q1
SN74LVC573ADGVR TV	VSOP DGV	20 2000	830.0	2.4 6.9 5.6	1.6 8.0	12.0 Q1
SN74LVC573ADWR SO	SIC DW 20	2000 330.0	24.4	10.9 13.3	2.7 12.0	24.0 Q1
SN74LVC573ANSR SC	NS 20 2000	330.0	24.4 8.4	13.0 2.5	12.0 24.0	Q1
SN74LVC573APWR TS	SOP PW	20 2000 330.0	16.4	6.95 7.1	1.6 8.0	16.0 Q1
SN74LVC573APWR TS	SOP PW	20 2000 330.0	16.4	6.95 7.0	1.4 8.0	16.0 Q1
SN74LVC573APWRG4 T	SSOP PW	20 2000 330.0	16.4	6.95 7.0	1.4 8.0	16.0 Q1
SN74LVC573APWT TS	SOP PW	20 250 330.0	16.4	6.95 7.1	1.6 8.0	16.0 Q1
SN74LVC573ARGYR V	QFN RGY	20 3000 330.0	12.4	3.8 4.8	1.6 8.0	12.0 Q1

TAPE AND REEL BOX DIMENSIONS W L

*All dimensions are nominal

Device	Package Type	Package Drawing	Pins	SPQ	Length (mm)	Width (mm)	Height (mm)
SN74LVC573ADBR SSOP DB 20 2000 853.0 449.0 35.0
SN74LVC573ADGVR TVSOP DGV 20 2000 853.0 449.0 35.0
SN74LVC573ADWR SOC DW 20 2000 367.0 367.0 45.0
SN74LVC573ANSR SONS 20 2000 367.0 367.0 45.0
SN74LVC573APWR TSSOP	PW	20	2000	364.0	364.0	27.0
SN74LVC573APWR TSSOP	PW	20	2000	853.0	449.0	35.0
SN74LVC573APWRG4 TSSOP	PW	20	2000	853.0	449.0	35.0
SN74LVC573APWT TSSOP	PW	20	250	853.0	449.0	35.0
SN74LVC573ARGYR VQFN	RGY 20 3000 853.0 449.0 35.0

TUBE

T - Tube height L - Tube length W - Tube width B - Alignment groove width

*All dimensions are nominal

Device	Package Name	Package Type	Pins	SPQ	L (mm)	W (mm)	T (μm)	B (mm)
5962-9757501Q2A FK	CCC 20 1 506.98	12.06 2030 NA
SN74LVC573ADW	DW	SOIC	20	25	507	12.83	5080	6.6
SN74LVC573AN	N	PDIP	20	20	506	13.97	11230	4.32
SN74LVC573APW	PW	TSSOP	20	70	530	10.2	3600	3.5
SN74LVC573APWG4	PW	TSSOP	20	70	530	10.2	3600	3.5
SNJ54LVC573AFK	FK LCCC 20 1 506.98	12.06 2030 NA

W (R-GDFP-F20)

CERAMIC DUAL FLATPACK

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification only.

E. Falls within Mil-Std 1835 GDFP2-F20

SMALL OUTLINE PACKAGE

A 6.6 TYP 6.2 PIN 1 INDEX AREA 1 20 18X 0.65 6.6 6.4 NOTE 3 2X 5.85 10 11 20X 0.30 0.19 B 4.5 4.3 NOTE 4 ⊕ 0.1@ A B

C SEATING PLANE 0.1 C 1.2 MAX

SEE DETAIL A (0.15) TYP

GAGE PLANE 0.25 0.15 0.05 0°-8° 0.75 0.50 DETAIL A TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

SMALL OUTLINE PACKAGE

20X (1.5) 1 20X (0.45) 18X (0.65) 10 (5.8) SYMM (R0.05) TYP 20 SYMM 11

LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN SCALE: 10X

SOLDER MASK OPENING METAL EXPOSED METAL 0.05 MAX ALL AROUND

NON-SOLDER MASK DEFINED (PREFERRED)

METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL 0.05 MIN ALL AROUND

SOLDER MASK DETAILS

4220206/A 02/2017

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SMALL OUTLINE PACKAGE

20X (1.5) 1 20X (0.45) 18X (0.65) 10 (5.8) SYMM (5.8) SYMM 20 (R0.05) TYP 11

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220206/A 02/2017

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

PW (R-PDSO-G20)

Example Board Layout

18x0,65 5,6 Example Non Soldermask Defined Pad Example Solder Mask Opening (See Note E) 0,3 1,6 0,07 Pad Geometry All Around

Based on a stencil thickness of .127mm (.005inch).

20x0,25 1,55 5,6 18x0,65

4211284-5/G 08/15

NOTES:

A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate design.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

FK (S-CQCC-N**)

28 TERMINAL SHOWN

LEADLESS CERAMIC CHIP CARRIER

NO. OF TERMINALS**	A		B
	MIN	MAX	MIN	MAX
20	0.342(8,69)	0.358(9,09)	0.307(7,80)	0.358(9,09)
28	0.442(11,23)	0.458(11,63)	0.406(10,31)	0.458(11,63)
44	0.640(16,26)	0.660(16,76)	0.495(12,58)	0.560(14,22)
52	0.740(18,78)	0.761(19,32)	0.495(12,58)	0.560(14,22)
68	0.938(23,83)	0.962(24,43)	0.850(21,6)	0.858(21,8)
84	1.141(28,99)	1.165(29,59)	1.047(26,6)	1.063(27,0)

4040140/D 01/11
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. Falls within JEDEC MS-004

SMALL OUTLINE PACKAGE

A 8.2 7.4 TYP PIN 1 INDEX AREA 1 20 18X 0.65 7.5 6.9 NOTE 3 2X 5.85 10 11 20X 0.38 0.22 B 5.6 5.0 NOTE 4 ⊕ 0.1@ A B

C 0.1 C SEATING PLANE

SEE DETAIL A (0.15) TYP

GAGE PLANE 0.25 0° -8° 0.95 0.55 2 MAX 0.05 MIN

DETAIL A TYPICAL

4214851/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.

SMALL OUTLINE PACKAGE

20X (1.85) SYMM (0.45) 1 20X 18X (0.65) 10 (7) (R0.05) TYP 20 SYMM 11

LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN SCALE: 10X

SOLDER MASK OPENING METAL EXPOSED METAL 0.07 MAX ALL AROUND

NON-SOLDER MASK DEFINED (PREFERRED)

METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL 0.07 MIN ALL AROUND

SOLDER MASK DETAILS

4214851/B 08/2019

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SMALL OUTLINE PACKAGE

20X (1.85) SYMM (0.45) 20X 1 18X (0.65) 10 (7) (R0.05) TYP 20 SYMM 11

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4214851/B 08/2019

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

MECHANICAL DATA

NS (R-PDSO-G\*\*)

PLASTIC SMALL-OUTLINE PACKAGE

14-PINS SHOWN

1,27 14 0,51 0,35 Ø 0,25① 8 5,60 5,00 8,20 7,40 1 7 A

0,15 NOM Gage Plane 0,25 0°-10° 1,05 0,55

2,00 MAX 0,15 0,05

Seating Plane 0.10

DIM\PINS **	14	16	20	24
A MAX	10,50	10,50	12,90	15,30
A MIN	9,90	9,90	12,30	14,70

4040062/C 03/03

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.

B 14 8 C 1 0.065 (1,65) 0.045 (1,14)

PINS **DIM	14	16	18	20
A	0.300(7,62)BSC	0.300(7,62)BSC	0.300(7,62)BSC	0.300(7,62)BSC
B MAX	0.785(19,94)	.840(21,34)	0.960(24,38)	1.060(26,92)
B MIN	—	—	—	—
C MAX	0.300(7,62)	0.300(7,62)	0.310(7,87)	0.300(7,62)
C MIN	0.245(6,22)	0.245(6,22)	0.220(5,59)	0.245(6,22)

0.005 (0,13) MIN 0.060 (1,52) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.026 (0,66) 0.014 (0,36) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) A 0°-15°

4040083/F 03/03

NOTES:

A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package is hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18 and GDIP1-T20.

DGV (R-PDSO-G\*\*) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

DIM\PINS **	14		20		382416	48	56
A MAX	3,70		5,10	5,103,70	7,90	9,80	11,40
A MIN	3,50	3,50	4,90	4,90	7,70	9,60	11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 per side.
D. Falls within JEDEC: 24/48 Pins - MO-153

14/16/20/56 Pins - MO-194

This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details.

TEXAS INSTRUMENTS

4225320/A 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

EXPOSED METAL SHOWN
SCALE:18X

0.07 MAX ALL AROUND METAL EXPOSED METAL SOLDER MASK OPENING

NON SOLDER MASK
DEFINED
(PREFERRED)

0.07 MIN ALL AROUND SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK

SOLDER MASK
DEFINED
SOLDER MASK DETAILS

4225320/A 09/2019

NOTES: (continued)

1. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
2. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

N (R-PDIP-T\*\*)

16 PINS SHOWN

PLASTIC DUAL-IN-LINE PACKAGE

A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) 0.045 (1,14)

C

DIM\PINS **	14	16	18	20
A MAX	0.775(19,69)	0.775(19,69)	0.920(23,37)	1.060(26,92)
A MIN	0.745(18,92)	0.745(18,92)	0.850(21,59)	0.940(23,88)
MS-001VARIATION	AA	BB	AC	AD

0.045 (1,14) 0.030 (0,76) D 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) ⊕ 0.010 (0,25) M 14/18 Pin Only 20 Pin vendor opt

0.325 (8,26) 0.300 (7,62) 0.015 (0,38) Gauge Plane 0.010 (0,25) NOM 0.430 (10,92) MAX

4040049/E 12/2002

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C Falls within JEDEC MS-001, except 18 and 20 pin minimum body length (Dim A).

The 20 pin end lead shoulder width is a vendor option, either half or full width.

SOIC

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

SOIC

20X (2) 1 20X (0.6) 18X (1.27) (R0.05) TYP 10 SYMM 20 SYMM 11 (9.3)

LAND PATTERN EXAMPLE SCALE:6X

SOLDER MASK OPENING METAL 0.07 MAX ALL AROUND

NON SOLDER MASK DEFINED

METAL UNDER SOLDER MASK SOLDER MASK OPENING 0.07 MIN ALL AROUND

SOLDER MASK DEFINED
SOLDER MASK DETAILS

4220724/A 05/2016

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SOIC

20X (2) 1 20X (0.6) 18X (1.27) SYMM 20 SYMM 10 (9.3) 11

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

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