SN74CBTLV3251DR - Electronic component TEXAS INSTRUMENTS - Free user manual and instructions

USER MANUAL SN74CBTLV3251DR TEXAS INSTRUMENTS

● 5-Ω Switch Connection Between Two Ports
●Rail-to-Rail Switching on Data I/O Ports
●I off Supports Partial-Power-Down Mode Operation

D, DBQ, DGV, OR PW PACKAGE (TOP VIEW)

B4 1 16 VCC B3 2 15 B5 B2 3 14 B6 B1 4 13 B7 A 5 12 B8 NC 6 11 S0 OE 7 10 S1 GND 8 9 S2

NC - No internal connection

●Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

RGY PACKAGE (TOP VIEW)

B4 VCC 1 16 B3 2 15 B5 B2 3 14 B6 B1 4 13 B7 A 5 12 B8 NC 6 11 S0 OE 7 10 S1 8 9 GND S2

NC – No internal connection

description/ordering information

The SN74CBTLV3251 device is a 1-of-8 high-speed FET multiplexer/demultiplexer. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The select inputs (S0, S1, S2) control the data flow. The FET multiplexers/demultiplexers are disabled when the output-enable (OE) input is high.

This device is fully specified for partial-power-down applications using I_off . The I_off feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

T_A	PACKAGE^†		ORDERABLEPART NUMBER	TOP-SIDEMARKING
-40°C to 85°C	QFN - RGY Tape and reel SN74CBTLV3		251RGYR CL251
	SOIC - D	Tube SN74CBTLV3251D		CBTLV3251
		Tape and reel SN74CBTLV3251DR
	SSOP (QSOP) - DBQ Tape and reel SN74CBTLV3251DBQR CL251
	TSSOP - PW Tape and reel SN74CBTLV3251PWR CL251
	TVSOP - DGV Tape and reel SN74CBTLV3251DGVR CL251

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCDS054I - MARCH 1998 - REVISED OCTOBER 2003

FUNCTION TABLE

INPUTS	FUNCTION
OE S2 S1 S0
LLLLA port = B1 port
LLLLHA port = B2 port
LLLLHA port = B3 port
LLLLHA port = B4 port
LLLLA port = B5 port
LLLLHA port = B6 port
LLLLHA port = B7 port
LLLLHA port = B8 port
HXXX Disconnect

logic diagram (positive logic)

graph TD
    subgraph Inputs
        A["5"] --> SW1["SW"]
        A --> SW2["SW"]
        A --> SW3["SW"]
        A --> SW4["SW"]
        A --> SW5["SW"]
        A --> SW6["SW"]
        A --> SW7["SW"]
        A --> SW8["SW"]
        A --> SW9["SW"]
    end
    subgraph Outputs
        B1["4"] --> SW1
        B2["3"] --> SW2
        B3["2"] --> SW3
        B4["1"] --> SW4
        B5["15"] --> SW5
        B6["14"] --> SW6
        B7["13"] --> SW7
        B8["12"] --> SW8
        B0["11"] --> NAND1["NAND"]
        S0["10"] --> NAND2["NAND"]
        S1["9"] --> NAND3["NAND"]
        S2["7"] --> NAND4["NAND"]
        OE["OE"] --> NAND5["NAND"]
    end
    SW1 --> NAND1
    SW1 --> NAND2
    SW1 --> NAND3
    SW1 --> NAND4
    SW1 --> NAND5
    SW2 --> NAND1
    SW2 --> NAND2
    SW2 --> NAND3
    SW2 --> NAND4
    SW2 --> NAND5
    SW3 --> NAND1
    SW3 --> NAND2
    SW3 --> NAND3
    SW3 --> NAND4
    SW3 --> NAND5
    SW4 --> NAND1
    SW4 --> NAND2
    SW4 --> NAND3
    SW4 --> NAND4
    SW4 --> NAND5
    SW5 --> NAND1
    SW5 --> NAND2
    SW5 --> NAND3
    SW5 --> NAND4
    SW5 --> NAND5
    SW6 --> NAND1
    SW6 --> NAND2
    SW6 --> NAND3
    SW6 --> NAND4
    SW6 --> NAND5
    SW7 --> NAND1
    SW7 --> NAND2
    SW7 --> NAND3
    SW7 --> NAND4
    SW7 --> NAND5
    SW8 --> NAND1
    SW8 --> NAND2
    SW8 --> NAND3
    SW8 --> NAND4
    SW8 --> NAND5

simplified schematic, each FET switch

A B (OE)

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage range, V_CC -0.5 V to 4.6 V

Input voltage range, V_I (see Note 1) -0.5 V to 4.6 V

Continuous channel current 128 mA

Input clamp current, I_K(V_I/O < 0) -50 mA

Package thermal impedance, _JA (see Note 2): D package 73°C/W

(see Note 2): DBQ package 90°C/W

(see Note 2): DGV package 120°C/W

(see Note 2): PW package 108°C/W

(see Note 3): RGY package 39°C/W

Storage temperature range, T_stg -65°C to 150°C

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

1. The package thermal impedance is calculated in accordance with JESD 51-7.

2. The package thermal impedance is calculated in accordance with JESD 51-5.

recommended operating conditions (see Note 4)

		MIN	MAX	UNIT
V_CC Supply voltage		2.3	3.6	V
V_IH High-level control input voltage	V_CC = 2.3 V to 2.7 V	1.7		V
	V_CC = 2.7 V to 3.6 V	2
V_IL Low-level control input voltage	V_CC = 2.3 V to 2.7 V		0.7	V
	V_CC = 2.7 V to 3.6 V		0.8
T_A Operating free-air temperature		-40	85	°C

NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

SCDS054I - MARCH 1998 - REVISED OCTOBER 2003

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP					MAX UNIT
V_IK		V_CC=3V,I I=-18mA-1.2V
I_I		V_CC=3.6V,V I=V_CCor GND±1μA
I_off		V_CC=0,V I or V_O=0 to 3.6V 20μA
I_CC		V_CC=3.6V,I O=0, V_I=V_CCor GND			10 μA
I_CC^	Control inputs	V_CC=3.6V, One input at 3V, Other inputs at V CC or GND			300 μA
C_i	Control inputs	V_I=3V or 0			3	pF
C_io(OFF)	A port	V_O=3V or 0, =V_CC			40.5	pF
	B port				6
r_on		V_CC=2.3V,TYP at V_CC=2.5V	V_I=0	I_I=64mA	5 8	Ω
				I_I=24mA	5 8
			V_I=1.7V, I_I=15mA		27 40
		V_CC=3V	V_I=0	I_I=64mA	5 7
				I_I=24mA	5 7
			V_I=2.4V, I_I=15mA		10 15

All typical values are at V_CC = 3.3 V (unless otherwise noted) , T_A = 25^ .
This is the increase in supply current for each input that is at the specified voltage level, rather than V_CC or GND.
Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals.

switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	V_CC = 2.5 V ± 0.2 V		V_CC = 3.3 V ± 0.3 V		UNIT
			MIN	MAX	MIN	MAX
t_pd	A or B¶	B or A	0.15		0.25		ns
	S	A	16.1		15.3
t_en	S	B	14.1		13.6	ns
t_dis	S	B	13.5		13.3	ns
t_en		A or B	1	5.2	1	4.5	ns
t_dis		A or B	1	6.7	1	7.2	ns

The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).

PARAMETER MEASUREMENT INFORMATION

From Output Under Test CL (see Note A) RL RL S1 2 × VCC Open GND

LOAD CIRCUIT

TEST S1
t_PLH/t_PHL	Open
t_PLZ/t_PZL	2 × V_CC
t_PHZ/t_PZH	GND

V_CC	C_L	R_L	V_
2.5 V ±0.2 V	30 pF	500 Ω	0.15 V
3.3 V ±0.3 V	50 pF	500 Ω	0.3 V

Input VCC/2 tw VCC/2 0 V VCC

Timing Input VCC/2 0 V tsu th Data Input VCC/2 VCC/2 0 V

VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

Input VCC/2 VCC/2 0 V tPLH tPHL Output VCC/2 VCC/2 VOH VOL tPHL tPLH Output VCC/2 VCC/2 VOH VOL

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS

Output Control VCC/2 VCC/2 0 V Output Waveform 1 S1 at 2 × VCC (see Note B) tPZL VCC/2 tPLZ VCC VOL + VΔ VOL tPZH VCC/2 tPHZ VOH - VΔ VOH -0 V Output Waveform 2 S1 at GND (see Note B)

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C L includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, t_r ≤ 2 ns, t_f ≤ 2 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as t_dis

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as t_pd .

H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

TEXAS

INSTRUMENTS

www.ti.com

PACKAGE OPTION ADDENDUM

10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status(1)		Package Type	Package Drawing	Pins	Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4-5)	Samples
74CBTLV3251DBQRG4 ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 CL251											Samples
SN74CBTLV3251D	ACTIVE	SOIC	D	16	40	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	CBTLV3251	Samples
SN74CBTLV3251DBQR ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 CL251											Samples
SN74CBTLV3251DGVR	ACTIVE	TVSOP	DGV	16	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	CL251	Samples
SN74CBTLV3251DR	ACTIVE	SOIC	D	16	2500	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	CBTLV3251	Samples
SN74CBTLV3251PWR	ACTIVE	TSSOP	PW	16	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	CL251	Samples
SN74CBTLV3251RGYR ACTIVE VQFN RGY 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 CL251											Samples

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "\~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

TEXAS INSTRUMENTS

www.ti.com

PACKAGE OPTION ADDENDUM

10-Dec-2020

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package	Type	Package Drawing	Pins	SPQ Reel	Diameter (mm)	Reel Width W1 (mm)	A0 (mm)	B0 (mm)	K0 (mm)	P1 (mm)	W (mm)	Pin1 Quadrant
SN74CBTLV3251DBQR	SSOP DBQ	16 2500	330.0	12.5 6.4 5.2	2.1 8.0	12.0 Q1
SN74CBTLV3251DGVR	TVSOP DGV	16 2000	330.0	12.4 6.8	4.0 1.6	8.0 12.0 Q1
SN74CBTLV3251DR SOIC D	16 2500	330.0	16.4 6.5	10.3 2.1	8.0	16.0 Q1
SN74CBTLV3251PWR	TSSOP	PW	16	2000	330.0	12.4	6.9	5.6	1.6	8.0	12.0	Q1
SN74CBTLV3251RGYR	VQFN	RGY	16	3000	330.0	12.4	3.8	4.3	1.5	8.0	12.0	Q1

TAPE AND REEL BOX DIMENSIONS W L

*All dimensions are nominal

Device	Package Type	Package Drawing	Pins	SPQ	Length (mm)	Width (mm)	Height (mm)
SN74CBTLV3251DBQR S	SOP DBQ 16 2500	340.5 338.1 20.6
SN74CBTLV3251DGVR T	VSOP DGV 16 2000	853.0 449.0 35.0
SN74CBTLV3251DR SO	IC D 16	2500 340.5 336.1 32.0
SN74CBTLV3251PWR T	SSOP	PW 16 20	00 367.0	367.0 35.0
SN74CBTLV3251RGYR V	QFN RGY 16 3000	367.0 367.0 35.0

TUBE

T - Tube height L - Tube length W-Tube width B - Alignment groove width

*All dimensions are nominal

Device	Package Name	Package Type	Pins	SPQ	L (mm)	W (mm)	T (μm)	B (mm)
SN74CBTLV3251D D S	OIC 16 40 507 8 39	40 4.32

DGV (R-PDSO-G\*\*) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

DIM\PINS **	14		20		382416	48	56
A MAX	3,70		5,10	5,103,70	7,90	9,80	11,40
A MIN	3,50	3,50	4,90	4,90	7,70	9,60	11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 per side.
D. Falls within JEDEC: 24/48 Pins - MO-153

14/16/20/56 Pins - MO-194

SHRINK SMALL-OUTLINE PACKAGE

TYP.-244.228 -6.195.80[] PIN 1 ID AREA 16 14X .0250 [0.635] 16X -.012.008 -0.300.21[] NOTE 3 -.197.189 -5.004.81[] NOTE 4 B 8 9 2X .175 [4.45] 16X -.012.008 -0.300.21[] ⊕ .007 [0.17]@ A B S S SEATING PLANE .004 [0.1] C .069 MAX [1.75] TYP.-010.005 -0.250.13[] SEE DETAIL A .010 [0.25] GAGE PLANE 0° - 8° -.035.016 -0.880.41[] (.041) [1.04] -.010.004 -0.250.11[] DETAIL A TYPICAL 4214846/A 03/2014

NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.

SHRINK SMALL-OUTLINE PACKAGE

16X (.063) [1.6] 1 16X (.016) [0.41] 14X (.0250) [0.635] 8 SYM SEE DETAILS 16 9 (.213) [5.4]

LAND PATTERN EXAMPLE SCALE:8X

METAL SOLDER MASK OPENING .002 MAX [0.05] ALL AROUND

NON SOLDER MASK DEFINED

SOLDER MASK OPENING METAL .002 MIN [0.05] ALL AROUND

SOLDER MASK DEFINED
SOLDER MASK DETAILS

4214846/A 03/2014

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SHRINK SMALL-OUTLINE PACKAGE

SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.127 MM] THICK STENCIL SCALE:8X

4214846/A 03/2014

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

RGY (R-PVQFN-N16)

PLASTIC QUAD FLATPACK NO-LEAD

4,15 3,85 A 15 10 B 16 9 3,65 3,35 Pin 1 Index Area Top and Bottom 1 2 7 F 1,00 0,80 0,20 Nominal Lead Frame Seating Plane 0,05 0,00 C 0,08 C Seating Height 2,50 0,50 2 7 16X 0,50 0,30 1 THERMAL PAD 8 1,50 SIZE AND SHAPE SHOWN ON SEPRATE SHEET 9 16 15 10 16X 0,30 0,18 Φ 0,10 M C A B 0,05 M C

Bottom View
4203539-3/1 06/2011
NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
C. QFN (Quad Flatpack No-Lead) package configuration.
D. The package thermal pad must be soldered to the board for thermal and mechanical performance.
E. See the additional figure in the Product Data Sheet for details regarding the exposed thermal pad features and dimensions.
Pin 1 identifiers are located on both top and bottom of the package and within the zone indicated.
The Pin 1 identifiers are either a molded, marked, or metal feature.
G. Package complies to JEDEC MO-241 variation BA.

RGY (R-PVQFN-N16)

PLASTIC QUAD FLATPACK NO-LEAD

THERMAL INFORMATION

This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB). After soldering, the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC).

For information on the Quad Flatpack No-Lead (QFN) package and its advantages, refer to Application Report, QFN/SON PCB Attachment, Texas Instruments Literature No. SLUA271. This document is available at www.ti.com.

The exposed thermal pad dimensions for this package are shown in the following illustration.

2 7 Exposed Thermal Pad 1 8 2,05±0,10 16 9 15 10 2,55±0,10 Bottom View

Exposed Thermal Pad Dimensions

4206353-3/P 03/14

NOTE: All linear dimensions are in millimeters

RGY (R-PVQFN-N16)
PLASTIC QUAD FLATPACK NO-LEAD

Example Board Layout 4,80 Note D 4,30 2,60 1,50 2,05 0,85 x 16 PL 10x0,50 0,28 x 16 PL Non Solder Mask Defined Pad R0,14 0,07 All Around Example Solder Mask Opening (Note F) 0,85 0,28 Example Pad Geometry (Note C) Example Stencil Design 0.125mm Stencil Thickness (Note E) 4,75 4,25 2,65 1,50 1,07 0,30 x 2 PL 0,82 1,07 0,80 x 16 PL 10x0,50 0,23 x 16 PL 67% solder coverage by printed area on center thermal pad Example Via Layout Design may vary depending on constraints (Note D, F) 6xØ0,3 4208122-3/P 03/14

NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate designs.
D. This package is designed to be soldered to a thermal pad on the board. Refer to Application Note, Quad Flat-Pack QFN/SON PCB Attachment, Texas Instruments Literature No. SLUA271, and also the Product Data Sheets for specific thermal information, via requirements, and recommended board layout. These documents are available at www.ti.com http://www.ti.com.
E. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC 7525 for stencil design considerations.
F. Customers should contact their board fabrication site for minimum solder mask web tolerances between signal pads.

D (R-PDSO-G16)
PLASTIC SMALL OUTLINE

0.394 (10,00) 0.386 (9,80) 16 9 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,80) Pin 1 Index Area 1 8 0.050 (1,27) 0.020 (0,51) 0.012 (0,31) ⊕ 0.010 (0,25) M 0.069 (1,75) Max 0.010 (0,25) 0.004 (0,10) Gcuge Plane 0.010 (0,25) 0.005 (0,13) 0'-8" Seating Plane 0.010 (0,25) 0.050 (1,27) 0.016 (0,40) 4040047-6/M 06/11

NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.006 (0,15) each side.
Body width does not include interlead flash. Interlead flash shall not exceed 0.017 (0,43) each side.
E. Reference JEDEC MS-012 variation AC.

D (R-PDSO-G16)

4211283-4/E 08/12
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate designs.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

SMALL OUTLINE PACKAGE

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

SMALL OUTLINE PACKAGE

16X (1.5) 1 16X (0.45) SYMM (R0.05) TYP 16 SYMM 14X (0.65) 8 9 (5.8)

LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN SCALE: 10X

SOLDER MASK OPENING METAL EXPOSED METAL 0.05 MAX ALL AROUND

NON-SOLDER MASK DEFINED (PREFERRED)

METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL 0.05 MIN ALL AROUND

SOLDER MASK DEFINED
SOLDER MASK DETAILS

4220204/A 02/2017

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SMALL OUTLINE PACKAGE

16X (1.5) 1 16X (0.45) SYMM (R0.05) TYP 16 SYMM 14X (0.65) 8 (5.8)

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

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