SN74CBT16245CDL - Electronic component TEXAS INSTRUMENTS - Free user manual and instructions

USER MANUAL SN74CBT16245CDL TEXAS INSTRUMENTS

●Member of the Texas Instruments Widebus™ Family
●Undershoot Protection for Off-Isolation on A and B Ports Up to -2 V
●Bidirectional Data Flow, With Near-Zero Propagation Delay
●Low ON-State Resistance ( r_on ) Characteristics ( r_on = 3 Typical)
●Low Input/Output Capacitance Minimizes Loading and Signal Distortion ( C_io(OFF) = 5.5 pF Typical)
●Data and Control Inputs Provide Undershoot Clamp Diodes
●Low Power Consumption ( I_CC = 3 A Max )
●V CC Operating Range From 4 V to 5.5 V
●Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
●Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs
●I off Supports Partial-Power-Down Mode Operation
●Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22 - 2000-V Human-Body Model (A114-B, Class II) - 1000-V Charged-Device Model (C101)
●Supports Both Digital and Analog Applications: PCI Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating

DGG, DGV, OR DL PACKAGE (TOP VIEW)

NC	1	48	1OE
1B1	2	47	1A1
1B2	3	46	1A2
GND	4	45	GND
1B3	5	44	1A3
1B4	6	43	1A4
VCC	7	42	VCC
1B5	8	41	1A5
1B6	9	40	1A6
GND	10	39	GND
1B7	11	38	1A7
1B8	12	37	1A8
2B1	13	36	2A1
2B2	14	35	2A2
GND	15	34	GND
2B3	16	33	2A3
2B4	17	32	2A4
VCC	18	31	VCC
2B5	19	30	2A5
2B6	20	29	2A6
GND	21	28	GND
2B7	22	27	2A7
2B8	23	26	2A8
NC	24	25	2OE

NC - No internal connection

description/ordering information

ORDERING INFORMATION

T_A	PACKAGET		ORDERABLEPART NUMBER	TOP-SIDEMARKING
-40°C to 85°C	SSOP - DL	Tube SN74CBT16245CDL		CBT16245C
		Tape and reel SN74CBT16245CDLR
	TSSOP - DGG	Tube SN74CBT16245CDGG		CBT16245C
		Tape and reel SN74CBT16245CDGGR
	TVSOP - DGV Tape and reel SN74CBT16245CDGVR CY245C

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

PRODUCTIONDATAinformationiscurrentasofpublicationdate. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testingofallparameters.

TEXAS

INSTRUMENTS

POST OFFICE BOX 655303 ● DALLAS, TEXAS 75265

Copyright © 2003, Texas Instruments Incorporated

description/ordering information (continued)

The SN74CBT16245C is a high-speed TTL-compatible FET bus switch with low ON-state resistance ( r_on ), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT16245C provides protection for undershoot up to -2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state.

The SN74CBT16245C is organized as two 8-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 8-bit bus switches or as one 16-bit bus switch. When OE is low, the associated 8-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 8-bit bus switch is OFF and the high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using I_off . The I_off feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

FUNCTION TABLE
(each 8-bit bus switch)

INPUTOE	INPUT/OUTPUTA	FUNCTION
L B AH Z D	port = B portsconnect

logic diagram (positive logic)

graph TD
    subgraph Top_Circuit
        A1["1A1"] --> SW1["SW"]
        A8["1A8"] --> SW2["SW"]
        OE["1OE"] --> NOT1["NOT"]
        SW1 --> SW3["SW"]
        SW2 --> SW4["SW"]
        NOT1 --> NOT2["NOT"]
    end
    subgraph Bottom_Circuit
        A1a["2A1"] --> SW5["SW"]
        A8a["2A8"] --> SW6["SW"]
        OEa["2OE"] --> NOT3["NOT"]
        SW5 --> SW7["SW"]
        SW6 --> SW8["SW"]
        NOT3 --> NOT4["NOT"]
    end
    SW1 --> SW4
    SW2 --> SW7
    NOT1 --> NOT3
    SW3 --> SW8
    NOT2 --> SW9["SW"]
    NOT3 --> NOT4
    SW5 --> SW7
    SW6 --> SW8
    NOT4 --> NOT5["NOT"]
    SW7 --> SW9
    NOT5 --> SW10["SW"]
    NOT6["2B1"] --> SW10
    NOT7["2B8"] --> SW10
    style Top_Circuit fill:#f9f,stroke:#333
    style Bottom_Circuit fill:#bbf,stroke:#333

simplified schematic, each FET switch (SW)

A Undershoot Protection Circuit B EN†

EN is the internal enable signal applied to the switch.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡

Supply voltage range, V_CC -0.5 V to 7 V

Control input voltage range, V_IN (see Notes 1 and 2) -0.5 V to 7 V

Switch I/O voltage range, V_I/O (see Notes 1, 2, and 3) -0.5 V to 7 V

Control input clamp current, I_IK ( V_IN < 0 ) -50 mA

I/O port clamp current, I_I/OK ( V_I/O < 0 ) -50 mA

ON-state switch current, I_I/O (see Note 4) ±128 mA

Continuous current through V_CC or GND terminals ± 100 mA

Package thermal impedance, _JA (see Note 5): DGG package 70^ / W

DGV package 58°C/W

DL package 63°C/W

Storage temperature range, T_stg -65°C to 150°C

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltages are with respect to ground unless otherwise specified.

1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. V_I and V_O are used to denote specific conditions for V_I/O .
3. and are used to denote specific conditions for /O .
4. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 6)

		MIN	MAX	UNIT
V_CC	Supply voltage	4	5.5	V
V_IH	High-level control input voltage	2	5.5	V
V_IL	Low-level control input voltage	0	0.8	V
V_I/O	Data input/output voltage	0	5.5	V
T_A	Operating free-air temperature	-40	85	°C

NOTE 6: All unused control inputs of the device must be held at V_CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST		CONDITIONS MIN TYP			MAX	UNIT
V_IK	Control inputs V	CC=4.5 V, I	IN=-18 mA-1.8 V
V_IKU	Data inputs V	CC=5 V,	0 mA > I_I ≥ -50 mA, V_IN = V_CC or GND,	Switch OFF-2 V
I_IN	Control inputs V	CC=5.5 V, V	IN=VCCor GND ±1 μA
I_OZ		VCC=5.5 V,	VO=0 to 5.5 V,VI=0,	Switch OFF, V_IN = V_CC or GND	±10 μA
I_off		VCC=0,	VO=0 to 5.5 V,	VI=0	10 μA
I_CC		VCC=5.5 V,	I_I/O = 0 , V_IN = V_CC or GND,	Switch ON or OFF	3 μA
I_CC	Control inputs V	CC=5.5 V,	One input at 3.4 V,	Other inputs at V_CC or GND	2.5	mA
C_in	Control inputs V	IN=3 V or 0			3.5	pF
C_io(OFF)		V_I/O = 3 V or 0,	Switch OFF,	V_IN = V_CC or GND	5.5	pF
C_io(ON)		V_I/O = 3 V or 0,	Switch ON,	V_IN = V_CC or GND	14	pF
r_on		VCC=4 V,TYP at V_CC = 4 V	V_I = 2.4 V,	b=-15 mA 8 12		Ω
		VCC=4.5 V	V_I = 0	I_O = 64 mA	3 6
				I_O = 30 mA	3 6
			V_I = 2.4 V,	b=-15 mA 5 10

V_IN and I_IN refer to control inputs. V_I, V_O, I_I , and I_O refer to data pins.
All typical values are at V_CC = 5 V (unless otherwise noted), T_A = 25^.
‡For I/O ports, the parameter IOZ includes the input leakage current.
§This is the increase in supply current for each input that is at the specified voltage level, rather than V_CC or GND.
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals.

switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	V_CC = 4 V		V_CC = 5 V ± 0.5 V		UNIT
			MIN	MAX	MIN	MAX
t_pd^\#	A or B	B or A		0.24		0.15	ns
t_en		A or B		5.4	1.5	5	ns
t_dis		A or B		5.6	1.5	5.6	ns

The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).

undershoot characteristics (see Figures 1 and 2)

PARAMETER TEST CONDITIONS MIN TYP			MAX UNIT
V_OUTU	V_CC = 5.5 V, Switch OFF, V	IN = V_CC or GND 2 V	OH^-0.3 V

All typical values are at V_CC = 5 V (unless otherwise noted), T_A = 25^ C .

Input Generator 50 Ω VCC DUT Ax Bx 11 V 100 kΩ 100 kΩ 10 pF VS

Figure 1. Device Test Setup

Figure 2. Transient Input Voltage ( V_I ) and Output Voltage ( V_OUTU ) Waveforms (Switch OFF)

PARAMETER MEASUREMENT INFORMATION

Input Generator VG1 50 Ω VCC VIN 50 Ω DUT TEST CIRCUIT VCC V1 VO RL S1 7 V Open VG2 50 Ω 50 Ω CL (see Note A) RL GND

TEST	V_CC	S1	R_L	V_I	C_L	V_
t_pd(s)	5 V ± 0.5 V4 V	OpenOpen	500 Ω500 Ω	V_CC or GND V_CC or GND	50 pF50 pF
t_PLZ/t_PZL	5 V ± 0.5 V4 V	7 V7 V	500 Ω500 Ω	GNDGND	50 pF50 pF	0.3 V0.3 V
t_PHZ/t_PZH	5 V ± 0.5 V4 V	OpenOpen	500 Ω500 Ω	V_CC V_CC	50 pF50 pF	0.3 V0.3 V

Output Control (VIN) 1.5 V 1.5 V 3 V 0 V tPLH tPHL Output 1.5 V 1.5 V VOH VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (pd(s))

NOTES: A. C L includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O = 50 , t_r ≤ 2.5 ns , t_f ≤ 2.5 ns .

D. The outputs are measured one at a time with one transition per measurement.

E. t_PLZ and t_PHZ are the same as t_dis .

F. tPZL and tPZH are the same as t_en .

G. t_PLH and t_PHL are the same as t_pd(s) . The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).

H. All parameters and waveforms are not applicable to all devices.

Figure 3. Test Circuit and Voltage Waveforms

PACKAGING INFORMATION

Orderable Device Status(1)		Package Type	Package Drawing	Pins	Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4/5)	Samples
SN74CBT16245CDGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBT16245C											Samples
SN74CBT16245CDGVR ACTIVE TVSOP DGV 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CY245C											Samples
SN74CBT16245CDL	ACTIVE	SSOP	DL	48	25	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	CBT16245C	Samples
SN74CBT16245CDLR	ACTIVE	SSOP	DL	48	1000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	CBT16245C	Samples

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "\~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

TEXAS INSTRUMENTS

www.ti.com

PACKAGE OPTION ADDENDUM

10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

A0	Dimension designed to accommodate the component width
B0	Dimension designed to accommodate the component length
K0	Dimension designed to accommodate the component thickness
W	Overall width of the carrier tape
P1	Pitch between successive cavity centers

*All dimensions are nominal

Device Package

Type

Package Drawing

Pins

SPQ Reel

Diameter (mm)

Reel Width W1 (mm)

A0 (mm)

B0 (mm)

K0 (mm)

P1 (mm)

W (mm)

Pin1 Quadrant

SN74CBT16245CDGGR

TSSOP DG

GG 48 2000

330.0

24.4 8.6

13.0 1.8

12.0 24.0 Q1

SN74CBT16245CDGVR

TVSOP DG

V 48 2000

330.0

16.4 7.1

0.2 1.6

12.0 16.0 Q1

SN74CBT16245CDLR S

SOP DL 48

1000 330

0.0 32.4

11.35 16

2 3.1

16.0 32.0 Q1

TAPE AND REEL BOX DIMENSIONS W L

*All dimensions are nominal

Device	Package Type	Package Drawing	Pins	SPQ	Length (mm)	Width (mm)	Height (mm)
SN74CBT16245CDGGR T	SSOP DGG 48 2000	367.0 367.0 45.0
SN74CBT16245CDGVR TV	VSOP DGV 48 2000	853.0 449.0 35.0
SN74CBT16245CDLR S	SOP	DL 48 1000	367.0	367.0 55.0

TUBE

T - Tube height L - Tube length W-Tube width B - Alignment groove width

*All dimensions are nominal

Device	Package Name	Package Type	Pins	SPQ	L (mm)	W (mm)	T (μm)	B (mm)
SN74CBT16245CDL DL	SSOP 48 25 473.7	14.24 5110 7.87

DL (R-PDSO-G48)

PLASTIC SMALL-OUTLINE PACKAGE

0.025 (0,635) 48 0.0135 (0,343) 0.008 (0,203) 0.005 (0,13) 25 0.420 (10,67) 0.395 (10,03) 0.299 (7,59) 0.291 (7,39) 1 24 0.630 (16,00) 0.620 (15,75) 0.010 (0,25) 0.005 (0,13) Gage Plane 0°-8° 0.010 (0,25) 0.040 (1,02) 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.008 (0,20) MIN 0.004 (0,10) 4040048-3/F 05/13

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D. Falls within JEDEC MO-118

PowerPAD is a trademark of Texas Instruments.

DGV (R-PDSO-G\*\*) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

DIM\PINS **	14		20		382416	48	56
A MAX	3,70		5,10	5,103,70	7,90	9,80	11,40
A MIN	3,50	3,50	4,90	4,90	7,70	9,60	11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 per side.
D. Falls within JEDEC: 24/48 Pins - MO-153

14/16/20/56 Pins - MO-194

SMALL OUTLINE PACKAGE

8.3 TYP 7.9 PIN 1 ID AREA 46X 0.5 1 48 2X 11.5 12.6 12.4 NOTE 3 24 25 48X 0.27 0.17 B 6.2 6.0 ⊕ 0.08@ A B

SEATING PLANE 0.1 C 1.2 1.0

SEE DETAIL A (0.15) TYP GA

GAGE PLANE 0° - 8° 0.25 0.75 0.50 0.15 0.05

DETAIL A TYPICAL

4214859/B 11/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.

SMALL OUTLINE PACKAGE

48X (1.5) 1 48X (0.3) 46X (0.5) (R0.05) TYP 24 SYMM 48 SYMM 25 (7.5)

LAND PATTERN EXAMPLE SCALE:6X

SOLDER MASK OPENING METAL 0.05 MAX ALL AROUND

NON SOLDER MASK DEFINED

METAL UNDER SOLDER MASK SOLDER MASK OPENING 0.05 MIN ALL AROUND

SOLDER MASK DEFINED
SOLDER MASK DETAILS

4214859/B 11/2020

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SMALL OUTLINE PACKAGE

48X (1.5) 1 48X (0.3) 46X (0.5) (R0.05) TYP 24 SYMM 48 SYMM 25 (7.5)

SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X

4214859/B 11/2020

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

DGG (R-PDSO-G\*\*) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,50 48 0,27 0,17 ⊕ 0,08 Ⓜ 25 6,20 6,00 8,30 7,90 1 24 A 0,15 NOM Gage Plane 0,25 0°-8° 0,75 0,50 1,20 MAX Seating Plane 0,10 PINS ** DIM 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 4040078/F 12/97

NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

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