SN74LVC07ADR - Electronic component TEXAS INSTRUMENTS - Free user manual and instructions

USER MANUAL SN74LVC07ADR TEXAS INSTRUMENTS

SN74LVC07AHexBufferandDriverWithOpen-DrainOutputs

1Features

• OperatesFrom1.65Vto5V
• InputsandOpen-DrainOutputsAcceptVoltages Upto5.5V
  •Maxt pd of2.6nsat5V
  •Latch-UpPerformanceExceeds250mA PerJESD17
• I_off SupportsLiveInsertion, Partial-Power-Down Mode, and Back-DriveProtection

2Applications

•AVReceiver
•AudioDock:Portable
•Blu-rayPlayerandHomeTheater
•MP3PlayerorRecorder
•PersonalDigitalAssistant(PDA)
•Power:Telecom/ServerAC/DCSupply:Single Controller:AnalogandDigital
•SolidStateDrive(SSD):ClientandEnterprise
•TV:LCD, Digital, and High-Definition(HDTV)
- Tablet: Enterprise
•VideoAnalytics:Server
•WirelessHeadset, Keyboard, and Mouse

3Description

TheSN74LVC07Adeviceisahexbufferanddriver thatisdesignedfor1.65-Vto5.5-VV CC operation.

DeviceInformation (1)

PARTNUMBERPACKAGEBODYSIZE(NOM)
SN74LVC07ADSOIC(14) 8.65mm×3.91mm
SN74LVC07ADB	SSOP(14)	6.20mm×5.30mm
SN74LVC07ADGV	TVSOP(14)	3.60mm×4.40mm
SN74LVC07APW	TSSOP(14)	5.00mm×4.40mm
SN74LVC07ANS	SO(14)	10.30mm×5.30mm
SN74LVC07ARGY	VQFN(14)	3.50mm×3.50mm

(1) For all available packages, see the orderable addendum at theendofthedatasheet.

SimplifiedSchematic

graph LR
    A --> |A| Triangle
    Triangle --> Y

Copyright © 2016 Texas Instruments Incorporated

TableofContents

1 Features.... 1
2 Applications 1
3 Description 1
4 Revision History...... 2

5PinConfigurationandFunctions....4

6 Specifications.... 5

6.1 AbsoluteMaximumRatings....5
6.2ESDRatings....5
6.3RecommendedOperatingConditions....5
6.4ThermalInformation....6
6.5 ElectricalCharacteristics—DCLimitChanges......6
6.6SwitchingCharacteristics....6
6.7OperatingCharacteristics....7
6.8TypicalCharacteristics....7

7ParameterMeasurementInformation......8

7.1V CC = 1.8V±0.15V....8
7.2V CC = 2.5V ± 0.2V....9
7.3V CC =2.7and3.3V±0.3V....10
7.4V CC =5V±0.5V....11

8DetailedDescription....12

8.1Overview....12
8.2FunctionalBlockDiagram....12
8.3FeatureDescription....12
8.4DeviceFunctionalModes....12

9ApplicationandImplementation....13

9.1 Application Information....13
9.2 Typical Application....13

10PowerSupplyRecommendations....14

11 Layout.... 14

11.1 LayoutGuidelines....14
11.2LayoutExample....15

12DeviceandDocumentationSupport....16

12.1 DocumentationSupport....16
12.2ReceivingNotificationofDocumentationUpdates16
12.3CommunityResources....16
12.4Trademarks....16
12.5ElectrostaticDischargeCaution....16
12.6Glossary....16

13Mechanical, Packaging, and Orderable Information 16

4RevisionHistory

NOTE: Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion.

ChangesfromRevisionV(May2015)toRevisionW

Page

• Changed Pin Functions table 4
• Added Junction temperature to the Absolute Maximum Ratings table .... 5
• Reformatted the Electrical Characteristics and the Switching Characteristics tables .... 6
• Changed Typical Application Diagram 13
• Added Receiving Notification of Documentation Updates section 16

ChangesfromRevisionU(June2014)toRevisionV

Page

• Changed Handling Ratings table to ESD Ratings table 5
• Added industry standard terms to package designators in the Thermal Information table 6
• Changed from "High" to "High-Z" in the Function Table 12

ChangesfromRevisionT(February2011)toRevisionU

Page

• Updated document to new TI data sheet format.... 1
• Removed Ordering Information table 1
• Added Applications.... 1
  -Addedl off Features bullet 1
• Added Device Information table .... 1
• Added Handling Ratings table.... 5
• Changed MAX operating free-air temperature from 85°C to 125°C.... 5
• Updated Thermal Information table. 6
• Added -40^ TO +125^ temperature range to Electrical Characteristics table 6
• Added Switching Characteristics table for -40^ TO 125^ temperature range....6

- Added Typical Characteristics....7

5PinConfigurationandFunctions

D,DB,DGV,NS,PWPackage
14-PinSOIC,SSOP,TVSOP,SO,TSSOP TopView

1A 1 14 Vcc 1Y 2 13 6A 2A 3 12 6Y 2Y 4 11 5A 3A 5 10 5Y 3Y 6 9 4A GND 7 8 4Y

RGYPackage

14-PinVQFN
TopView

1A VCC 1Y 2 14 6A 2A 3 13 6Y 2Y 4 12 5A 3A 5 11 5Y 3Y 6 10 4A 7 8 GND 4Y

PinFunctions

PIN		I/ODESCRIPTION
NO.NAME
11AllInput1
21YOOutput1
32AllInput2
42YOOutput2
53AllInput3
63YOOutput3
7GND	—	Groundpin
84YOOutput4
94AllInput4
10	5YOOutput5
11	5AllInput5
12	6YOOutput6
13	6AllInput6
14	V_CC	—	Powerpin

6Specifications

6.1 AbsoluteMaximumRatings

overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1)

			MINMAXUNIT
V_CC	Supplyvoltage-0.56.5V
V_I	Inputvoltage(2)		-0.56.5V
V_O	Outputvoltage-0.56.5V
I_IK	Inputclampcurrent	V_I < 0	-50	mA
I_OK	Outputclampcurrent	V_O < 0	-50	mA
I_O	Continuousoutputcurrent		±50	mA
	Continuouscurrentthrough V_CC orGND		±100	mA
T_j	Junctiontemperature		150	°C
T_stg	Storagetemperature		-65150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)Theinputandoutputnegative-voltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved.

6.2ESDRatings

		VALUE	UNIT
V_(ESD) Electrostaticdischarge	Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001 (1)	±4000	V
	Chargeddevicemodel(CDM),perJEDECspecificationJESD22-C101(2)	±1500

(1)JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.

(2)JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.

6.3 Recommended Operating Conditions

overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1)

		MIN	MAX	UNIT
V_CC Supplyvoltage		1.65	5.5	V
V_IH High-levelinputvoltage	V_CC=1.65Vto1.95V	0.65×V CC		V
	V_CC=2.3Vto2.7V	1.7
	V_CC=2.7Vto3.6V	2
	V_CC=4.5Vto5.5V	0.7×V CC
V_IL Low-levelinputvoltage	V_CC=1.65Vto1.95V	0.35×V CC		V
	V_CC=2.3Vto2.7V	0.7
	V_CC=2.7Vto3.6V	0.8
	V_CC=4.5Vto5.5V	0.3×V CC
V_I Inputvoltage		0	5.5	V
V_O Outputvoltage		0	5.5	V
I_OL Low-leveloutputcurrent	V_CC=1.65V	4		mA
	V_CC=2.3V	12
	V_CC=2.7V	12
	V_CC=3V	24
	V_CC=4.5V	24
T_A Operating free-air temperature		-40	125	°C

(1) AllunusedinputsofthedevicemustbeheldatV CMOSInputs, SCBA004.
cc orGNDtoensureproperdeviceoperation.See Implications of Slowor Floating

6.4ThermalInformation

THERMALMETRIC (1)		SN74LVC07A						UNIT
		D(SOIC)	DB(SSOP)	DGV(TVSOP)	NS(SO)	PW(TSSOP)	RGY(VQFN)
		14PINS
R_ JA	Junction-to-ambientthermalresistance177.413	5.1157.712	0.3160.380.6°C/W
R_ JC(top)	Junction-to-case(top)thermalresistance75.486	778.376.38	4.497.0°C/W
R_ JB	Junction-to-boardthermalresistance	70.682.49	0.879.0102.1	156.7°C/W
_JT	Junction-to-topcharacterizationparameter34.7	43.721.036	224.316.7	°C/W
_JB	Junction-to-boardcharacterizationparameter	70.481.99	0.178.7101.4	456.8°C/W
R_ JC(bot)	Junction-to-case (bottom) thermal resistance	n/a	n/a	n/a	n/a	n/a	35.8	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics—DCLimitChanges

T_A = -40^ to +125^ , unless otherwise noted

PARAMETER	TESTCONDITIONS	VCC	MIN	TYP(1)	MAXUNIT
V_OL	I_OL=100μA	1.65Vto5.5V		0.2	V
	I_OL=4mA	1.65V		0.45
	I_OL=12mA	2.3V		0.7
		2.7V		0.4
	I_OL=24mA	3V		0.55
I_I	V_I=5.5VorGND	3.6V		±5μA
I_off	V_I or V_O=5.5V	0V		±10μA
I_CC	V_I = V_CC orGND, I_O=0	3.6V		10μA
I_CC	Oneinputat V_CC-0.6V, Otherinputsat V_CC orGND	2.7Vto3.6V		500μA
C_i	V_I = V_CC orGND	3.3V	5.0		pF

(1) AlltypicalvaluesareatV
CC=3.3V,T A=25°C.

6.6 Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 through Figure 6)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	TESTCONDITIONS		MIN	MAX	UNIT
t_pd	A	Y	-40°Cto85°C	V_CC=1.8V±0.15V	1	5.6	ns
				V_CC=2.5V±0.2V	1	3.4
				V_CC=2.7V	1	3.3
				V_CC=3.3V±0.3V	1	3.6
				V_CC=5V±0.5V	1	2.6
			-40°Cto125°C	V_CC=1.8V±0.15V	1	6.1
				V_CC=2.5V±0.2V	1	3.9
				V_CC=2.7V	1	3.8
				V_CC=3.3V±0.3V	1	4.1
				V_CC=5V±0.5V	1	3.1

6.7 Operating Characteristics

T_A=25^

PARAMETER		TEST CONDITIONS	V_CC=1.8VV	_CC=2.5VV	_CC=3.3VV	_CC=5V	UNIT
			TYP	TYP	TYP	TYP
C_pd	Powerdissipationcapacitance perbufferanddriver	f = 10 MHz	1.8	2	2.5	3.78	pF

6.8TypicalCharacteristics

Figure1.TPDvsV cc

Figure2.TPDvsTemperature

7ParameterMeasurementInformation

7.1 V_cc = 1.8 V ± 0.15 V

From Output Under Test CL = 30 pF (see Note A) 1 kΩ S1 2 · Vcc Open GND

LOAD CIRCUIT

Timing Input VCC/2 0 V tsu th Data Input VCC/2 VCC/2 0 V VCC

VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

Input VCC/2 VCC/2 0 V tPLH tPHL Output VCC/2 VCC/2 VCC VOL

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

TEST S1
t_PZL (see Note F)	2 · V_CC
t_PLZ (see Note G)	2 · V_CC
t_PHZ/t_PZH	2 · V_CC

Input VCC/2 tw VCC/2 0 V VOLTAGE WAVEFORMS PULSE DURATION

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
NOTES: A. C L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O = 50 , t_r ≤ 2 ns , t_f ≤ 2 ns .
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, t PLZ and tPZL are the same as tpd.
F. t_PZL is measured at V_CC/2 .
G. _PLZ is measured at V_OL + 0.15 V .
H. All parameters and waveforms are not applicable to all devices.

Figure 3. Load Circuit and Voltage Waveforms

7.2V cc = 2.5V ± 0.2V

From Output Under Test C_L = 30 pF (see Note A) 500 Ω 500 Ω S1 2 · V_CC Open GND

LOAD CIRCUIT

Timing Input Vcc/2 0 V tsu th Data Input Vcc/2 Vcc/2 0 V

VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

Input VCC/2 VCC/2 0 V tPLH tPHL Output VCC/2 VCC/2 VCC VOL

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

TEST S1
t_PZL (see Note F)	2 · V_CC
t_PLZ (see Note G)	2 · V_CC
t_PHZ/t_PZH	2 · V_CC

Input VCC/2 tw VCC/2 0 V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
NOTES: A. C L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 Ω, t r ≤ 2 ns, t f ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, t PLZ and tPZL are the same as tpd.
F. tPZL is measured at V_CC/2 .
G. _PLZ is measured at V_OL + 0.15 V .
H. All parameters and waveforms are not applicable to all devices.

Figure 4. Load Circuit and Voltage Waveforms

7.3V cc =2.7and3.3V±0.3V

From Output Under Test C_L = 50 pF (see Note A) 500 Ω 500 Ω S1 6 V Open GND

LOAD CIRCUIT

Timing Input 2.7 V 0 V 1.5 V t_su t_h Data Input 1.5 V 1.5 V 2.7 V 0 V

VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

TEST S1
t_PZL (see Note F)	6 V
t_PLZ (see Note G)	6 V
t_PHZ/t_PZH	6 V

Input tw 2.7 V 1.5 V 1.5 V 0 V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
NOTES: A. C L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 Ω, t f ≤ 2.5 ns, t f ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, t PLZ and t PZL are the same as t pd.
F. tPZL is measured at 1.5 V.
G. t_PLZ is measured at V_OL + 0.3 V .
H. All parameters and waveforms are not applicable to all devices.

Figure 5. Load Circuit and Voltage Waveforms

7.4 V_cc = 5 V ± 0.5 V

From Output Under Test C_L = 50 pF (see Note A) 500 Ω 500 Ω S1 2 x V_CC Open GND

LOAD CIRCUIT

Timing Input Vcc/2 0 V tsu th Data Input Vcc/2 Vcc/2 0 V

VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

Input VCC/2 VCC/2 0 V tPLH tPHL Output VCC/2 VCC/2 VOL

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

TEST	S1
t_PZL (see Note F)	2 × V_CC
t_PLZ (see Note G)	2 × V_CC
t_PHZ/t_PZH	2 × V_CC

Input VCC/2 tw VCC/2 0 V

Output Control (low-level enabling) VCC/2 VCC/2 0 V Output Waveform 1 S1 at 2 x VCC (see Note B) tPZL VCC/2 tPLZ VCC VOL + 0.3 V VOL tPZH VCC/2 tPHZ Output Waveform 2 S1 at 2 x VCC (see Note B) VCC/2 VCC - 0.3 V 0 V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
NOTES: A. C L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal connections such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal connections such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 100MHz, Z = 50 ≤ t22.5ms, t
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and PZL are the same as pd.
F. tPZL is measured at V_CC/2 .
G. t_PLZ is measured at V_OL + 0.3 V .
H. All parameters and waveforms are not applicable to all devices.

Figure 6. Load Circuit and Voltage Waveforms

8DetailedDescription

8.1 Overview

The output of the SN74LVC07A device are open drain and can be connected to other open-drain output to implement active low-wired-OR or active-high-wired-AND functions. The maximum sink current is 24mA.

Inputscanbedrivenfrom1.8-V,2.5-V,3.3-V(LVTTL),or5-V(CMOS)devices.Thisfeatureallowstheuseof thisdeviceastranslatorsinamixed-systemenvironment.

This device is fully specified for partial-power-down applications using l_off . The l_off circuitry disable the outputs, preventing damaging current back flow through the device when it is powered down.

8.2 FunctionalBlockDiagram

A Y

Copyright © 2016 Texas Instruments Incorporated

8.3FeatureDescription

•Wideoperatingvoltagerange

-Operatesfrom1.65Vto5.5V

- Allowsupordownvoltagetranslation

-Inputsandoutputsacceptvoltagesto5.5V

- I_off feature

-AllowsvoltagesontheinputsandoutputswhenV CC is0V

8.4DeviceFunctionalModes

Table1 liststhefunctionalmodesoftheSN74LVC07A.

Table1.FunctionTable

INPUTA	OUTPUTY
H	Hi-Z
L	L

9ApplicationandImplementation

NOTE

InformationinthefollowingapplicationssectionsisnotpartoftheTlcomponent specification,andTldoesnotwarrantitsaccuracyorcompleteness.TI'scustomersare responsiblefordeterminingsuitabilityofcomponentsfortheirpurposes.Customersshould validateandtesttheirdesignimplementationtoconfirmsystemfunctionality.

9.1 Application Information

TheSN74LVC07Adeviceisahigh-drive, open-drainCMOSdevicethatcanbeusedforamultitudeofbuffer-typefunctions.Itcanproduce24mAofdrivecurrentat3.3V. Therefore, this device is idealfordriving multiple inputs and for high-speed applications upto 100MHz. The inputs and outputs are 5.5-Vtolerantallowing the device to translate upto 5.5VordowntoV CC.

9.2 Typical Application

graph LR
    subgraph Buffer Function
        A["LVC07A"] --> B["μC or Logic"]
        C["LVC07A"] --> D["μC or Logic"]
    end
    subgraph Basic LED Driver
        E["LVC07A"] --> F["Diode"]
        G["VPU"] --> H["Diode"]
    end
    I["Basic LED Driver"] --> J["Diode"]
    K["VPU"] --> L["Diode"]
    M["VPU"] --> N["Diode"]
    style A fill:#f9f,stroke:#333
    style C fill:#f9f,stroke:#333
    style E fill:#ccf,stroke:#333
    style G fill:#ccf,stroke:#333
    style I fill:#fff,stroke:#333
    style K fill:#fff,stroke:#333

Copyright © 2016 Texas Instruments Incorporated

Figure7.TypicalApplicationDiagram

9.2.1 DesignRequirements

This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive current that would exceed maximum limits. The high drivewill also create fasted edges into light loads; therefore, routing and load conditions must be considered to prevent ringing.

9.2.2 Detailed Design Procedure

1. RecommendedInputConditions

2. Rise time and fall time specs: See ( t / V) in the Recommended Operating Conditions table.
   -Specifiedhighandlowlevels:See(V IH andV IL )intheRecommendedOperatingConditionstable.
   -Inputsareovervoltage-tolerantallowingthemtogoashighas5.5VatanyvalidV cc-

3. RecommendedOutputConditions

TypicalApplication(continued)

-Loadcurrentsmustnotexceed25mAperoutputand50mAtotalforthepart.
-Outputsmustnotbepulledabove5.5V.

9.2.3 Application Curve

Figure8.1 cc vsFrequency

10PowerSupplyRecommendations

The powersupply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Condition stable.

EachV CC pinmusthaveagoodbypasscapacitortopreventpowerdisturbance. For devices with asinglesupply, 0.1μf is recommended; if there are multiple V CC pins, then 0.01μ for 0.022μ is recommended for each power pin. It is acceptable to parallel multiple bypasscapstoreject different frequencies of noise. A 0.1μ fanda 1μf are commonly used in parallel. The bypasscapacitormust be installed as closeto the powerpin as possible for best results.

11Layout

11.1 LayoutGuidelines

When using multiple bit logic devices inputs must never float.

In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputsofatriple-inputANDgateareusedoronly3ofthe4buffergatesareused.Suchinputpinsmustnotbe left unconnected because the undefined voltages at the outside connections result in undefined operational states. Figure 9 specifies the rules that must be observed under all circumstances. All unused inputs of digital logicdevicesmustbeconnectedtoahighorlowbiastopreventthemfromfloating.Thelogiclevelthatmustbe appliedtoanyparticularunusedinputdependsonthefunctionofthedevice.GenerallytheywillbetiedtoGND or V_CC ,whichevermakesmoresenseorismoreconvenient.Itisgenerallyacceptabletofloatoutputs,unlessthe partisatransceiver.

11.2LayoutExample

Vcc Unused Input Input Output

Input Unused Input Output

Figure9.LayoutDiagram

12DeviceandDocumentationSupport

12.1 DocumentationSupport

12.1.1 Related Documentation

Forrelateddocumentationseethefollowing:

- Implications of Slowor Floating CMOS Inputs, SCBA004.

- SemiconductorandICPackageThermalMetrics,SPRA953.

12.2ReceivingNotificationofDocumentationUpdates

Toreceivenotificationofdocumentationupdates,navigatetothedeviceproductfolderonti.com.Intheupper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "ASIS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contactinformationfortechnicalsupport.

12.4Trademarks

E2EisatrademarkofTexasInstruments.

Allothertrademarksarethepropertyoftheirrespectiveowners.

12.5ElectrostaticDischargeCaution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.

12.6Glossary

SLYZ022—TIGlossary.

This glossarylistsandexplainsterms,acronyms,anddefinitions.

13Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to changewithout notice and revision of this document. For browser-based versions of this datasheet, referto the left-hand navigation.

PACKAGING INFORMATION

Orderable Device Status(1)		Package Type	Package Drawing	Pins	Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4-5)	Samples
SN74LVC07AD ACTIVE SOIC D 14:50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC07A											Samples
SN74LVC07ADBR	ACTIVE	SSOP	DB	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LC07A	Samples
SN74LVC07ADBRG4	ACTIVE	SSOP	DB	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LC07A	Samples
SN74LVC07ADE4	ACTIVE	SOIC	D	14	50	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LVC07A	Samples
SN74LVC07ADGVR	ACTIVE	TVSOP	DGV	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LC07A	Samples
SN74LVC07ADR	ACTIVE	SOIC	D	14	2500	RoHS & Green	NIPDAU | SN	Level-1-260C-UNLIM	-40 to 125	LVC07A	Samples
SN74LVC07ADRG3	ACTIVE	SOIC	D	14	2500	RoHS & Green	SN	Level-1-260C-UNLIM	-40 to 125	LVC07A	Samples
SN74LVC07ADRG4	ACTIVE	SOIC	D	14	2500	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LVC07A	Samples
SN74LVC07ADT	ACTIVE	SOIC	D	14	250	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LVC07A	Samples
SN74LVC07ANSR	ACTIVE	SO	NS	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LVC07A	Samples
SN74LVC07APW	ACTIVE	TSSOP	PW	14	90	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LC07A	Samples
SN74LVC07APWE4	ACTIVE	TSSOP	PW	14	90	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LC07A	Samples
SN74LVC07APWG4	ACTIVE	TSSOP	PW	14	90	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LC07A	Samples
SN74LVC07APWR	ACTIVE	TSSOP	PW	14	2000	RoHS & Green	NIPDAU | SN	Level-1-260C-UNLIM	-40 to 125	LC07A	Samples
SN74LVC07APWRE4	ACTIVE	TSSOP	PW	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LC07A	Samples
SN74LVC07APWRG3	ACTIVE	TSSOP	PW	14	2000	RoHS & Green	SN	Level-1-260C-UNLIM	-40 to 125	LC07A	Samples
SN74LVC07APWRG4	ACTIVE	TSSOP	PW	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LC07A	Samples
SN74LVC07APWT	ACTIVE	TSSOP	PW	14	250	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LC07A	Samples
SN74LVC07APWTG4	ACTIVE	TSSOP	PW	14	250	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LC07A	Samples
SN74LVC07ARGYR	ACTIVE	VQFN	RGY	14	3000	RoHS & Green	NIPDAU	Level-2-260C-1 YEAR	-40 to 125	LC07A	Samples

TEXAS INSTRUMENTS

www.ti.com

PACKAGE OPTION ADDENDUM

10-Dec-2020

Orderable Device Status(1)	Package Type Package Drawing	Pins Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4-5)	Samples
SN74LVC07ARGYRG4 ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LC07A								Samples

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".
RoHS Exempt: Ti defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "\~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC07A :

• Automotive: SN74LVC07A-Q1

TEXAS INSTRUMENTS

www.ti.com

PACKAGE OPTION ADDENDUM

10-Dec-2020

• Enhanced Product: SN74LVC07A-EP

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package	Type	Package Drawing	Pins	SPQ Reel	Diameter (mm)	Reel Width W1 (mm)	A0 (mm)	B0 (mm)	K0 (mm)	P1 (mm)	W (mm)	Pin1 Quadrant
SN74LVC07ADBR SS	DP DB 14	2000 330.0	16.4	8.35 6.6 2	4 12.0 16.0	Q1
SN74LVC07ADGVR TV	SOP DGV	14 2000	330.0	2.4 6.8 4.0	1.6 8.0 1	2.0 Q1
SN74LVC07ADR SOIC	D 14 250	0 330.0	16.4 6.5	9.0 2.1 8.0	16.0 Q1
SN74LVC07ADR SOIC	D 14 250	0 330.0	16.8 6.5	9.5 2.1 8.0	16.0 Q1
SN74LVC07ADR SOIC	D 14 250	0 330.0	16.4 6.5	9.0 2.1 8.0	16.0 Q1
SN74LVC07ADRG3 SOIC	D 14 250	500 330.0	16.8 6	5 9.5 2.1	8.0 16.0 Q1
SN74LVC07ADRG4 SOIC	D 14 250	500 330.0	16.4 6	5 9.0 2.1	8.0 16.0 Q1
SN74LVC07ADRG4 SOIC	D 14 250	500 330.0	16.4 6	5 9.0 2.1	8.0 16.0 Q1
SN74LVCOTADT SOIC	D 14	250 330.0	16.4	6.5 9.0 2.1	8.0 16.0 Q1
SN74LVC07ANSR	SO	NS	14	2000	330.0	16.4	8.2	10.5	2.5	12.0	16.0	Q1
SN74LVC07APWR	TSSOP	PW	14 2000	330.0 12.4	6.9 5.6 1	6 8.0 12.0	Q1
SN74LVC07APWRG3	TSSOP	PW	14	2000	330.0	12.4	6.9	5.6	1.6	8.0	12.0	Q1
SN74LVC07APWRG4	TSSOP	PW	14	2000	330.0	12.4	6.9	5.6	1.6	8.0	12.0	Q1
SN74LVC07APWT TS	SOP PW	14 250	330.0	12.4 6.9 5	6 1.6 8.0	12.0 Q1
SN74LVC07ARGYR VQFN RGY	14 3000	330.0	12	4 3.75 3.75	1.15 8.0	12.0 Q1

TAPE AND REEL BOX DIMENSIONS W L

*All dimensions are nominal

Device	Package Type	Package Drawing	Pins	SPQ	Length (mm)	Width (mm)	Height (mm)
SN74LVC07ADBR SSOP DB 14 2000 853.0	449.0 35.0
SN74LVC07ADGVR TVSOP DGV 14 2000 853.0	449.0 35.0
SN74LVC07ADR SOIC	D	14 2500	340.5 336.1	32.0
SN74LVC07ADR SOIC	D	14 2500	364.0 364.0	27.0
SN74LVC07ADR SOIC	D	14 2500	353.0 449.0	35.0
SN74LVC07ADRG3	SOIC	D	14	2500	364.0	364.0	27.0
SN74LVC07ADRG4	SOIC	D	14	2500	853.0	449.0	35.0
SN74LVC07ADRG4	SOIC	D	14	2500	340.5	336.1	32.0
SN74LVC07ADT	SOIC	D	14	250	210.0	185.0	35.0
SN74LVC07ANSR	SO	NS 14 2000	853.0	449.0 35.0
SN74LVC07APWR	TSSOP	PW	14	2000	853.0	449.0	35.0
SN74LVC07APWRG3	TSSOP	PW	14	2000	364.0	364.0	27.0
SN74LVC07APWRG4	TSSOP	PW	14	2000	853.0	449.0	35.0
SN74LVC07APWT	TSSOP	PW	14	250	853.0	449.0	35.0
SN74LVC07ARGYR	VQFN	RGY 14 3000	853.0	449.0 35.0

TUBE

T - Tube height L - Tube length W - Tube width B - Alignment groove width

*All dimensions are nominal

Device	Package Name	Package Type	Pins	SPQ	L (mm)	W (mm)	T (μm)	B (mm)
SN74LVC07AD D SOIC 14 50 506.6 8 39	40 4.32
SN74LVC07ADE4 D SOIC 14 50 506.6 8 39	40 4.32
SN74LVC07APW PW TSSOP 14 90 530 10.2	3600	3.5
SN74LVC07APWE4	PW	TSSOP	14	90	530	10.2	3600	3.5
SN74LVC07APWG4	PW	TSSOP	14	90	530	10.2	3600	3.5

RGY (S-PVQFN-N14)

PLASTIC QUAD FLATPACK NO-LEAD

3,65 3,35 A 13 9 B 3,65 3,35 Pin 1 Index Area Top and Bottom 1 2 6 F 1,00 0,80 0,20 Nominal Lead Frame Seating Plane 0,08 C 0,05 0,00 C Seating Height 2,00 0,50 14X 0,50 0,30 2 6 1 THERMAL PAD 7 1,50 SIZE AND SHAPE SHOWN ON SEPRATE SHEET 8 14X 0,30 0,18 13 9 ⊕ 0,10 M C A B 0,05 M C

Bottom View

4203539-2/1 06/2011

NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.
C. QFN (Quad Flatpack No-Lead) package configuration.
D. The package thermal pad must be soldered to the board for thermal and mechanical performance.
E. See the additional figure in the Product Data Sheet for details regarding the exposed thermal pad features and dimensions.

Pin 1 identifiers are located on both top and bottom of the package and within the zone indicated.

The Pin 1 identifiers are either a molded, marked, or metal feature.

G. Package complies to JEDEC MO-241 variation BA.

RGY (S-PVQFN-N14)

PLASTIC QUAD FLATPACK NO-LEAD

THERMAL INFORMATION

This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB). After soldering, the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC).

For information on the Quad Flatpack No-Lead (QFN) package and its advantages, refer to Application Report, QFN/SON PCB Attachment, Texas Instruments Literature No. SLUA271. This document is available at www.ti.com.

The exposed thermal pad dimensions for this package are shown in the following illustration.

2 6 Exposed Thermal Pad 1 7 2,05±0,10 14 8 13 9 2,05±0,10

Bottom View

Exposed Thermal Pad Dimensions

4206353-2/P 03/14

NOTE: All linear dimensions are in millimeters

RGY (S-PVQFN-N14)
PLASTIC QUAD FLATPACK NO-LEAD

Example Board Layout 4,30 Note D 4,30 2,60 1,50 2,05 2,05 8x0,50 0,28 Example Stencil Design 0.125mm Stencil Thickness (Note E) 4,25 4,25 2,65 1,50 0,82 50 0,30 0,80 x 14 PL 8x0,50 0,23 x 14 PL. 64% solder coverage by printed area on center thermal pad Non Solder Mask Defined Pad Example Solder Mask Opening (Note F) 0,08 R0,14 0,85 0,28 Example Pad Geometry (Note C) 0,07 All Around Example Via Layout Design may vary depending on constraints (Note D, F) 6xØ0,3 1,00 1,00 4208122-2/P 03/14

NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate designs.
D. This package is designed to be soldered to a thermal pad on the board. Refer to Application Note, Quad Flat-Pack QFN/SON PCB Attachment, Texas Instruments Literature No. SLUA271, and also the Product Data Sheets for specific thermal information, via requirements, and recommended board layout. These documents are available at www.ti.com http://www.ti.com.
E. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC 7525 for stencil design considerations.
F. Customers should contact their board fabrication site for minimum solder mask web tolerances between signal pads.

MECHANICAL DATA

NS (R-PDSO-G\*\*)

PLASTIC SMALL-OUTLINE PACKAGE

14-PINS SHOWN

1,27 14 0,51 0,35 Ø 0,25① 8 5,60 5,00 8,20 7,40 1 7 A

0,15 NOM Gage Plane 0,25 0°-10° 1,05 0,55

2,00 MAX 0,15 0,05

Seating Plane 0.10

DIM\PINS **	14	16	20	24
A MAX	10,50	10,50	12,90	15,30
A MIN	9,90	9,90	12,30	14,70

4040062/C 03/03

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.

DGV (R-PDSO-G\*\*) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

DIM\PINS **	14		20		382416	48	56
A MAX	3,70		5,10	5,103,70	7,90	9,80	11,40
A MIN	3,50	3,50	4,90	4,90	7,70	9,60	11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 per side.
D. Falls within JEDEC: 24/48 Pins - MO-153

14/16/20/56 Pins - MO-194

D (R-PDSO-G14)
PLASTIC SMALL OUTLINE

0.344 (8,75) 0.337 (8,55) 14 8 Pin 1 Index Area 1 0.050 (1,27) 7 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,80) 0.020 (0,51) 0.012 (0,31) ⊕ 0.010 (0,25) M 0.069 (1,75) Max 0.010 (0,25) 0.004 (0,10) Gcuge Plane 0.010 (0,25) 0.005 (0,13) 0°-8° Seating Plane 0.010 (0,25) 0.050 (1,27) 0.016 (0,40) 4040047-5/M 06/11

NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.006 (0,15) each side.
Body width does not include interlead flash. Interlead flash shall not exceed 0.017 (0,43) each side.
E. Reference JEDEC MS-012 variation AB.

D (R-PDSO-G14)

4211283-3/E 08/12
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate designs.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

PW (R-PDSO-G14)

NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0,15 each side.

Body width does not include interlead flash. Interlead flash shall not exceed 0,25 each side.

E. Falls within JEDEC MO-153

PW (R-PDSO-G14)

A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate designs.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

DB (R-PDSO-G\*\*) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,65 28 0,38 0,22 0,15 M 15 5,60 5,00 8,20 7,40 1 14 A

0,25 0,09 Gage Plane 0°-8° 0,25 0,95 0,55

2,00 MAX 0,05 MIN

Seating Plane 0,10

DIM\PINS **	14	16	20	24	28	30	38
A MAX	6,50	6,50	7,50	8,50	10,50	10,50	12,90
A MIN		5,905,906,90			9,907,909,90		12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

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