SN74LV07APWR - Electronic component TEXAS INSTRUMENTS - Free user manual and instructions

USER MANUAL SN74LV07APWR TEXAS INSTRUMENTS

SN74LV07AHexBuffers/DriversWithOpen-DrainOutputs

1Features2Applications

•2-Vto5.5-VV CC Operation

- Servers

•TypicalV OLP (OutputGroundBounce)•TelecomInfrastructures <0.8VatV CC=3.3V,T A=25°C •TVS

•TypicalV OHV (OutputV OH Undershoot)

2.3VatV CC =3.3V,T A =25°C

•TVSet-TopBoxes

- OutputsareDisabledDuringPowerUp andPowerDownWithInputsTiedtoV cc

•SupportMixed-ModeVoltageOperation onAllPorts

- Latch-UpPerformanceExceeds100mA PerJESD78,ClassII

- ESDProtectionExceedsJESD22 - 2000-VHuman-BodyModel - 200-VMachineModel - 1000-VCharged-DeviceModel

3Description

Thesehexbuffers/driversaredesignedfor2-Vto 5.5-VV CC operation.

TheSN74LV07AdeviceperformstheBoolean functionY=Ainpositivelogic.

DeviceInformation (1)

PARTNUMBERPACKAGEBODYSIZE(NOM)
SN74LV07A	TVSOP(14)	3.60mmx4.40mm
	SOIC(14)	8.65mm×3.91mm
	SOP(14)	10.30mmx5.30mm
	SSOP(14)	6.20mmx5.30mm
	TSSOP(14)	5.00mmx4.40mm

(1) For all available packages, see the orderable addendum at the end of the data sheet.

4Simplified Schematic

graph TD
    A1["A"] --> G1["◇"]
    A2["A"] --> G2["◇"]
    A3["A"] --> G3["◇"]
    A4["A"] --> G4["◇"]
    A5["A"] --> G5["◇"]
    A6["A"] --> G6["◇"]
    G1 --> Y1["Y"]
    G2 --> Y2["Y"]
    G3 --> Y3["Y"]
    G4 --> Y4["Y"]
    G5 --> Y5["Y"]
    G6 --> Y6["Y"]

TableofContents

1 Features.... 1

2 Applications 1

3 Description 1

4SimplifiedSchematic....1

5 Revision History...... 2

6PinConfigurationandFunctions....3

7 Specifications....4

7.1 AbsoluteMaximumRatings....4

7.2HandlingRatings....4

7.3RecommendedOperatingConditions....4

7.4ThermalInformation....5

7.5 Electrical Characteristics....5

7.6SwitchingCharacteristics, V CC =2.5V±0.2V......5

7.7SwitchingCharacteristics, V CC =3.3V±0.3V......5

7.8SwitchingCharacteristics, V _CC=5V±0.5V .....6

7.9NoiseCharacteristics....6

7.10OperatingCharacteristics....6

7.11 TypicalCharacteristics....6

8ParameterMeasurementInformation....7

9 Detailed Description 7

9.1Overview....7

9.2FunctionalBlockDiagram....7

9.3FeatureDescription....7

9.4DeviceFunctionalModes....7

10ApplicationandImplementation....8

10.1 Application Information....8

10.2TypicalApplication....8

11PowerSupplyRecommendations....9

12 Layout....9

12.1 LayoutGuidelines....9

12.2LayoutExample....9

13DeviceandDocumentationSupport....10

13.1 RelatedLinks....10

13.2Trademarks....10

13.3ElectrostaticDischargeCaution....10

13.4Glossary....10

14Mechanical, Packaging, and Orderable Information 10

5RevisionHistory

ChangesfromRevisionJ(October2010)toRevisionK

Page

• Updated document to new TI data sheet format. 1
• Deleted Ordering Information table. 1
• Added Handling Ratings table. 4
• Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. 4
• Added Thermal Information table. 5
• Added Typical Characteristics. 6
• Added Detailed Description section....7
• Added Application and Implementation section......8
• Added Power Supply Recommendations and Layout sections....9

6PinConfigurationandFunctions

SN74LV07A...D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

1A 1 14 VCC 1Y 2 13 6A 2A 3 12 6Y 2Y 4 11 5A 3A 5 10 5Y 3Y 6 9 4A GND 7 8 4Y

PinFunctions

PIN		I/ODESCRIPTION
NAMENO.
1A1|1AInput
1Y2O1YOutput
2A3|2AInput
2Y4O2YOutput
3A5|3AInput
3Y6O3YOutput
4A9|4AInput
4Y8O4YOutput
5A	11|5AInput
5Y	10	O5YOutput
6A	13|6AInput
6Y	12	O6YOutput
GND	7	—	GroundPin
V_CC	14	—	PowerPin

7Specifications

7.1 AbsoluteMaximumRatings (1)

overoperatingfree-airtemperaturerange(unlessotherwisenoted)

			MINMAXUNIT
V_CC	Supplyvoltagerange-0.57V
V_I	Inputvoltagerange(2)		-0.57V
V_O	Voltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2)		-0.57V
I_IK	InputclampcurrentV	_1<0-20 mA
I_OK	Outputclampcurrent	V_O<0	-50	mA
I_O	Continuousoutputcurrent	V_O=0toV_CC	-35	mA
	ContinuouscurrentthroughV CC orGND		±50	mA

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

7.2HandlingRatings

			MIN	MAXUNIT
T_stg	Storagetemperaturerange		-65	150	°C
V_(ESD)	Electrostaticdischarge	Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,all pins ^(1)	0	2000	V
		Chargeddevicemodel(CDM),perJEDECspecification JESD22-C101,allpins ^(2)	0	1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1)

			MIN	MAX	UNIT
V_CC	Supplyvoltage		2	5.5	V
V_IH	Highlevelinputvoltage	V_CC=2V	1.5		V
		V_CC=2.3Vto2.7V	V_CC×0.7
		V_CC=3Vto3.6V	V_CC×0.7
		V_CC=4.5Vto5.5V	V_CC×0.7
V_IL	Lowlevelinputvoltage	V_CC=2V	0.5		V
		V_CC=2.3Vto2.7V	V_CC×0.3
		V_CC=3Vto3.6V	V_CC×0.3
		V_CC=4.5Vto5.5V	V_CC×0.3
V_I	Inputvoltage		0	5.5	V
V_O	Outputvoltage		0	5.5	V
I_OL	Lowleveloutputcurrent	V_CC=2V	50		μA
		V_CC=2.3Vto2.7V	2		mA
		V_CC=3Vto3.6V	8
		V_CC=4.5Vto5.5V	16
t/ v	Input transition rise and fall rate	V_CC=2.3Vto2.7V	200
		V_CC=3Vto3.6V	100ns/V
		V_CC=4.5Vto5.5V	20
T_A	Operating free-air temperature		-40	125	°C

(1) AllunusedinputsofthedevicemustbeheldatV CC or GNDtoensureproperdeviceoperation. RefertotheTlapplicationreport, ImplicationsofSloworFloatingCMOSInputs(SCBA004).

7.4ThermalInformation

THERMALMETRIC (1)		SN74LV07A
		DDBDGVNSPWUNIT
		14PINS14	PINS14PINS1	4PINS14PINS
R_ JA	Junction-to-ambient thermal resistance	100.6	112.5	135.2	95.4	128.7	°C/W
R_ JC(top)	Junction-to-case (top) thermal resistance	51.8	65.0	57.9	52.9	57.2
R_ JB	Junction-to-board thermal resistance	54.9	59.9	68.3	51.2	70.7
_JT	Junction-to-top characterization parameter	25.0	25.0	9.2	17.9	9.3
_JB	Junction-to-board characterization parameter	54.7	59.3	67.6	53.8	70.0

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER	TESTCONDITIONS	V_CC	SN74LV07A			-40°C to 125°C SN74LV07A			UNIT
			MIN	TYP	MAX	MIN	TYP	MAX
V_OL	I_OL=50μA	2V to 5.5V			0.1			0.1	V
	I_OL=2mA	2.3V			0.4			0.4
	I_OL=8mA	3V			0.44			0.44
	I_OL=16mA	4.5V			0.55			0.55
I	V_I=5.5 V or GND	0 to 5.5 V			±1			±1	μA
I_OH	V_I=V_IH, V_OH=V_CC	5.5V			±2.5			±2.5	μA
I_CC	V_I=V_CC or GND, I_O=0	5.5 V			20			20	μA
I_off	V_I or V_O=0 to 5.5 V	0			5			5	μA
C_i	V_I=V_CC or GND	3.3 V		1.6			1.6		pF

7.6SwitchingCharacteristics,V _cc=2.5V±0.2V

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)

PARAMETER	FROMTO(INPUT)	(OUTPUT)	LOADCAPACITANCE	T_A=25°C			SN74LV07A		-40°C to 125°CSN74LV07A		UNIT
				MIN	TYP	MAX	MIN	MAX	MIN	MAX
t_PLH	A	Y	C_L=15pF		6.6(1)	10.4(1)	1	13	114		ns
t_PHL	A	Y			7.5(1)	10.4(1)	1	13	114
t_PLH	A	Y	C_L=50pF		11.1	15.2	1	18	1	19	ns
t_PHL	A	Y			9.6	15.2	1	18	1	19

(1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested.

7.7SwitchingCharacteristics,V cc=3.3V±0.3V

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	LOADCAPACITANCE	T_A =25°C			SN74LV07A		-40°Cto125°CSN74LV07A		UNIT
				MIN	TYP	MAX	MIN	MAX	MIN	MAX
t_PLH	A	Y	C_L =15pF		5(1)	7.1(1)	18.5		19.5		ns
t_PHL	A	Y			5(1)	7.1(1)	18.5		19.5
t_PLH	A	Y	C_L =50pF		8.2	10.6	1	12	1	13	ns
t_PHL	A	Y			6.6	10.6	1	12	1	13

(1) OnproductscomplianttoMIL-PRF-38535, this parameter is not produced tested.

7.8SwitchingCharacteristics,V cc =5V±0.5V

operatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3)

PARAMETER	FROMTOLOAD(INPUT)	(OUTPUT)	CAPACITANCE	T_A =25°C SN74LV07A			-40°C to 125°C SN74LV07A			UNIT
				MIN	TYP	MAX	MIN	MAX	MIN	MAX
t_PLH	A	Y	C_L =15pF		3.8	5.5(1)	1	6.5	1	7.2
t_PHL	A	Y			3.4(1)	5.5(1)	1	6.5	1	7.2
t_PLH	A	Y	C_L =50pF		5.7	7.5	1	8.5	1	9.2
t_PHL	A	Y			4.5	7.5	1	8.5	1	9.2

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.

7.9NoiseCharacteristics (1)

V_CC=3.3V,C _L=50pF,T _A=25^

PARAMETER		MIN	TYP	MAX	UNIT
V_OL(P)	Quiet output, maximum dynamic V_OL		0.4	0.8	V
V_OL(V)	Quiet output, minimum dynamic VOL		-0.1	-0.8	V
V_OH(V)	Quiet output, minimum dynamic V_OH		3.2		V
V_IH(D)	High-level dynamic input voltage	2.31			V
V_IL(D)	Low-level dynamic input voltage			0.99	V

(1) Characteristics are for surface-mount packages only.

7.10 Operating Characteristics

T_A=25^

PARAMETER		TEST CONDITIONS	V_cc	TYP	UNIT
C_pd	Power dissipation capacitance	C_L = 50 pF, f = 10 MHz	3.3 V	2.9	pF
			5 V	5.3

7.11 Typical Characteristics

Figure 1. TPD vs V_cc

Figure 2. TPD vs Temperature at 3.3 V

8ParameterMeasurementInformation

VCC RL = 1 kΩ From Output Under Test Test Point CL (see Note A)

LOAD CIRCUIT FOR OPEN-DRAIN OUTPUTS

Input 50% VCC 50% VCC 0 V tPHL tPLH Output 50% VCC =VCC VOL + 0.3 V VOL

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

A. C_L includesprobeandjigcapacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z_O = 50 , t_r ≤ 3ns , t_f ≤ 3ns .
C. The outputs are measured one at a time, with one input transition per measurement.

Figure3.LoadCircuitandVoltageWaveforms

9DetailedDescription

9.1 Overview

The output of the SN74LV07A device are open and can be connected to other open-drain output to implement active low-wired-OR active-high-wired-AND functions. The maximum sink current is 16 mA at 5-VV CC. Input scan bed driven from 2.5-V, 3.3-V, or 5-V (CMOS) devices. This feature allows the use of the SN74LV07A device as a translator in an mixed-system environment. This device is fully specified for partial power-down applications using I off. The I off circuitry disable the outputs, thus preventing adamaging current backflow through the device when it is powered down.

9.2 FunctionalBlock Diagram

Figure4.LogicDiagram, EachBuffer/Driver(PositiveLogic)

9.3FeatureDescription

• Wideoperatingvoltagerange
- Operatesfrom2Vto5.5 V
- Allowsupordownvoltagetranslation
- Inputsandoutputsacceptvoltagesto 5.5V
- I_off feature
- Allows voltages on the inputs and outputs when V CC is 0V

9.4DeviceFunctional Modes

Table1.FunctionTable (EachBuffer/Driver)

INPUTA	OUTPUTY
H	H
L	L

10ApplicationandImplementation

NOTE

InformationinthefollowingapplicationssectionsisnotpartoftheTlcomponent specification,andTldoesnotwarrantitsaccuracyorcompleteness.TI'scustomersare responsiblefordeterminingsuitabilityofcomponentsfortheirpurposes.Customersshould validateandtesttheirdesignimplementationtoconfirmsystemfunctionality.

10.1 Application Information

TheSN74LV07Adeviceisalowdrive,open-drainCMOSdevicethatcanbeusedforamultitudeofbuffertype functions. Theinputsare5.5-Vtolerant. Theoutputsareopendrainand5.5-Vtolerant;thus,allowingthedevice totranslateupto5.5VordowntoanyothervoltagebetweenGNDand5.5V.

10.2 Typical Application

Buffer Function

VPU uC or Logic LV07A Wired OR uC or Logic uC or Logic LV07A

Basic LED Driver

uC or Logic LV07A VPU

Figure5.TypicalApplicationSchematic

10.2.1 Design Requirements

This device uses CMOS technology and isopendrain, soithaslow output drive only. Careshould betakento avoid bus contention, because it can drive current that would exceed maximum limits. Parallel output drive can create fasted edges into light loads, sorouting and load condition should be considered to prevent ringing.

10.2.2 Detailed Design Procedure

1. Recommended Input Conditions:

2. For rise time and fall time specifications, see t / V in the Recommended Operating Conditions table.
   -Forspecifiedhighandlowlevels,seeV IH andV IL intheRecommendedOperatingConditionstable.
   -Inputsareovervoltagetolerantallowingthemtogoashighas5.5VatanyvalidV cc-

3. RecommendedOutputConditions:

-Loadcurrentsshouldnotexceed35mAperoutputand50mAtotalforthepart.

TypicalApplication(continued)

10.2.3 ApplicationCurves

Figure 6. Output During Power Up with 4 k Pullup at 3.3 V

11 Power Supply Recommendations

The powersupply can be any voltage between the MIN and MAX supply voltage, operating in the Recommended Operating Conditions. Each V CC terminal should have a good bypass capacitance to prevent power disturbance. For devices with asinglesupply, 0.1 μF is recommended. If there are multiple V CC terminal then 0.01 μF or 0.022 μF is recommended for each power terminal. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results.

12 Layout

12.1 LayoutGuidelines

When using multiple bit logic devices, input should not float. In many cases, functions or part so function so digital logic devices are unused. Some examples are when only two input so at triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states.

Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low biastoprevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or V_CC , whichever makes moresense or is more convenient. It is acceptable to float outputs unless the partisa transceiver.

12.2 LayoutExample

Vcc Unused Input Input Output

Input Unused Input Output

Figure7.LayoutDiagram

13DeviceandDocumentationSupport

13.1 RelatedLinks

Thetablebelowlistsquickaccesslinks. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.

Table2.RelatedLinks

PARTSPRODU	CTFOLDERSAMPLE&	BUY	TECHNICALTOOLS&SUPPORT& DOCUMENTSSOFTWARE	COMMUNITY
SN74LV07A	Click here	Click here	Click here	Click here

13.2 Trademarks

Alltrademarksarethepropertyoftheirrespectiveowners.

13.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

13.4 Glossary

SLYZ022 — TIGlossary.

This glossarylistsandexplainsterms,acronyms,anddefinitions.

14Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this datasheet, refertotheleft-handnavigation.

PACKAGING INFORMATION

Orderable Device Status	(1)	Package Type	Package Drawing	Pins	Package Qty	Eco Plan (2)	Lead finish/ Ball material (6)	MSL Peak Temp (3)	Op Temp (°C)	Device Marking (4,5)	Samples
SN74LV07AD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV07A											Samples
SN74LV07ADBR	ACTIVE	SSOP	DB	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV07A	Samples
SN74LV07ADG4	ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV07A										Samples
SN74LV07ADGVR	ACTIVE	TVSOP	DGV	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV07A	Samples
SN74LV07ADR	ACTIVE	SOIC	D	14	2500	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV07A	Samples
SN74LV07ADRG4	ACTIVE	SOIC	D	14	2500	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV07A	Samples
SN74LV07ANS	ACTIVE	SO	NS	14	50	RoHS & Green	NIPDAU	Level-1-260C-UNLIM		74LV07A	Samples
SN74LV07ANSR	ACTIVE	SO	NS	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	74LV07A	Samples
SN74LV07APW	ACTIVE	TSSOP	PW	14	90	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV07A	Samples
SN74LV07APWG4	ACTIVE	TSSOP	PW	14	90	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV07A	Samples
SN74LV07APWR	ACTIVE	TSSOP	PW	14	2000	RoHS & Green	NIPDAU | SN	Level-1-260C-UNLIM	-40 to 125	LV07A	Samples
SN74LV07APWRG3	ACTIVE	TSSOP	PW	14	2000	RoHS & Green	SN	Level-1-260C-UNLIM	-40 to 125	LV07A	Samples
SN74LV07APWRG4	ACTIVE	TSSOP	PW	14	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV07A	Samples
SN74LV07APWT	ACTIVE	TSSOP	PW	14	250	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV07A	Samples
SN74LV07APWTG4	ACTIVE	TSSOP	PW	14	250	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 125	LV07A	Samples

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "\~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package	Type	Package Drawing	Pins	SPQ Reel	Diameter (mm)	Reel Width W1 (mm)	A0 (mm)	B0 (mm)	K0 (mm)	P1 (mm)	W (mm)	Pin1 Quadrant
SN74LV07ADBR SSOP DB 14	2000 330.0	16.4	8.35	6.6 2.4	12.0	16.0	Q1
SN74LV07ADGVR TV$	SOP DGV	14 2000 33	0.0	12.4	6.8	4.0	1.6	8.0	12	0 Q1
SN74LV07ADR SOIC	D 14 250	330.0	16	4 6.5	9.0	2.1	8.0	16.0	Q1
SN74LV07ANSR	SO	NS 14	2000	330.0	16.4	8.2	10.5	2	5	12.0	16	0 Q1
SN74LV07APWR	TSSOP	PW	14	2000	330.0	12.4	6.9	5.6	1	6	8.0	12.0
SN74LV07APWR	TSSOP	PW	14	2000	330.0	12.4	6.9	5.6	1	6	8.0	12.0
SN74LV07APWRG3 TS	SOP	PW	14	2000	330.0	12.4	6.9	5.6	1	6	8.0	12.0
SN74LV07APWRG4 TS	SOP	PW	14	2000	330.0	12.4	6.9	5.6	1	6	8.0	12.0
SN74LV07APWT	TSSOP	PW	14	250	330.0	12.4	6.9	5.6	1	6	8.0	12.0

TAPE AND REEL BOX DIMENSIONS W L

*All dimensions are nominal

Device	Package Type	Package Drawing	Pins	SPQ	Length (mm)	Width (mm)	Height (mm)
SN74LV07ADBR SSOP DB 14 2000 853.0	449.0 35.0
SN74LV07ADGVR TVSOP DGV 14 2000 853.0	449.0 35.0
SN74LV07ADR SOIC	D	14 2500 853.0	449.0	35.0
SN74LV07ANSR SO	NS 14 2000 853.0	449.0	35.0
SN74LV07APWR	TSSOP	PW	14	2000	853.0	449.0	35.0
SN74LV07APWR	TSSOP	PW	14	2000	364.0	364.0	27.0
SN74LV07APWRG3	TSSOP	PW	14	2000	364.0	364.0	27.0
SN74LV07APWRG4	TSSOP	PW	14	2000	853.0	449.0	35.0
SN74LV07APWT	TSSOP	PW	14	250	853.0	449.0	35.0

TUBE

T - Tube height L - Tube length W-Tube width B - Alignment groove width

*All dimensions are nominal

Device	Package Name	Package Type	Pins	SPQ	L (mm)	W (mm)	T (μm)	B (mm)
SN74LV07AD D SOIC	14 50 506.6 8 3940	4.32
SN74LV07ADG4 D SOIC	14 50 506.6 8 3940	4.32
SN74LV07ANS NS SOP	14 50 530	10.5 4000	4.1
SN74LV07APW	PW	TSSOP	14	90	530	10.2	3600	3.5
SN74LV07APWG4	PW	TSSOP	14	90	530	10.2	3600	3.5

DGV (R-PDSO-G\*\*) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

DIM\PINS **	14		20		382416	48	56
A MAX	3,70		5,10	5,103,70	7,90	9,80	11,40
A MIN	3,50	3,50	4,90	4,90	7,70	9,60	11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 per side.
D. Falls within JEDEC: 24/48 Pins - MO-153

14/16/20/56 Pins - MO-194

D (R-PDSO-G14)
PLASTIC SMALL OUTLINE

0.344 (8,75) 0.337 (8,55) 14 8 Pin 1 Index Area 1 0.050 (1,27) 7 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,80) 0.020 (0,51) 0.012 (0,31) ⊕ 0.010 (0,25) M 0.069 (1,75) Max 0.010 (0,25) 0.004 (0,10) Gcuge Plane 0.010 (0,25) 0.005 (0,13) 0°-8° Seating Plane 0.010 (0,25) 0.050 (1,27) 0.016 (0,40) 4040047-5/M 06/11

NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.006 (0,15) each side.
Body width does not include interlead flash. Interlead flash shall not exceed 0.017 (0,43) each side.
E. Reference JEDEC MS-012 variation AB.

D (R-PDSO-G14)

4211283-3/E 08/12
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate designs.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

PW (R-PDSO-G14)

NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 each side.

Body width does not include interlead flash. Interlead flash shall not exceed 0,25 each side.

E. Falls within JEDEC MO-153

PW (R-PDSO-G14)

A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate designs.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

DB (R-PDSO-G\*\*) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,65 28 0,38 0,22 0,15 M 15 5,60 5,00 8,20 7,40 1 14 A

0,25 0,09 Gage Plane 0°-8° 0,25 0,95 0,55

2,00 MAX 0,05 MIN

Seating Plane 0,10

DIM\PINS **	14	16	20	24	28	30	38
A MAX	6,50	6,50	7,50	8,50	10,50	10,50	12,90
A MIN		5,905,906,90			9,907,909,90		12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

MECHANICAL DATA

NS (R-PDSO-G\*\*)

PLASTIC SMALL-OUTLINE PACKAGE

14-PINS SHOWN

1,27 14 0,51 0,35 Ø 0,25① 8 5,60 5,00 8,20 7,40 1 7 A

0,15 NOM Gage Plane 0,25 0°-10° 1,05 0,55

2,00 MAX 0,15 0,05

Seating Plane 0.10

DIM\PINS **	14	16	20	24
A MAX	10,50	10,50	12,90	15,30
A MIN	9,90	9,90	12,30	14,70

4040062/C 03/03

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.

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