LP339N - Electronic component TEXAS INSTRUMENTS - Free user manual and instructions

Product Type	Quad Differential Comparator
Model	LP339N
Brand	Texas Instruments
Package	14-pin DIP (Plastic Dual-In-Line)
Dimensions	19.3 mm x 6.35 mm x 4.57 mm
Weight	Approx. 1.0 g
Supply Voltage Range	2 V to 36 V (single supply) or ±1 V to ±18 V (dual supply)
Supply Current (per comparator)	Typ. 60 µA (total for all four)
Output Type	Open-collector (requires pull-up resistor)
Input Offset Voltage	Typ. 2 mV
Input Bias Current	Typ. 25 nA
Response Time	Typ. 1.3 µs (for 5 mV overdrive)
Operating Temperature	0°C to +70°C
Storage Temperature	-65°C to +150°C
Hysteresis	Not built-in; can be added externally (positive feedback)
Number of Comparators	4
Power Consumption	Very low (ideal for battery-powered devices)
Common Mode Input Voltage Range	0 V to Vcc - 1.5 V
ESD Protection	Human body model: 2 kV
RoHS Compliant	Yes
Application	Voltage comparison, level detection, battery monitoring, signal conditioning
Handling Precautions	ESD sensitive; store in anti-static bag; avoid mechanical stress
Cleaning	Use isopropyl alcohol; avoid abrasive cleaners

Frequently Asked Questions - LP339N TEXAS INSTRUMENTS

What is the LP339N and what does it do?

The LP339N is a low-power quad comparator manufactured by Texas Instruments. It compares two analog voltages and outputs a digital signal (open-collector) indicating which is higher. It is ideal for battery-operated devices due to its very low supply current.

What is the supply voltage range for the LP339N?

The LP339N can operate from a single supply of 2 V to 36 V or from dual supplies of ±1 V to ±18 V.

Do I need an external pull-up resistor on the outputs?

Yes, the LP339N has open-collector outputs. To obtain a high logic level, a pull-up resistor must be connected from the output to a positive voltage (typically to Vcc or a logic supply).

How can I add hysteresis to prevent oscillation?

Hysteresis is not built-in. Add positive feedback by connecting a resistor from the output to the non-inverting input. This creates a voltage gap between the switching thresholds, preventing rapid toggling when the input signal is noisy.

What is the typical response time?

The typical response time is 1.3 µs with a 5 mV overdrive. For faster or slower requirements, consider different comparator families.

Can I use the LP339N in single-supply applications?

Yes, it works well with a single supply from 2 V to 36 V. The common-mode input voltage ranges from 0 V to Vcc - 1.5 V.

What is the maximum output current?

The open-collector output can sink up to 6 mA (typical) when low. For higher current, use an external transistor.

How should I handle the LP339N to avoid damage?

The device is ESD sensitive. Use anti-static wrist straps and mats. Store in conductive foam or anti-static bags. Avoid mechanical stress on leads.

What are typical applications for the LP339N?

Common uses include battery voltage monitoring, level detectors, window comparators, zero-crossing detectors, and signal conditioning for sensors.

Can I replace an LM339 with the LP339N?

Yes, the LP339N is a low-power version of the LM339. It has lower supply current (60 µA total vs. 2 mA) but slightly slower response. Check your circuit requirements before substitution.

USER MANUAL LP339N TEXAS INSTRUMENTS

● Wide Supply-Voltage Range ... 3 V to 30 V
●Ultralow Power Supply Current Drain ... 60 μA Typ
● Low Input Biasing Current ... 3 nA
● Low Input Offset Current . . . ±0.5 nA
● Low Input Offset Voltage ... ±2 mV
●Common-Mode Input Voltage Includes Ground
●Output Voltage Compatible With MOS and CMOS Logic
●High Output Sink-Current Capability (30 mA at V_O = 2V )
●Power Supply Input Reverse-Voltage Protected
●Single-Power-Supply Operation
●Pin-for-Pin Compatible With LM239, LM339, LM2901

D OR N PACKAGE (TOP VIEW)

1OUT 1 14 3OUT 2OUT 2 13 4OUT VCC 3 12 GND 2IN - 4 11 4IN + 2IN + 5 10 4IN - 1IN - 6 9 3IN + 1IN + 7 8 3IN -

description/ordering information

The LP239, LP339, LP2901 are low-power quadruple differential comparators. Each device consists of four independent voltage comparators designed specifically to operate from a single power supply and typically to draw 60- A drain current over a wide range of voltages. Operation from split power supplies also is possible and the ultra-low power-supply drain current is independent of the power-supply voltage.

Applications include limit comparators, simple analog-to-digital converters, pulse generators, squarewave generators, time-delay generators, voltage-controlled oscillators, multivibrators, and high-voltage logic gates. The LP239, LP339, LP2901 were designed specifically to interface with the CMOS logic family. The ultra-low power-supply current makes these products desirable in battery-powered applications.

The LP239 is characterized for operation from -25^ to 85^ . The LP339 is characterized for operation from 0^ to 70^ . The LP2901 is characterized for operation from -40^ to 85^ .

ORDERING INFORMATION

TA	VIOMAX AT 25°C	PACKAGET		ORDERABLE PART NUMBER	TOP-SIDE MARKING
0°C to 70°C	±5 mV	PDIP (N) Tube of 25 LP339N LP339N
		SOIC (D)	Tube of 50 LP339D		LP339
			Reel of 2500 LP339DR
-40°C to 85°C	±5 mV	PDIP (N) Tube of 25 LP2901N LP2901N
		SOIC (D)	Tube of 50 LP2901D		LP2901
			Reel of 2500 LP2901DR

^ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

schematic diagram (each comparator)

VCC 0.2 µA 5 µA 0.2 µA 6 µA IN+ OUT IN- GND

absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ^†

Supply voltage, V_CC (see Note 1) 36 V

Differential input voltage, V_ID (see Note 2) ±36 V

Input voltage range, V_I (either input) -0.3 V to 36 V

Input current, V_I ≤ -0.3 V (see Note 3) -50 mA

Duration of output short-circuit to ground (see Note 4) .... Unlimited

Continuous total dissipation (see Note 5) ..... See Dissipation Rating Table

Operating free-air temperature range, T_A : LP239 -25^ to 85^

LP339 0°C to 70°C

LP2901 -40°C to 85°C

Package thermal impedance, _JA (see Notes 6 and 7): D package 86°C/W

N package 80°C/W

Operating virtual junction temperature, T_J 150°C

Lead temperature range 1,6 mm (1/16 inch) from case for 60 seconds: J package ..... 300°C

Storage temperature range, T_stg -65^ to 150^

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential voltages, are with respect to the network ground.

1. Differential voltages are at IN+ with respect to IN - .
2. This input current only exists when the voltage at any of the inputs is driven negative. The current flows through the collector-base junction of the input clamping device. In addition to the clamping device action, there is lateral n-p-n parasitic transistor action. This action is not destructive, and normal output states are reestablished when the input voltage returns to a value more positive than -0.3 V at T_A = 25^ .
3. Short circuits between outputs to V_CC can cause excessive heating and eventual destruction.
4. If the output transistors are allowed to saturate, the low-bias dissipation and the on-off characteristics of the outputs keep the dissipation very small (usually less than 100 mW).
5. Maximum power dissipation is a function of T_J() , _JA , and T_A . The maximum allowable power dissipation at any allowable ambient temperature is P_D = (T_J() - T_A) / _JA . Operating at the absolute maximum T_J of 150^ can impact reliability.
6. The package thermal impedance is calculated in accordance with JESD 51-7.

DISSIPATION RATING TABLE

PACKAGE	T_A ≤ 25°C POWER RATING	DERATING FACTORABOVE T_A = 25°C	T_A = 70°C POWER RATING	T_A = 85°C POWER RATING
J	1025 mW	8.2 mW/°C	656 mW	533 mW

recommended operating conditions

		LP239 LP339 LP2901			UNIT
		MIN MAX MIN	MAX MIN MAX
V_CC Supply voltage 3 30 3 30 3 30 V
V_IC Common-mode input voltage	V_CC = 5 V 0 3	0 3 0 3 V
	V_CC = 30 V	0 28 0 28 0	28 V
V_I Input voltage	V_CC = 5 V 0 3	0 3 0 3 V
	V_CC = 30 V	0 28 0 28 0	28 V
T_A Operating free-air temperature		-25 85	0 70	-40 85	°C

electrical characteristics, V_CC = 5 V, T_A = 25^ (unless otherwise noted)

PARAMETER		TEST CONDITIONS		T_A^	MIN TYP MAX UNT
V_IO	Input offset voltage	V_CC=5 V to 30 V, V_O=2 V, RS=0, See Note 6		25°C	±2 ±5
				Full range	±9
I_IO	Input offset current			25°C	±0.5 ±5
				Full range	±1 ±15
I_IB	Input bias current	See Note 7		25°C	-2.5 -25
				Full range	-4 -40
V_ICR	Common-mode input voltage range	Single supply		25°C	0 to V_CC-1.5
				Full range	0 to V_CC-2
A_VD	Large-signal differential voltage amplification	V_CC=15 V, RL=15 k			500
Output sink current		V_I-=1 V, V_I+=0	V_O=2 V, See Note 8	25°C	20 30
				Full range	15
			V_O=0.4 V	25°C	0.2 0.7
Output leakage current		V_I+=1 V, V_I-=0	V_O=5 V	25°C	0.1
			V_O=30 V	Full range	1
V_ID	Differential input voltage	V_I≤0 (or V_CC-on split supplies)			36
I_CC	Supply current	R_L= all comparators			60 100

Full range is -25^ to 85^ for the LP239, 0^ to 70^ for the LP339, and -40^ to 85^ for the LP2901.
NOTES: 8. V_IO is measured over the full common-mode input voltage range.
9. Because of the p-n-p input stage, the direction of the current is out of the device. This current essentially is constant (i.e., independent of the output state). No loading change exists on the reference or input lines as long as the common-mode input voltage range is not exceeded.
10. The output sink current is a function of the output voltage. These devices have a bimodal output section that allows them to sink (via a Darlington connection) large currents at output voltages greater than 1.5 V, and smaller currents at output voltages less than 1.5 V.

switching characteristics, V_CC = 5 ~V , T_A = 25^ C , R_L connected to 5 ~V through 5.1 k

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Large-signal response time	TTL logic swing, V_ref = 1.4 V		1.3		‘μs
Response time			8

APPLICATION INFORMATION

Figure 1 shows the basic configuration for using the LP239, LP339, or LP2901 comparator. Figure 2 shows the diagram for using one of these comparators as a CMOS driver.

IN + IN - + - VCC 30 kΩ OUT 1/4 LP239, LP339, or LP2901

Figure 1. Basic Comparator

IN + IN - 1/4 LP239, LP339, or LP2901 3 12 100 kΩ VCC OUT 1/4 SN54/74LS00 or 1/4 SN54/74ALS1000A

Figure 2. CMOS Driver

All pins of any unused comparators should be grounded. The bias network of the LP239, LP339, and LP2901 establishes a drain current that is independent of the magnitude of the power-supply voltage over the range of 2 V to 30 V. It usually is necessary to use a bypass capacitor across the power supply line.

The differential input voltage may be larger than V_CC without damaging the device. Protection should be provided to prevent the input voltages from going negative by more than -0.3 V. The output section has two distinct modes of operation: a Darlington mode and ground-emitter mode. This unique drive circuit permits the device to sink 30 mA at V_O = 2 V in the Darlington mode and 700 A at V_O = 0.4 V in the ground-emitter mode. Figure 3 is a simplified schematic diagram of the output section. The output section is configured in a Darlington connection (ignoring Q3). If the output voltage is held high enough (above 1 V), Q1 is not saturated and the output current is limited only by the product of the h_FE of Q1, the h_FE of Q2, and I1 and the 60- saturation resistance of Q2. The devices are capable of driving LEDs, relays, etc. in this mode while maintaining an ultra-low power-supply current of 60 A, typically.

I1 = 6 μA VCC Q3 Q1 VO Q2

Figure 3. Output-Section Schematic Diagram

APPLICATION INFORMATION

Without transistor Q3, if the output voltage were allowed to drop below 0.8 V, transistor Q1 would saturate, and the output current would drop to zero. The circuit would be unable to pull low current loads down to ground or the negative supply, if used. Transistor Q3 has been included to bypass transistor Q1 under these conditions and apply the current I1 directly to the base of Q2. The output sink current now is approximately I1 times the h_FE of Q2 (700 A at V_O = 0.4 V). The output of the devices exhibits a bimodal characteristic, with a smooth transition between modes.

In both cases, the output is an uncommitted collector. Several outputs can be tied together to provide a dot logic function. An output pullup resistor can be connected to any available power-supply voltage within the permitted power-supply range, and there is no restriction on this voltage, based on the magnitude of the voltage that is supplied to V_CC of the package.

PACKAGING INFORMATION

Orderable Device Status(1)		Package Type	Package Drawing	Pins	Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4-5)	Samples
LP2901D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LP2901											Samples
LP2901DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LP2901											Samples
LP2901DRE4	ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LP2901										Samples
LP2901DRG4	ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LP2901										Samples
LP2901N	ACTIVE	PDIP	N	14	25	RoHS & Green	NIPDAU	N / A for Pkg Type	-40 to 85	LP2901N	Samples
LP339D	ACTIVE	SOIC	D	14	50	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	0 to 70	LP339	Samples
LP339DE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU					Level-1-260C-UNLIM 0 to 70 LP339						Samples
LP339DG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LP339											Samples
LP339DR	ACTIVE	SOIC	D	14	2500	RoHS & Green	NIPDAU | SN	Level-1-260C-UNLIM	0 to 70	LP339	Samples
LP339DRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70							LP339				Samples
LP339DRG4	ACTIVE	SOIC	D	14	2500	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	0 to 70	LP339	Samples
LP339N	ACTIVE	PDIP	N	14	25	RoHS & Green	NIPDAU	N / A for Pkg Type	0 to 70	LP339N	Samples

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "\~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LP2901 :

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package	Type	Package Drawing	Pins	SPQ Reel	Diameter (mm)	Reel Width W1 (mm)	A0 (mm)	B0 (mm)	K0 (mm)	P1 (mm)	W (mm)	Pin1 Quadrant
LP2901DR SOIC D	14 2500	330.0 16.4	6.5 9.0	2.1 8.0 16	6.0 Q1
LP2901DR SOIC D	14 2500	330.0 16.4	6.5 9.0	2.1 8.0 16	6.0 Q1
LP339DR SOIC D	14 2500	330.0 16.8	6.5 9.5	2.1 8.0 16	6.0 Q1
LP339DR SOIC D	14 2500	330.0 16.4	6.5 9.0	2.1 8.0 16	6.0 Q1
LP339DR SOIC D	14 2500	330.0 16.4	6.5 9.0	2.1 8.0 16	6.0 Q1
LP339DRG4 SOIC D	14 2500	330.0 16.4	6.5 9	0 2.1 8.0	6.0 Q1
LP339DRG4 SOIC D	14 2500	330.0 16.4	6.5 9	0 2.1 8.0	6.0 Q1

TAPE AND REEL BOX DIMENSIONS W L

*All dimensions are nominal

Device	Package Type	Package Drawing	Pins	SPQ	Length (mm)	Width (mm)	Height (mm)
LP2901DR SOIC D	14 2500 340.5 336.1	32.0
LP2901DR SOIC D	14 2500 853.0 449.0	35.0
LP339DR SOIC D	14 2500 364.0 364.0	27.0
LP339DR SOIC D	14 2500 340.5 336.1	32.0
LP339DR SOIC D	14 2500 853.0 449.0	35.0
LP339DRG4 SOIC D	14 2500 340.5 336.1	32.0
LP339DRG4 SOIC D	14 2500 853.0 449.0	35.0

TUBE

T - Tube height L - Tube length W-Tube width B - Alignment groove width

*All dimensions are nominal

Device	Package Name	Package Type	Pins	SPQ	L (mm)	W (mm)	T (μm)	B (mm)
LP2901D D SOIC	14 50 507 8 3940 4.32
LP2901D D SOIC	14 50 506.6 8 3940 4.32
LP2901N N PDIP	14 25 506 13.97	11230 4.32
LP339D	D SOIC 14	50 507 8 3940 4.32
LP339D	D SOIC 14	50 506.6 8 3940 4.32
LP339DE4	D SOIC 14	50 506.6 8 3940 4.32
LP339DE4	D SOIC 14	50 507 8 3940 4.32
LP339DG4	D SOIC 14	50 507 8 3940 4.32
LP339DG4	D SOIC 14	50 506.6 8 3940 4.32
LP339N	N PDIP 14	25 506 13.97	11230 4.32

N (R-PDIP-T\*\*)

16 PINS SHOWN

PLASTIC DUAL-IN-LINE PACKAGE

A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) 0.045 (1,14)

C

DIM\PINS **	14	16	18	20
A MAX	0.775(19,69)	0.775(19,69)	0.920(23,37)	1.060(26,92)
A MIN	0.745(18,92)	0.745(18,92)	0.850(21,59)	0.940(23,88)
MS-001VARIATION	AA	BB	AC	AD

0.045 (1,14) 0.030 (0,76) D 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) ⊕ 0.010 (0,25) M 14/18 Pin Only 20 Pin vendor opt

0.325 (8,26) 0.300 (7,62) 0.015 (0,38) Gauge Plane 0.010 (0,25) NOM 0.430 (10,92) MAX

4040049/E 12/2002

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C Falls within JEDEC MS-001, except 18 and 20 pin minimum body length (Dim A).

The 20 pin end lead shoulder width is a vendor option, either half or full width.

D (R-PDSO-G14)
PLASTIC SMALL OUTLINE

0.344 (8,75) 0.337 (8,55) 14 8 Pin 1 Index Area 1 0.050 (1,27) 7 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,80) 0.020 (0,51) 0.012 (0,31) ⊕ 0.010 (0,25) M 0.069 (1,75) Max 0.010 (0,25) 0.004 (0,10) Gcuge Plane 0.010 (0,25) 0.005 (0,13) 0°-8° Seating Plane 0.010 (0,25) 0.050 (1,27) 0.016 (0,40) 4040047-5/M 06/11

NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.006 (0,15) each side.
Body width does not include interlead flash. Interlead flash shall not exceed 0.017 (0,43) each side.
E. Reference JEDEC MS-012 variation AB.

D (R-PDSO-G14)

4211283-3/E 08/12
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate designs.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

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