LMC6482IM/NOPB - Electronic component TEXAS INSTRUMENTS - Free user manual and instructions

USER MANUAL LMC6482IM/NOPB TEXAS INSTRUMENTS

LMC6482CMOSDualRail-to-RailInputandOutputOperationalAmplifier

1 Features

•Specificationsaretypicalunlesssotherwisenoted
• Rail-to-railinputcommon-modevoltagerange (specified over temperature)
- Rail-to-railoutputswing(within20-mVofsupply rail,100-kΩ load)
•Specified3-V,5-V,and15-Vperformance
•ExcellentCMRRandPSRR:82dB
•Ultra-lowinputcurrent:20fA
•Highvoltagegain(RL=500kΩ):130dB
•Specifiedfor2-kΩ and600-Ω loads
•Power-goodoutput
•Packages:PDIP,SOIC,andVSSOP

2 Applications

•Dataacquisition(DAQ)
•Currencycounter
•Oscilloscope(DSO)
•Intra-DCinterconnect(METRO)
•Macroremoteradiounit(RRU)
•Multiparameterpatientmonitor
• Merchanttelecomrectifiers
• Traincontrolandmanagement
- Processanalytics(pH,gas,concentration,force, andhumidity)
•ThreephaseUPS
- ImprovedreplacementforTLC272,TLC277

3 Description

TheLMC6482deviceprovidesacommmon-mode rangethatextendstobothsupplyrails. This rail-to-rail performancecombinedwithexcellentaccuracy, due toahighCMRR, make this device unique among rail-to-rail input amplifiers. The device is an excellent choice for systems, such as data acquisition, that require a large input signal range. The LMC6482 is also an excellent upgrade for circuits using limited common-mode range amplifiers, such as the TLC272 and TLC277.

Maximum dynamic signal range is provided in low voltage and singlesupplysystemsbytherail-to-rail output swing of the LMC6482. The rail-to-rail output swing is maintained for loads down to 600 Ω of the device. Specified low-voltage characteristics and low-power dissipationmaketheLMC6482agreatchoice forbattery-operatedsystems.

TheLMC6482 isavailablein8-pinPDIPandSOIC packages. The device is also available in a VSSOP package, almost half the size of a SOIC-8 device. See the LMC6484 for a quad CMOS operational amplifierwiththesesamefeatures.

DeviceInformation (1)

(1) For all available packages, seethe package option addendum at the end of the datasheet.

Rail-to-RailInput

Rail-to-RailOutput

TableofContents

1 Features.... 1
2 Applications 1
3 Description 1
4 Revision History...... 2

5PinConfigurationandFunctions....3

6 Specifications.... 3

6.1 AbsoluteMaximumRatings....3
6.2ESDRatings....4
6.3RecommendedOperatingConditions....4
6.4ThermalInformation....4
6.5ElectricalCharacteristicsforV ^+ =5V....4
6.6ElectricalCharacteristicsforV ^+ =3V....7
6.7TypicalCharacteristics....9

7DetailedDescription....18

7.1Overview....18
7.2FunctionalBlockDiagram....18

7.3FeatureDescription....18
7.4DeviceFunctionalModes....19

8ApplicationandImplementation....20

8.1 Application Information....20
8.2TypicalApplications....22

9PowerSupplyRecommendations....28

10 Layout.... 28

10.1 LayoutGuidelines....28
10.2LayoutExample....28

11DeviceandDocumentationSupport....30

11.1 ReceivingNotificationofDocumentationUpdates30
11.2SupportResources....30
11.3Trademarks....30
11.4ElectrostaticDischargeCaution....30
11.5Glossary....30

12Mechanical, Packaging, and Orderable Information 30

4RevisionHistory

NOTE: Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion.

ChangesfromRevisionF(April2020)toRevisionG

Page

- Deletedoldnote4from ElectricalCharacteristicsforV

^+ = 5 Vtable. 4

ChangesfromRevisionE(April2015)toRevisionF

Page

- Changed junction temperature max value from -85^ to 85^ (typo) in Recommended Operating Conditions table...... 4

ChangesfromRevisionD(March2013)toRevisionE

Page

- Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .... 1

ChangesfromRevisionC(March2013)toRevisionD

Page

- Changed layout of National Semiconductor Data Sheet to TI format 27

5PinConfigurationandFunctions

D,DGK,andPPackages
8-PinSOIC, VSSOP, and PDIP TopView

OUTPUT A 1 INVERTING INPUT A 2 NONINVERTING INPUT A 3 V- 4 A B OUTPUT B 7 6 INVERTING INPUT B 5 NONINVERTING INPUT B 8 V+

PinFunctions

PIN		TYPEDESCRIPTION
NO.NAME
1OUTPUTAO	OutputforAmplifierA
2INVERTING	INPUTAINvertinginputforAmplifierA
3NONINVERT	TINGINPUTAlNoninvertinginputforAmplifierA
4	V^-	P	Negativesupplyvoltageinput
5NONINVERT	TINGINPUTBINoninvertinginputforAmplifierB
6INVERTING	INPUTBINvertinginputforAmplifierB
7OUTPUTBO	OutputforAmplifierB
8	V^+	P	Positivesupplyvoltageinput

6Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ^(1)(2)

		MIN	MAX	UNIT
	Differentialinputvoltage	±SupplyVoltage
	Voltageatinput/outputpin	(V-)-0.3	(V+)+0.3	V
	Supplyvoltage(V+-)		16	V
	Currentatinputpin (3)	-5	5	mA
	Currentatoutputpin (4)(5)	-30	30	mA
	Currentatpowersupplypin		40	mA
	Lead temperature (soldering, 10 sec.)		260	°C
	Junctiontemperature (6)		150	°C
T_stg	Storage temperature	-65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings.
(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150^ C. Output currents in excess of ±30 mA over long term may adversely affect reliability.
(5) DonotshortcircuitoutputtoV +,whenV + isgreaterthan13Vorreliabilitywillbeadverselyaffected.
(6) Themaximumpowerdissipationisafunctionof T_J() , R_ JA , and T_A . Themaximumallowablepowerdissipationatanyambient temperatureis P_D = (T_J() - ) / _JA . All numbers apply for packagessoldered directly into a PC board.

6.2ESDRatings

				VALUEUNIT
V_(ESD)	ElectrostaticdischargeHuman	-bodymodel(HBM),perANSI/ESDA/JEDECJS-001	(1)	±1500V

(1)JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.

6.3 Recommended Operating Conditions

overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1)

			MINMAXUNIT
	Supplyvoltage315.5 V
	Junctiontemperature	LMC6482AM	-55	125	°C
		LMC6482AI,LMC6482I	-40	85	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.4ThermalInformation

THERMALMETRIC (1)		LMC6482	LMC6482	LMC6482	UNIT
		D(SOIC)	DGK(VSSOP)	P(PDIP)
		8PINS8PINS8PINS
R_ JA	Junction-to-ambient thermal resistance	155	194	90	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics for V ^+ =5V

unless otherwise specified, all limit specific for T J=25^,V^+=5V,V^-=0V,VCM=V_O=V^+/2andR_L>1M.

PARAMETER		TESTCONDITIONS	T_J =25°C			ATTEMPERATURE EXTREMES(1)			UNIT
			MIN	TYP(2)	MAX(3)	MIN	TYP(2)	MAX(3)
DCELECTRICALCHARACTERISTICS
V_OS	Inputoffset voltage	LMC6482AI		0.11	0.75			1.35	mV
		LMC6482I		0.11	3			3.7
		LMC6482M		0.11	3			3.8
TCV_OS	Inputoffset voltage averagedrift			1					μV/°C
I_B	Inputcurrent	LMC6482AI		0.02				4	pA
		LMC6482I		0.02				4
		LMC6482M		0.02				10
I_OS	Inputoffset current	LMC6482AI		0.01				2	pA
		LMC6482I		0.01				2
		LMC6482M		0.01				5
C_IN	Common-modeinput capacitance			3					pF
R_IN	Input resistance			10					TeraΩ

(1) See Recommended Operating Conditions for operating temperature ranges.
(2) Typicalvaluesrepresentthemostlikelyparametricnorm.
(3) Alllimitsarespecifiedbytestingorstatisticalanalysis.

ElectricalCharacteristicsforV ^+=5V (continued)

unless otherwise specified, all limit unspecified for T J=25^,V^+=5V,V^-=0V,VCM=V_O=V^+/2andR_L>1M.

PARAMETERTEST CONDITIONS					T_J =25°C			ATTEMPERATURE EXTREMES(1)			UNIT
					MINTYP (2) MAX(3)			MINTYP (2) MAX(3)
CMRR	Common-moderejection ratio	0V≤ V_CM ≤ 15V V^+ =15V	LMC6482AI708267								dB
			LMC6482I658262
			LMC6482M658260
		0V≤ V_CM ≤ 5V V^+ =5V	LMC6482AI708267
			LMC6482I658262
			LMC6482M658260
+PSRR	Positivepower supply rejectionratio	5V≤ V^+ ≤ 15V, V^-=0V V_O=2.5V	LMC6482AI708267								dBLMC6482I658262
			LMC6482M658260
-PSRR	Negative powersupply rejectionratio	-5V≤ V^- ≤ -15V, V^+=0V V_O=-2.5V	LMC6482AI708267								dBLMC6482I658262
			LMC6482M658260
V_CM	Input common-modevoltage	V^+=5Vand15VForCMRR≥ 50dB	LMC6482AI		V^--0.3-0.25						0 V
			LMC6482I		V^--0.3-0.25
			LMC6482M		V^--0.3-0.25
			LMC6482AI		V^++V^++0.3V0.25				+		V
			LMC6482I		V^++V^++0.3V0.25				+
			LMC6482M		V^++V^++0.3V0.25				+
A_V	Largesignal voltagegain	R_L=2kΩ^(4)	Sourcing	LMC6482AI	140	66684					V/mV
				LMC6482I	120	66672
				LMC6482M	120	66660
			Sinking	LMC6482AI	357520						V/mV
				LMC6482I	357520
				LMC6482M	357518
		R_L=600Ω^(4)	Sourcing	LMC6482AI	80	30048					V/mV
				LMC6482I	50	30030
				LMC6482M	50	30025
			Sinking	LMC6482AI	203513						V/mV
				LMC6482I	153510
				LMC6482M	1535	8

(4) V^+=15V, V_CM=7.5V and R_L connected to 7.5V. Forsourcing tests, 7.5V ≤ V_O ≤ 11.5V. Forsinking tests, 3.5V ≤ V_O ≤ 7.5V.

ElectricalCharacteristicsforV + =5V(continued)

unless otherwise specified, all limit unspecified for T J=25^,V^+=5V,V^-=0V,VCM=V_O=V^+/2andR_L>1M.

PARAMETERTEST CONDITIONS				T_J =25°C			ATTEMPERATURE EXTREMES(1)		UNIT
				MINTYP (2) MAX(3)			MINTYP (2) MAX(3)
V_O	Outputswing	V^+ = 5V R_L = 2kΩ to V^+/2	LMC6482AI4.84.94.7						V
			LMC6482I4.84.94.7
			LMC6482M4.84.94.7
			LMC6482AI0.10.18	0.24
			LMC6482I	0.10.18			0.24
			LMC6482M	0.10.18			0.24
		V^+ = 5V R_L = 600Ω to V^+/2	LMC6482AI4.54.7	4.24					V
			LMC6482I4.54.7	4.24
			LMC6482M4.54.7	4.24
			LMC6482AI0.3 0.5	0.65
			LMC6482I	0.3 0.5			0.65
			LMC6482M	0.3 0.5			0.65
		V^+ = 15V R_L = 2kΩ to V^+/2	LMC6482AI	14.4 14.7			14.2		V
			LMC6482I14.4 14.7	14.2
			LMC6482M	14.4 14.7			14.2
			LMC6482AI	0.160.32			0.45
			LMC6482I	0.160.32			0.45
			LMC6482M	0.160.32			0.45
		V^+ = 15V R_L = 600Ω to V^+/2	LMC6482AI	13.4 14.1			13		V
			LMC6482I13.4 14.1	13
			LMC6482M	13.4 14.1			13
			LMC6482AI0.5 1	1.3
			LMC6482I	0.5 1			1.3
			LMC6482M	0.5 1			1.3
I_SC	Outputshort circuitcurrent V^+ = 5V	Sourcing, V_O=0V	LMC6482AI	16 20			12		mA
			LMC6482I	16 20			12
			LMC6482M	16 20			10
		Sinking, V_O=5V	LMC6482AI	11 159.5					mA
			LMC6482I	11 159.5
			LMC6482M	11 15			8
I_SC	Outputshort circuitcurrent V^+ = 15V	Sourcing, V_O=0V	LMC6482AI	28 30			22		mA
			LMC6482I	28 30			22
			LMC6482M	28 30			20
		Sinking, V_O=12V^(5)	LMC6482AI	30 30			24		mA
			LMC6482I	30 30			24
			LMC6482M	30 30			22
I_S	Supplycurrent	BothAmplifiers V^+ = +5V , V_O=V^+/2	LMC6482AI	1 1.4			1.8		mA
			LMC6482I	1 1.4			1.8
			LMC6482M	1 1.4			1.9
		BothAmplifiers V^+ = 15V , V_O=V^+/2	LMC6482AI1.3 1.6	1.9					mA
			LMC6482I	1.3 1.6			1.9
			LMC6482M	1.3 1.6			2

(5) DonotshortcircuitoutputtoV +, when V + isgreaterthan13Vorreliabilitywillbeadverselyaffected.

ElectricalCharacteristicsforV + =5V(continued)

unless otherwise specified, all limit unspecified for T J=25^,V^+=5V,V^-=0V,VCM=V_O=V^+/2andR_L>1M.

PARAMETERTEST		CONDITIONS	T_J =25°C		ATTEMPERATURE EXTREMES(1)	UNIT
			MINTYP (2) MAX(3)		MINTYP (2) MAX(3)
ACELECTRICALCHARACTERISTICS
SRSlewrate (6)		LMC6482AI11.30.7				V/μsLMC6482I0.91.3
		LMC6482M	0.91.3	0.54
GBW	Gain-bandwidth product	V^+ =15V	1.5			MHz
_m	Phasemargin		50			Deg
G_m	Gainmargin		15			dB
	Amp-to-amp isolation	See (7)	150			dB
e_n	Input-referred voltagenoise	F=1kHz V_cm =1V	37			nV/
I_n	Input-referred currentnoise	F=1kHz	0.03			pA/
T.H.D.	Total harmonic distortion	F=10kHz,AV=-2 R_L =10kΩ, V_O =4.1V PP	0.01%
		F=10kHz,AV=-2 R_L =10kΩ, V_O =8.5V PP V^+ =10V	0.01%

(6) V + = 15V. Connected as voltage follower with 10-V step input. Number specified is the slower of either the positive or negative slew rates.
(7) Input referred, V ^+ =15V and R L =100kΩ connected to 7.5V. Each ampexcited in turn with 1kHz to produce V O =12V PP.

6.6 ElectricalCharacteristicsforV ^+=3V

Unless otherwise specified, all limits specified for T J=25^,V^+=3V,V^-=0V,VCM=V_O=V^+/2andR_L>1M .

PARAMETER		TESTCONDITIONS		T_J =25°C			ATTEMPERATURE EXTREMES(1)			UNIT
				MIN	TYP(2)	MAX(3)	MIN	TYP(2)	MAX(3)
DCELECTRICALCHARACTERISTICS
V_OS	Inputoffset voltage	LMC6482AI		0.9		2	2.7			mV
		LMC6482I		0.9		3	3.7
		LMC6482M		0.9		3	3.8
TCV_OS	Inputoffset voltage averagedrift			2						μV/°C
I_B	Inputbias current			0.02						pA
I_os	Inputoffset current			0.01						pA
CMRR	Common moderejection ratio	0V≤ V_CM ≤ 3V	LMC6482AI64	74						dB
			LMC6482I	60	74
			LMC6482M	60	74

(1) See Recommended Operating Conditions for operating temperature ranges.
(2) Typical values represent themost likely parametricnorm.
(3) Alllimitsarespecifiedbytestingorstatisticalanalysis.

ElectricalCharacteristicsforV + =3V(continued)

Unless otherwise specified, all limits specified for T J=25^,V^+=3V,V^-=0V,VCM=V_O=V^+/2andR_L>1M .

PARAMETERTEST CONDITIONS				T_J =25°C		ATTEMPERATURE EXTREMES(1)		UNIT
				MINTYP (2) MAX(3)		MINTYP (2) MAX(3)
PSRR	Powersupply rejection ratio	3V≤ V* ≤ 15V, V- =0V	LMC6482AI6880					dBLM C6482I6080
			LMC6482M6080
V_CM	Inputcommon-modevoltage	ForCMRR≥ 50 dB	LMC6482AIV	- -0.25 0				V
			LMC6482I	V- -0.25 0
			LMC6482M	V- -0.25 0
			LMC6482AIV	+ V+ +0.25				V
			LMC6482IV	+ V+ +0.25
			LMC6482MV	+ V+ +0.25
V_O	Outputswing	R_L =2kΩ toV+/2		2.8				V
				0.2
		R_L =600Ω to V+/2	LMC6482AI	2.5 2.7
			LMC6482I	2.5 2.7
			LMC6482M	2.5 2.7
			LMC6482AI	0.37 0.6
			LMC6482I	0.37 0.6
			LMC6482M	0.37 0.6
I_S	SupplycurrentBothamplifiers		LMC6482AI	0.825 1.2		1.5		mA
			LMC6482I	0.825 1.2		1.5
			LMC6482M	0.825 1.2		1.6
ACELECTRICALCHARACTERISTICS
SR	Slewrate	See (4)		0.9				V/μs
GBW	Gain-bandwidth product			1				MHz
T.H.D.	Totalharmonic distortion	f=10kHz,A v=-2 R_L =10kΩ,V O=2V PP		0.01%

(4) Connected as voltage follower with 2-V step input. Number specified is the slower of either the positive or negative slew rates.

6.7 Typical Characteristics

at V_S=15V , singlesupply, and T _A=25^ (unless otherwise specified)

Figure1. SupplyCurrentvsSupplyVoltage

Figure2.InputCurrentvsTemperature

Figure3.SourcingCurrentvsOutputVoltageFigure4.SourcingCurrentvsOutputVoltage

Figure5.SourcingCurrentvsOutputVoltage
Figure6.SinkingCurrentvsOutputVoltage

TypicalCharacteristics(continued)

at V_S = 15V , singlesupply, and T _A = 25^ (unless otherwise specified)

Figure7.SinkingCurrentvsOutputVoltageFigure8.SinkingCurrentvsOutputVoltage

Figure9.OutputVoltageSwingvsSupplyVoltage

Figure10.InputVoltageNoisevsFrequency

Figure11.InputVoltageNoisevsInputVoltageFigure12.InputVoltageNoisevsInputVoltage

TypicalCharacteristics(continued)

at V_S = 15V , singlesupply, and T _A = 25^ (unless otherwise specified)

Figure13.InputVoltageNoisevsInputVoltage

Figure14.CrosstalkRejectionvsFrequency

Figure15.CrosstalkRejectionvsFrequencyFigure16. PositivePSRRvsFrequency

Figure17.NegativePSRRvsFrequencyFigure18.CMRRvsFrequency

TypicalCharacteristics(continued)

at V_S = 15V , singlesupply, and T _A = 25^ (unless otherwise specified)

Figure19.CMRRvsInputVoltageFigure20.CMRRvsInputVoltage

Figure21.CMRRvsInputVoltage

Figure22.Δv os vsCMR

Figure23.Av os vsCMR

Figure24.InputVoltagevsOutputVoltage

TypicalCharacteristics(continued)

at V_S = 15V , singlesupply, and T _A = 25^ (unless otherwise specified)

Figure25.InputVoltagevsOutputVoltage

Figure26.Open-LoopFrequencyResponse

Figure27.Open-LoopFrequencyResponseFigure28.Open-LoopFrequencyResponsevsTemperature

Figure29.MaximumOutputSwingvsFrequency

Figure30.GainandPhasevsCapacitiveLoad

TypicalCharacteristics(continued)

at V_S = 15V , singlesupply, and T _A = 25^ (unless otherwise specified)

Figure31.GainandPhasevsCapacitiveLoadFigure32.Open-LoopOutputImpedancevsFrequency

Figure33.Open-LoopOutputImpedancevsFrequency

Figure34.SlewRatevsSupplyVoltage

Figure35.NoninvertingLargeSignalPulseResponseFigure36.NoninvertingLargeSignalPulseResponse

TypicalCharacteristics(continued)

at V_S = 15V , singlesupply, and T _A = 25^ (unless otherwise specified)

Figure37.NoninvertingLargeSignalPulseResponseFigure38.NoninvertingSmallSignalPulseResponse

Figure39.NoninvertingSmallSignalPulseResponseFigure40.NoninvertingSmallSignalPulseResponse

Figure41.InvertingLargeSignalPulseResponseFigure42.InvertingLargeSignalPulseResponse

TypicalCharacteristics(continued)

at V_S = 15V , singlesupply, and T _A = 25^ (unless otherwise specified)

Figure43.InvertingLargeSignalPulseResponseFigure44.InvertingSmallSignalPulseResponse

Figure45.InvertingSmallSignalPulseResponseFigure46.InvertingSmallSignalPulseResponse

Figure47.StabilityvsCapacitiveLoadFigure48.StabilityvsCapacitiveLoad

TypicalCharacteristics(continued)

at V_S = 15V , singlesupply, and T _A = 25^ (unless otherwise specified)

Figure49.StabilityvsCapacitiveLoadFigure50.StabilityvsCapacitiveLoad

Figure51.StabilityvsCapacitiveLoadFigure52.StabilityvsCapacitiveLoad

7DetailedDescription

7.1Overview

TheLMC6482isadualCMOSoperationalamplifierthatsupportsbothrail-to-railinputsandoutputs. The device can be operated in both dual-supply mode and single-supply mode.

7.2FunctionalBlockDiagram

OUTPUT A 1 INVERTING INPUT A 2 NONINVERTING INPUT A 3 V⁻ 4 A B 8 V+ 7 OUTPUT B 6 INVERTING INPUT B 5 NONINVERTING INPUT B

7.3FeatureDescription

7.3.1AmplifierTopology

TheLMC6482incorporatesspeciallydesignedwide-complianceangecurrentmirrorsandthebodyeffectto extendinputcommon-moderangetoeachsupplyrail.Complementaryparalleleddifferentialinputstages,likethe typeusedinotherCMOSandbipolarrail-to-railinputamplifiers,werenotusedbecauseoftheirinherent accuracyproblemsduetoCMRR,crossoverdistortion,andopen-loopgainvariation.

TheLMC6482sinputstagedesigniscomplementedbyanoutputstagecapableofrail-to-railoutputswingeven whendrivingalargeload.Rail-to-railoutputswingisobtainedbytakingtheoutputdirectlyfromtheinternal integratorinsteadofanoutputbufferstage.

7.3.2 InputCommon-ModeVoltageRange

UnlikeBi-FETamplifierdesigns,theLMC6482doesnotexhibitphaseinversionwhenaninputvoltageexceeds the negative supply voltage. Figure 53 shows an input voltage exceeding both supplies with no resulting phase inversionontheoutput.

AninputvoltagesignalexceedsthelMC6482powersupplyvoltageswithnooutputphaseinversion.

Figure53. InputVoltage

FeatureDescription(continued)

The absolutemaximuminputvoltageis300mVbeyondeithersupplyrailatroomtemperature.Voltagesgreatly exceeding this absolute maximum rating, as in Figure 54, can cause excessive current to flow in or out of the inputpinspossiblyaffectingreliability.

NOTE: A ±7.5-V input signal greatly exceeds the 3-V supply in Figure 55 causing no phase inversion due to R _i .

Figure54.InputSignal

Application that exceed this rating must externally limit the maximum input current to ±5mA with an input resistor (R _1 ) as shown in Figure 55.

3V - ½ LMC6482 + R₁=10 kΩ Vₐₙ Vₒₐₜ

NOTE: R , inputcurrentprotectionforvoltagesexceedingthesupplyvoltages.

Figure55.R, InputCurrentProtectionfor VoltagesExceedingtheSupplyVoltages

7.3.3 Rail-to-RailOutput

The approximated output resistance of the LMC6482 is 180- sourcing and 13-0 sinking at V_S=3V_and110- sourcing and 80- sinking at V_S=5V . Using the calculated output resistance, the maximum output voltage swing can be estimated as a function of load.

7.4DeviceFunctionalModes

TheLMC6482canbeusedinapplicationswhereeachamplifierchannelisusedindependently,orinapplications in which the channels are cascaded. See the Typical Applications section for more information.

8ApplicationandImplementation

NOTE

InformationinthefollowingapplicationssectionsisnotpartoftheTlcomponent specification,andTldoesnotwarrantitsaccuracyorcompleteness.TI'scustomersare responsiblefordeterminingsuitabilityofcomponentsfortheirpurposes.Customersshould validateandtesttheirdesignimplementationtoconfirmsystemfunctionality.

8.1 Application Information

8.1.1 Upgrading Applications

TheLMC6484quadsandLMC6482dualshaveindustry-standardpinoutstoretofitexistingapplications.

System performance can be greatly increased by the features of the LMC6482. The key benefit of designing in the LMC6482 is increased linear signal range. Most op-amps have limited input common-mode ranges. Signals that exceed this range generate a nonlinear output response that persists long after the input signal returns to the common-moderange.

Linear signal range is vital in applications such as filters where signal peaking can exceed input common-mode ranges resulting in output phase inversion or severe distortion.

8.1.2 DataAcquisitionSystems

Low power, single supply data acquisition system solutions are provided by buffering the ADC12038 with the LMC6482 (Figure 56). Capable of using the full supply range, the LMC6482 does not require input signals to be scaled down to meet limited common-mode voltage ranges. The LMC4282 CMRR of 82 dB maintains integral linearity of a 12-bit data acquisition system to ±0.325 LSB. Other rail-to-rail input amplifiers with only 50 dB of CMRRwilldegradetheaccuracyofthedataacquisitionsystemtoonly8bits.

5V 12.1 kΩ 1 kΩ LMC6482 ½ + VA+ ADC12038 1000 pF VIN 1 kΩ 500 kΩ 1/2 + COM 2.5V 2 kΩ LMC6482 ½ - 2.048V 500Ω 200 kΩ 33Ω 0.47 μF 130 kΩ 10 μF VREF+ VREF- AGND

NOTE: Operating from the same supply voltage, the LMC6482 buffers the ADC12038 maintaining excellent accuracy.

Figure56.BufferingtheADC12038WiththeLMC6482

ApplicationInformation(continued)

8.1.3 Instrumentation Circuits

TheLMC6482hasthehighinputimpedance,largecommon-moderangeandhighCMRRneededfordesigning instrumentationcircuits.InstrumentationcircuitsdesignedwiththeLMC6482canrejectalargerrangeof common-modesignalsthanmostin-amps.ThismakesinstrumentationcircuitsdesignedwiththeLMC6482an excellentchoiceofnoisyorindustrialenvironments. Otherapplicationsthatbenefitfromthesefeaturesinclude analyticmedicalinstruments,magneticfielddetectors,gasdetectors,andsilicon-basedtransducers.

AsmallvaluedpotentiometerisusedinserieswithR _g tosetthedifferentialgainofthe3-op-ampinstrumentation circuit in Figure 57. This combination is used instead of one large valued potentiometer to increase gain trim accuracyandreduceerrorduetovibration.

10 kΩ R1 A1 LMC6482 + - C2 50 kΩ, 0.1% 0.1% 50 kΩ C4 3-20 pF AC CMR ADJUST 50 kΩ, 0.1% VIN RG C3 R1 A2 LMC6482 + - C1 10 pF A3 LMC6482 + - VOUT 48.7 kΩ DC CMR ADJUST R2 500Ω VREFERENCE

Figure57.Low-Power,Three-Op-AmplInstrumentationAmplifier

A two-op-amp instrumentation amplifier designed for a gain of 100 is shown in Figure 58. Low sensitivity trimming is made for offset voltage, CMRR, and gain. Low cost and low power consumption are the main advantages of this two-op-amp circuit.

Higher frequency and larger common-mode range applications are best facilitated by a three-op-amp instrumentationamplifier.

CMRR Trim 50Ω VCM + 1/2VD 9.95k 10k, 0.1% 191Ω 10Ω Gain Trim A1 ½ LMC6482 10k, 0.1% 10k, 0.1% - A2 ½ LMC6482 VCM - 1/2VD VOUT = 100VD

Figure58.Low-Power, Two-Op-AmplInstrumentationAmplifier

8.1.4 Spice Macromodel

AspicemacromodelisavailablefortheLMC6482. Thismodelincludesaccuratesimulationofthefollowing:

• Inputcommon-modevoltagerange
• Frequency and transient response
• GBWdependenceonloadingconditions
• Quiescentanddynamicsupplycurrent
• Outputswingdependenceonloadingconditions

Manymorecharacteristicsarelistedonthemacromodeldisk.

ContactyourlocalTIsalesofficetoobtainanoperationalamplifierspicemodellibrarydisk.

8.2TypicalApplications

8.2.13-VSingle-SupplyBufferCircuit

+3V 0.1 μF VIN ½ - LMC6482 VOUT

Figure59.3-VSingle-SupplyBufferCircuit

8.2.1.1 Design Requirements

Forbestperformance, makesure that the input voltages wing is between V+andV-.

Also, make certain that the input does not exceed the common-mode input range.

Toreducetheriskofdestabilizingtheoutput,useresistiveisolationontheoutputwhendrivingcapacitiveloads(seetheDetailedDesignProceduresection).

When large feedback resistors are used, compensation for parasitic capacitance on the input may be necessary. Seethe Detailed Design Procedure section.

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Capacitive Load Compensation

Capacitive load compensation can be accomplished using resistive isolation as shown in Figure 60. This simple technique is useful for isolating the capacitive input of multiplexers and converters.

LMC6482 R = 300 Ω CL = 330 pF

Figure60.Resistivelsolationofa330-pFCapacitiveLoad

Figure61.PulseResponseoftheLMC6482CircuitinFigure60

TypicalApplications(continued)

8.2.1.2.2 Capacitive Load Tolerance

TheLMC6482cantypicallydirectlydrivea100-pFloadwithV _S =15Vatunitygainwithoutoscillating.Theunity gainfolloweristhemostsensitiveconfiguration.Directcapacitiveloadingreducesthephasemarginofop-amps. Thecombinationoftheoutputimpedanceoftheop-ampandthecapacitiveloadinducesphaselag.Thisresults ineitheranunderdampedpulseresponseoroscillation.

Improved frequency response is achieved by indirectly driving capacitive loads, as shown in Figure 62.

10 kΩ C₁ 100 pF ½ LMC6482 Vₐₙ + - R1 300 Ω Vₒᵤₜ Cₗ = 330 pF

NOTE: Compensated to handle a 330-pF capacitive load.

Figure62.LMC6482NoninvertingAmplifier

R1 and C1 servetocounteract the lossof phasemargin by feeding forward the high-frequency component of the output signal back to the amplifiers inverting input, thereby preserving phasemargin in the overall feedback loop. The values of R1 and C1 are experimentally determined for the desired pulseresponse. The resulting pulse response is shown in Figure 63.

Figure63.PulseResponseof Lmc6482CircuitinFigure62

8.2.1.2.3 Compensating For Input Capacitance

Itisquitecommontouselargevaluesoffeedbackresistancewithamplifiersthathaveultra-lowinputcurrent, liketheLMC6482. Largefeedbackresistorscanreactwithsmallvaluesofinputcapacitanceduetotransducers, photodiodes,andcircuitsboardparasiticstoreducephasemargins.

TypicalApplications(continued)

VIN R1 CIN - ½ LMC6482 + Cf R2 VOUT

Figure64.CancelingtheEffectofInputCapacitance

Theeffectofinputcapacitancecanbecompensatedforbyaddingafeedbackcapacitor. Thefeedbackcapacitor (asinFigure64), C isfirstestimatedby:

$$ \frac {1}{2 \pi R _ {1} C _ {\mathrm{IN}}} \geq \frac {1}{2 \pi R _ {2} C _ {\mathrm{f}}} \tag {1} $$

or

$$ R _ {1} C _ {I N} \leq R C _ {f} \tag {2} $$

whichtypicallyprovidessignificantovercompensation.

Printed-circuit-boardstraycapacitancemaybelargerorsmallerthanthatofabread-board,sotheactual optimumvalueforC , maybedifferent.ThevaluesofC , shouldbecheckedontheactualcircuit.(Refertothe LMC660quadCMOSamplifierdatasheetforamoredetaileddiscussion.)

8.2.1.2.4OffsetVoltageAdjustment

Offset voltage adjustment circuits are illustrated in Figure 65 and Figure 66. Large value resistances and potentiometers are used to reduce power consumption while providing typically ± 2.5mV of adjustment range, referred to the input, for both configurations with V_S = ± 5V .

V+ 500 kΩ VIN R3 1 MΩ 1 kΩ 500 kΩ 499Ω V- LMC6482 ½ + -5V 5V R4 VOUT VOUT/VIN = - R4/R3

Figure65.InvertingConfigurationOffsetVoltageAdjustment

V+ 500 kΩ R1 200 kΩ R3 R4 5V V- R2 100 Ω VIN ½ LMC6482 VOUT -5V VOUT/VIN = 1 + R4/R3 ; R2 << R3

Figure66.NoninvertingConfigurationOffsetVoltageAdjustment

TypicalApplications(continued)

8.2.1.3 Application Curves

Figure67.Rail-To-RaillInput

Figure68.Rail-To-RailOutput

8.2.2 Typical Single-Supply Applications

The circuit in Figure 69 uses a single supply to half-wave rectify a sinusoid centered about ground. R _1 limits current into the amplifier caused by the input voltage exceeding the supply voltage. Full-wave rectification is provided by the circuit in Figure 71.

V+ = 3V 10 kΩ - ½ LMC6482 VIN Ri 10 kΩ VOUT

Figure69. Half-WaveRectifierWithInputCurrent Protection(R₁)

Figure70. Half-WaveRectifierWaveform

TypicalApplications(continued)

In Figure 75 dielectric absorption and leakage is minimized by using a polystyrene or polyethylene hold capacitor. Thedrooprate is primarily determined by the value of C input current of the LMC6482 has an negligible effect on droop.

V+ 10 kΩ Ri - ½ LMC6482 10 kΩ 1N9 14

Figure71.Full-WaveRectifierWithInputCurrent Protection(R₁)

V+ R - ½ LMC6482 VIN + IOUT = (V+ - VIN/R)

Figure73.LargeComplianceRangeCurrent Source

Figure72.Full-WaveRectifierWaveform

0.1Ω R1 LMC6482 - ½ + VOUT = 1 kΩ (R1/R2) IL R1 << R2

Figure74. PositiveSupplyCurrentSense

20 kΩ ½ LMC6482 1 kΩ ½ LMC6482 VOUT VIN C HOLD 100 pF

Figure75.Low-VoltagePeakDetectorWithRail-To-RailPeakCaptureRange

TypicalApplications(continued)

The high CMRR(82dB) of the LMC6482 allow sexcellent accuracy throughout the rail-dynamic capture range of the circuit.

20 kΩ LMC6482 ½ CD40566BM SAMPLE 1 kΩ C_HOLD ½ LMC6482 V_IN + - V_OUT

Figure76.Rail-To-RailSampleandHold

The low-pass filter circuit in Figure 77 can be used as an antialiasing filter with the same voltage supply as the A/Dconverter.

FilterdesignscanalsotakeadvantageoftheLMC6482ultra-lowinputcurrent. Theultra-lowinputcurrentyields negligibleoffseterroevenwhenlargevaluereresistorsareused. Thisinturnallowstheuseofsmallervalued capacitorsthattakelessboardspaceandcostless.

V_IN R1 + ½ LMC6482 R2 C1 C2 + ½ LMC6482 V_OUT R1 = R2, C1 = C2; f = ½/2πR1 C1; DF = ½√(C2/C1)√(R2/R1)

Figure77.Rail-To-RailSingleSupplyLowPassFilter

9PowerSupplyRecommendations

TheLMC6482canbeoperatedoverasupplyrangeof3Vto15V.Toachievenoiseimmunityasappropriateto theapplication,makesuretousegoodPCBlayoutpracticesforpowersupplyrailsandplanes,aswellasusing bypasscapacitorsconnectedbetweenthepowersupplypinsandground.

10Layout

10.1 LayoutGuidelines

Itisgenerallyrecognizedthatanycircuitthatmustoperatewithlessthan1000pAofleakagecurrentrequires speciallayoutofthePCboard.Totakeadvantageofthultra-lowinputcurrentoftheLMC6482,typicallyless than20fA,anexcellentlayoutisessential.Fortunately,thetechniquesofobtaininglowleakagesarequite simple.First,donotignorethesurfaceleakageofthePCB,Eventhroughtheleakagecurrentmaysometimes appearacceptablylow,becauseunderconditionsofhighhumidityordustorcontamination,thesurfaceleakage willbeappreciable.

Tominimizetheeffectofanysurfaceleakage,layoutaringoffoilcompletelysurroundingtheLM6482sinputs andtheterminalsofcapacitors,diodes,conductors,resistors,relayterminals,andsoforthconnectedtothe inputs of the op amp, as in Figure 78. To have a significant effect, place guard rings on both the top and bottom ofthePCB.ThisPCfoilmustthenbeconnectedtoavoltagethatisatthesamevoltageastheamplifierinputs, becauseoleakagecurrentcanflowbetweenwopointsatthesamepotential.Forexample,aPCBtrace-to-pad resistanceof 10^12 ,whichisnormallyconsideredaverylargeresistance,couldleak5pAifthetracewerea5-Vbusadjacenttothepadoftheinput.Thisleakagewouldcausea250timesdegradationfromtheactual performanceoftheLMC6482.However,ifaguardringisheldwithin5mVoftheinputs,thenevenaresistance of 10^11 causes only 0.05pA of leakage current. See Figure 79 through Figure 81 for typical connections of guardringsforstandardop-ampconfigurations.

BeawarethatwhenitisinappropriatetolayoutaPCBforthesakeofjustafewcircuits,anothertechniqueis evenbetterthanaguardringonaPCB:DonotinserttheinputpinoftheamplifierintothePCBatall,butbendit upintheair,anduseonlyairasaninsulator.Airisanexcellentinsulator.Inthiscaseyoumayhavetoforego someoftheadvantagesofPCBconstruction,butheadadvantagesaresometimeswellworththeeffortofusing point-to-pointup-in-the-airwiring.SeeFigure82.

10.2LayoutExample

OUT2 -IN2 +IN2 V- OUT1 -IN1 +IN1 V+ Guard Ring

Figure78. Example of Guard Ring in PCB Layout Typical Connection of Guard Rings

LayoutExample(continued)

INPUT R1 C1 R2 Guard Ring - ½ LMC6482 OUTPUT

Figure79.InvertingAmplifierTypicalConnectionsofGuardRings

R1 Guard Ring INPUT R2 LMC6482 OUTPUT

Figure80.NoninvertingAmplifierTypicalConnectionsofGuardRings

INPUT ½ LMC6482 OUTPUT

Figure81.FollowerTypicalConnectionsofGuardRings

FEEDBACK CAPACITOR RESISTOR OP AMP PC Board SOLDER CONNECTION

NOTE: InputpinsareliftedoutofPCBandsoldereddirectlytocomponents. AllotherpinsconnectedtoPCB.

Figure82.AirWiring

11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

Toreceivenotificationofdocumentationupdates, navigatetothedeviceproductfolderonti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For changed details, reviewtherevisionhistoryincludedinanyreviseddocument.

11.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's TermsofUse.

11.3 Trademarks

E2EisatrademarkofTexasInstruments.

Allothertrademarksarethepropertyoftheirrespectiveowners.

11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.

11.5Glossary

SLYZ022—TIGlossary.

This glossarylistsandexplainsterms,acronyms,anddefinitions.

12Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data subject to changewithout notice and revision of this document. For browser-based version of this datasheet, referto the left-hand navigation.

PACKAGING INFORMATION

Orderable Device Status(1)	Package Type Package Drawing		Pins	Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4/5)	Samples
LMC6482AIM NRND SOIC D 8 95 Non-RoHS						Call TI Level-1-235C-UNLIM -40 to 85 LMC64			82AIM
LMC6482AIM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN				Level-1-260C-UNLIM -40 to 85 LMC64					82AIM	Samples
LMC6482AIMX	NRND SOIC D 8	2500	Non-RoHS		& Green	Call TI Level-1-235C-UNLIM -40 to 85 LMC64			82AIM
LMC6482AIMX/NOPB	ACTIVE	SOIC	D	8	2500	RoHS & Green	SN	Level-1-260C-UNLIM	-40 to 85	LMC6482AIM
LMC6482AIN/NOPB	ACTIVE	PDIP	P	8	40	RoHS & Green	Call TI | SN	Level-1-NA-UNLIM	-40 to 85	LMC6482AIN
LMC6482IM	NRND SOIC D 8 95 Non-RoHS					Call TI Level-1-235C-UNLIM -40 to 85 LMC64			82IM
LMC6482IM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC64									82IM	Samples
LMC6482IMM	NRND	VSSOP	DGK	8	1000	Non-RoHS & Green	Call TI Level-1-260C-UNLIM -40 to 85 A10
LMC6482IMM/NOPB	ACTIVE	VSSOP	DGK	8	1000	RoHS & Green	SN	Level-1-260C-UNLIM	-40 to 85	A10
LMC6482IMMX	NRND	VSSOP	DGK	8	3500	Non-RoHS & Green	Call TI Level-1-260C-UNLIM -40 to 85 A10
LMC6482IMMX/NOPB	ACTIVE	VSSOP	DGK	8	3500	RoHS & Green	SN	Level-1-260C-UNLIM	-40 to 85	A10
LMC6482IMX NRND SOIC D 8	2500	Non-RoHS				Call TI Level-1-235C-UNLIM -40 to 85 LMC64			82IM
LMC6482IMX/NOPB	ACTIVE	SOIC	D	8	2500	RoHS & Green	SN	Level-1-260C-UNLIM	-40 to 85	LMC6482IM
LMC6482IN/NOPB	ACTIVE	PDIP	P	8	40	RoHS & Green	Call TI	Level-1-NA-UNLIM	-40 to 85	LMC6482IN

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".
RoHS Exempt: Ti defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "\~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

Package Drawing

Pins

SPQ Reel

Diameter (mm)

Reel Width W1 (mm)

A0 (mm)

B0 (mm)

K0 (mm)

P1 (mm)

W (mm)

Pin1 Quadrant

LMC6482AIMX SOIC

D 8 2500

330.0 12.4

6.5 5

4 2.0 8.0

2.0 Q1

LMC6482AIMX/NOPB SOIC

D 8 25

00 330.0

2.4 6.5

5 5.4 2.0 8

0 12.0 Q1

LMC6482IMM VSSOP

DGK 8

1000 178.0

12.4

5.3 3.4 1.4

8.0 12.0 Q1

LMC6482IMM/NOPB

VSSOP

DGK 8 1000

178.0

12.4 5.3

3.4 1.4 8.0

12.0 Q1

LMC6482IMMX

VSSOP

DGK 8 350

0 330.0

0 12.4 5.3

3.4 1.4 8.0

12.0 Q1

LMC6482IMMX/NOPB

VSSOP

DGK 8 350

0 330.0

0 12.4 5.3

3.4 1.4 8.0

12.0 Q1

LMC6482IMX

SOIC D

8 2500 330

0.0 12

4 6.5 5.4

2.0 8.0 12.0 Q1

LMC6482IMX/NOPB SOIC

D 8 25

00 330.0

2.4 6.5

5.4 2.0 8.0

0 12.0 Q1

TAPE AND REEL BOX DIMENSIONS W L

*All dimensions are nominal

Device	Package Type	Package Drawing	Pins	SPQ	Length (mm)	Width (mm)	Height (mm)
LMC6482AIMX SOIC	D 8 2500 367.0 367.0 35.0
LMC6482AIMX/NOPB SOIC	D 8 2500 367.0 367.0 35.0
LMC6482IMM VSSOP DGK	8 1000 208.0 191.0 35.0
LMC6482IMM/NOPB	VSSOP DGK	8 1000 208.0 191.0 35.0
LMC6482IMMX	VSSOP DGK	8 3500 367.0 367.0 35.0
LMC6482IMMX/NOPB	VSSOP DGK	8 3500 367.0 367.0 35.0
LMC6482IMX	SOIC D 8 2500 367.0 367.0 35.0
LMC6482IMX/NOPB SOIC	D 8 2500 367.0 367.0 35.0

TUBE

T - Tube height L - Tube length W-Tube width B - Alignment groove width

*All dimensions are nominal

Device	Package Name	Package Type	Pins	SPQ	L (mm)	W (mm)	T (μm)	B (mm)
LMC6482AIM D SOIC	8 95 495 8 4064 3.05
LMC6482AIM D SOIC	8 95 495 8 4064 3.05
LMC6482AIM/NOPB D SOIC	8 95 495 8 4064 3.05
LMC6482AIN/NOPB	P	PDIP	8	40	502	14	11938	4.32
LMC6482IM	D SOIC 8 95 495 8 4064 3.05
LMC6482IM	D SOIC 8 95 495 8 4064 3.05
LMC6482IM/NOPB	D SOIC 8 95 495 8 4064 3.05
LMC6482IN/NOPB	P	PDIP	8	40	502	14	11938	4.32

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061) [1.55] 1 8X (.024) [0.6] 6X (.050) [1.27] 4 (.213) [5.4] SYMM SEE DETAILS 8 SYMM (R.002) TYP [0.05]

LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X

METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND

NON SOLDER MASK DEFINED

SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND

SOLDER MASK DEFINED
SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061) [1.55] 1 8X (.024) [0.6] 6X (.050) [1.27] 4 (.213) [5.4] SYMM 8 SYMM (R.002) TYP [0.05]

SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X

4214825/C 02/2019

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE

0.400 (10,16) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) 0.045 (1,14) 0.045 (1,14) 0.030 (0,76) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) ⊕ 0.010 (0,25) M 0.325 (8,26) 0.300 (7,62) 0.015 (0,38) Gauge Plane 0.010 (0,25) NOM 0.430 (10,92) MAX 4040082/E 04/2010

NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 variation BA.

DGK (S-PDSO-G8)

PLASTIC SMALL-OUTLINE PACKAGE

4073329/E 05/06

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 per end.
D> Body width does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
E. Falls within JEDEC MO-187 variation AA, except interlead flash.

DGK (S-PDSO-G8)

Example Board Layout

(0,65)TYP. 8 5 PKG C (4,4) 1 4 PKG C Example Non Soldermask Defined Pad Example Solder Mask Opening (See Note E) (0,45) (1,45) Pad Geometry (See Note C) (0,05) All Around

Example Stencil Openings
Based on a stencil thickness of .127mm (.005inch).
(See Note D)

8X(0,45) 8X(1,45) (0,65)TYP. PKG C (4,4) PKG C

4221236/A 11/13

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate designs.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

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