MIC7400 - Voltage regulator Microchip - Free user manual and instructions

Product Type	Configurable PMIC (Power Management IC)
Number of Outputs	5 Buck Regulators + 1 Boost Regulator
Input Voltage Range	2.4V to 5.5V
Buck Output Voltage Range	0.8V to 3.3V (50 mV steps)
Boost Output Voltage Range	7V to 14V (200 mV steps)
Buck Output Current (per channel)	Up to 3A
Boost Output Current	Up to 200 mA
Quiescent Current (all regulators on)	200 μA typical
Buck Quiescent Current (per channel)	23 μA typical
Boost Quiescent Current	70 μA typical
Peak Buck Efficiency	93%
Typical Buck Efficiency at 1 mA	85%
Switching Frequency (Buck)	1.3 MHz (continuous mode)
Switching Frequency (Boost)	2.0 MHz
Control Interface	I²C up to 3.4 MHz
Package Type	36-Pin FQFN (4.5mm x 4.5mm x 0.85mm)
Solution Size (including external components)	15mm x 15mm x 1.25mm
Operating Junction Temperature	-40°C to +125°C
Protection Features	Thermal shutdown, overcurrent limit, output disconnect (boost)
Typical Applications	SSD, infotainment, handheld devices, security cameras, gaming machines

Frequently Asked Questions - MIC7400 Microchip

What is the input voltage range of the MIC7400?

The MIC7400 operates from an input voltage (PVIN and AVIN) of 2.4V to 5.5V.

How many output channels does the MIC7400 have?

It features five synchronous buck regulators and one boost regulator, providing up to six independent outputs.

Can I program the output voltages of the buck regulators?

Yes, each buck output can be programmed via I²C from 0.8V to 3.3V in 50 mV steps. The boost output is programmable from 7V to 14V in 200 mV steps.

What is the maximum output current per buck channel?

Each synchronous buck regulator can deliver up to 3A of continuous output current.

Does the MIC7400 support power sequencing?

Yes, it supports programmable power-up sequencing with up to 6 time slots and adjustable delays (0 ms to 7 ms per step).

How can I reduce power consumption in standby mode?

The device offers a standby mode where outputs can be disabled or set to lower voltages. The quiescent current is only 23 μA per buck and 70 μA for the boost in standby.

What protection features are built in?

It includes thermal shutdown, overcurrent protection (programmable current limit), and an output disconnect switch for the boost to protect against short circuits.

What is the typical efficiency of the buck regulators?

Peak efficiency reaches 93%, and at light loads (1 mA output), typical efficiency is 85%, thanks to HyperLight Load® mode.

What package is the MIC7400 available in?

It comes in a 36-lead FQFN package measuring 4.5mm x 4.5mm x 0.85mm with a 0.4mm pitch.

How do I configure the MIC7400 for my design?

Configuration is done via the I²C interface (up to 3.4 MHz). Internal EEPROM allows on-the-fly programmability of output voltages, sequencing, current limits, and more. Contact Microchip for custom default settings.

USER MANUAL MIC7400 Microchip

Configurable PMIC, Five Channel Buck Regulator Plus One Boost with HyperLight Load® and I²C Control

Features

• Input Voltage: 2.4V to 5.5V
• Five Independent Synchronous Bucks up to 3A
  • One Independent Non-Synchronous Boost 200 mA
  • 200 μA Quiescent Current (All Regulators On)
  • 93% Peak Buck Efficiency, 85% Typical Efficiency at 1 mA
• Dual Power Modes: Stand-by and Normal Mode
  • I²C Interface up to 3.4 MHz
• I²C On-the-Fly EEPROM Programmability, Featuring:
• Buck and Boost Output Voltage Scaling
• Power-on-Reset Threshold and Delay
• Power-Up Sequencing/Sequencing Delay
• Buck and Boost Current-Limit
• Buck and Boost Pull-Down when Disabled
• Individual ON, OFF, and Stand-by Modes
• Soft-Start and Global Power-Good Masking
  • 23 μA Buck Typical Quiescent Current
• 70 μA Boost Typical Quiescent Current
  • 1.5% Output Accuracy over Temperature/Line/Load
  • 2.0 MHz Boost Switching Frequency
  • 1.3 MHz Buck Operation in Continuous Mode
• Ultra-Fast Buck Transient Response
• 15 mm x 15 mm x 1.25 mm Solution Size
  • Thermal Shutdown and Current-Limit Protection
• 36-Pin 4.5 mm x 4.5 mm x 0.85 mm FQFN Package (0.4 mm Pitch)
• - 40 ^° C to + 125 ^° C Junction Temperature Range
• Client and Enterprise Solid State Drives (SSD)
• Consumer and In-Vehicle Infotainment Devices
• Multimedia Devices
• Portable Handheld Devices
• Security Cameras
• Gaming Machines
  • Service Provider Gateways

Applications

General Description

The MIC7400 is a powerful, highly integrated, configurable, power management IC (PMIC) featuring five synchronous buck regulators, one boost regulator and high-speed I²C interface with an internal EEPROM.

The device offers two distinct modes of operation—“stand-by mode” and “normal mode”—intended to provide an energy-optimized solution suitable for portable handheld, and infotainment applications.

In normal mode, the programmable switching converters can be configured to support a variety of features, including start-up sequencing, timing, soft-start ramp, output voltage levels, current-limit levels and output discharge for each channel.

In stand-by mode the PMIC can be configured in a low power state by either disabling an output or by changing the output voltage to another voltage level, either lower or higher than normal-mode. In general, it's assumed that the voltage in standby mode is lower than the one in normal mode. Independent exit from stand-by mode can be achieved either by I²C communication or the external STBY pin.

The device has five synchronous buck regulators with high-speed adaptive on-time control supporting even the challenging ultra-fast transient requirement for Core supplies. One boost regulator provides a flash memory programming supply that delivers up to 200 mA of output current. The boost is equipped with an output disconnect switch that opens if a short-to-ground fault is detected.

An internal EEPROM enables a single-chip solution across many platforms by allowing the designer to customize the PMIC for their design. Modifications can be made without the need to re-approve a new PMIC, saving valuable design resources and time.

All switchers provide light load efficiency with HyperLight Load ^® mode for buck and PFM mode for boost. An additional benefit of this proprietary architecture is very low output ripple voltage throughout the entire load range with the use of small output capacitors. The MIC7400 is designed for use with a small inductors (down to 0.47 µ H for buck, 1.5 µ H for boost), and an output capacitor as small as 10 µ F for buck, enabling a total solution size of 15 mm x 15 mm and less than 1 mm height.

Typical Application Circuit

Block Diagram

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Supply Voltages (PVIN[1-6])	-0.3V to +6V
Analog Supply Voltage (AVIN)	-0.3V to +6V
Buck Output Voltages (VOUT[1-5])	-0.3V to +6V
Boost Output Voltage (VOUT6)	-0.3V to +20V
Buck Switch Voltages (VSW[1-5])	-0.3V to +6V
Boost Switch Voltage (VSW6)	-0.3V to +20V
Power Good Voltage (VPG)	-0.3V to AVIN
Power-On Reset Output (VPOR)	-0.3V to +6V
POR Threshold Voltage (VVSLT)	-0.3V to +6V
Standby Voltage (VSTBY)	-0.3V to +6V
I2C IO (VSDA, VSCL)	-0.3V to AVIN
AGND to PGND[1-6]	-0.3V to +0.3V
ESD Rating (Note 1)	HBM: 2 kV; MM: 200V

Operating Ratings ‡

Input Voltage (PVIN[1-6])	+2.4V to +5.5V
Analog Input Voltage (AVIN)	+2.4V to +5.5V
Buck Output Voltage Range (VOUT[1-5])	+0.8V to +3.3V
Boost Output Voltage Range (VOUT6)	+7V to +14V
Power Good Voltage (VPG)	0V to AVIN
Power-On Reset Output (VPOR)	0V to AVIN
POR Threshold Voltage (VVSLT)	0V to AVIN
Standby Voltage (VSTBY)	0V to AVIN
I2C IO (VSDA, VSCL)	0V to AVIN

† Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. Specifications are for packaged product only.
‡ Notice: The device is not guaranteed to function outside its operating ratings.

Note 1: Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5 kΩ in series with 100 pF.

TABLE 1-1: ELECTRICAL CHARACTERISTICS
Electrical Characteristics: V_IN = AV_IN = PV_IN(1-6) = 5.0V ; V_OUT1 = 1.8V ; V_OUT2 = 1.1V ; V_OUT3 = 1.8V ; V_OUT4 = 1.05V ; V_OUT5 = 1.25V ; V_OUT6 = 12V . T_A = +25°C , unless otherwise noted. Bold values indicate -40°C ≤ T_J ≤ +125°C . Note 1

Parameter Min. Typ. Max. Units Conditions
Input Supply (VIN)
Input Voltage Range (AVIN, PVIN[1-6]) 2.4	5.5 V	—
Operating Quiescent Current into AVIN(Note 2, Note 3)	—	2	0	0	2
Operating Quiescent Current into PVIN(Note 2)	—	0.3	1.0	μA	VIN=5.0V; IOUT=0A μ A
Undervoltage Lockout Threshold	2.15	2.25	2.35	V	AVIN Rising
Undervoltage Lockout Hysteresis	—	150	—	mV	—
Standby Input (STBY)
Logic Level High	1.2	—	—	V	—
Logic Level Low	—	—	0.4	V	—
Bias Current into Pin	—	—	200	nA	VSTBY=VIN
Bias Current out of Pin	—	—	200	nA	VSTBY=0V
Rising/Falling Edge Reset Deglitch	—	100	—	μs	—
POR Threshold Input (VSLT)
Logic Level High	1.2	—	—		—
Logic Level Low	—	—	0.4		—
Bias Current Into Pin	—	—	200		VVSLT=VIN
Bias Current Out of Pin	—	—	200		VVSLT=0V
Power-On-Reset (POR) Comparator
POR Upper Comparator Range	2.646	2.7	2.754	V	AVIN Rising, VVSLT=0V
POR Lower Comparator Range	2.548	2.6	2.652	V	AVIN Falling, VVSLT=0V
POR Upper Comparator Range	3.626	3.7	3.774	V	AVIN Rising, VVSLT=VIN
POR Lower Comparator Range	3.528	3.6	3.672	V	AVIN Falling, VVSLT=VIN
Power Reset Output (POR) and Timer
POR Delay	18	20	22	ms	—
POR Deglitch Delay	—	50	—	μs	AVIN Falling
POR Output Low Voltage	—	75	400	mV	IPOR=10 mA (sinking)
POR Leakage Current	—	—	200	nA	VPOR=5.5V
Global Power Good Output (PG)
Buck Power Good Threshold Voltage	87	91	95	%VOUT	VOUT[1-5] Rising
Buck Hysteresis (Note 4)	—	4	—	%VOUT	VOUT[1-5] Falling
Boost Power Good Threshold Voltage	87	91	95	%VOUT	VOUT[6] Rising
Boost Hysteresis (Note 4)	—	380	—	mV	VOUT[6] Falling
Power Good Output Low Voltage	—	75	400	mV	IPG=10 mA (sinking)
Power Good Leakage Current	—	0.01	200	nA	VPG=5.5V
Power Good Deglitch Delay	—	100	—	μs	VOUT[1-6] Falling
Output Sequencing Delay (Note 4)	0.96	1	1.04	ms	—
Thermal Protection
Thermal Shutdown	—	160	—	°C	TJ Rising
Thermal Hysteresis	—	20	—	°C	—
Parameter	Min.	Typ.	Max.	Units	Conditions
Synchronous Buck (VOUT1 - VOUT5)Buck Output Voltage Accuracy (OUT[1-5])
Typical Output Voltage 1 Accuracy (Note 5)	-1.5	—	1.5	%	Includes Load, Line, and Reference
Typical Output Voltage 2 Accuracy (Note 5)	-1.5	—	1.5	%	Includes Load, Line, and Reference
Typical Output Voltage 3 Accuracy (Note 5)	-1.5	—	1.5	%	Includes Load, Line, and Reference
Typical Output Voltage 4 Accuracy (Note 5)	-1.5	—	1.5	%	Includes Load, Line, and Reference
Typical Output Voltage 5 Accuracy (Note 5)	-1.5	—	1.5	%	Includes Load, Line, and Reference
Output Voltage 1 Accuracy (Note 5)	-1	—	1	%	—
Output Voltage 2 Accuracy (Note 5)	-1	—	1	%	—
Output Voltage 3 Accuracy (Note 5)	-1	—	1	%	—
Output Voltage 4 Accuracy (Note 5)	-1	—	1	%	—
Output Voltage 5 Accuracy (Note 5)	-1	—	1	%	—
Load Regulation — 0.1 — % I					OUT = 10 mA to IOUT(MAX)
Line Regulation — 0.05 — % V					IN = 3.3V to 5.0V
Buck Soft-Start
Soft-Start (1-5) LSB (Note 4, Note 6)	3.84	4.0	4.16	μs/step	—
Buck Internal MOSFETs
High-Side On-Resistance	—	54	—	mΩ	VIN = 3.3V; ISW[1-5] = 200 mA
High-Side On-Resistance	—	40	—	mΩ	VIN = 5.0V; ISW[1-5] = 200 mA
Low-Side On-Resistance	—	37	—	mΩ	VIN = 3.3V; ISW[1-5] = -200 mA
Low-Side On-Resistance	—	30	—	mΩ	VIN = 5.0V; ISW[1-5] = -200 mA
Output Pull-Down Resistance	75	90	200	Ω	VSW[1-5] = 0V
Buck Controller Timing
Fixed On-Time (Note 7)	—	220	—	ns	VIN = 3.3; VOUT = 1.0V; IOUT = 1.0A
Minimum OFF-Time	— 80	—	ns	—
Buck Current-Limit (OUT1 - OUT5)
Buck 1 Current-Limit Threshold	3.075	4.1	5.125	A	See Table 4-3 for IPROG Settings
Buck 2 Current-Limit Threshold	3.075	4.1	5.125	A	See Table 4-3 for IPROG Settings
Buck 3 Current-Limit Threshold	3.075	4.1	5.125	A	See Table 4-3 for IPROG Settings
Buck 4 Current-Limit Threshold	4.88	6.1	7.32	A	See Table 4-3 for IPROG Settings
Buck 5 Current-Limit Threshold	3.075	4.1	5.125	A	See Table 4-3 for IPROG Settings
Gross High-Side Current-Limit [1-5]	—	150	—	%	With Respect to Buck [x]Current-Limit
Zero Cross Threshold	—	0	—	mV	Zero crossing detector
Boost (VOUT6)Boost Output Voltage (VOUT6)
Typical Output Voltage Accuracy (Note 5)	-1.5	—	1.5	%	Includes Load, Line, and Reference
Output Voltage Accuracy (Note 5)	-1	—	1	%	—
Load Regulation — 0.2 — % I					OUT6 = 1.0 mA to 200 mA
Line Regulation — 0.2 — % V					IN = 2.4V to 5.5V; IOUT6 = 10 mA
VOUT6 Discharge Current	111	148	185	mA	VIN = 3.3V; VOUT6 = 12V
Boost Soft-Start Step Duration
Soft-Start 6 LSB (Note 4, Note 6)	3.84	4.0	4.16	μs/step	—
Boost Internal MOSFETs
Low-Side On-Resistance	—	160	—	mΩ	VIN = 3.3V; ISW1 = -100 mA
Low-Side On-Resistance	—	140	—	mΩ	VIN = 5.0V; ISW1 = -100 mA
Boost Disconnect MOSFETs
Disconnect Switch On-Resistance	—	90	—	mΩ	IPVIN6O = 100 mA; VIN = 3.3V
Disconnect Switch Current-Limit	—	5	—	A	—
Boost Switching Frequency
Switching Frequency (PWM Mode)	1.92	2.0	2.08	MHz	—
Minimum Duty Cycle	35	40	45	%	—
Maximum Duty Cycle	80	85	90	%	—
Boost Current-Limit
NMOS Current-Limit Threshold	—	2.24	—	A	—
I2C InterfaceI2C Interface (SCL, SDA)
Low Level Input Voltage	—	—	0.4	V	—
High Level Input Voltage	1.2	—	—	V	—
Low Level Input Current	-200	0.01	200	nA	—
High Level Input Current	-200	0.01	200	nA	—
SDA Pull-Down Resistance	—	20	—	Ω	—
SDA Logic 0 Output Voltage	—	—	0.4	V	ISDA = 3 mA
CLK, DATA Pin Capacitance	— 0.7	—	pF	—
I2C Interface Timing (Note 4)
SCL Clock Frequency	—	—	100	kHz	Standard Mode
	—	—	400	kHz	Fast Mode
	—	—	3.4	MHz	High Speed Mode (Note 4)

Note 1: Specifications are for packaged product only.
2: Tested in a non-switching configuration.
3: When all outputs are configured to the minimum programmable voltage.
4: Guaranteed by design.
5: Not tested in a closed loop configuration.
6: The soft-start time is calculated using the following equation: t_softstart = [(V_OUTPROGRAM - 0.15)/0.05 + 1) × t_RAMP .
7: Buck frequency is calculated using the following equation f_SW = (V_OUT / V_IN) × (1 / t_ON) .

TEMPERATURE SPECIFICATIONS (Note 1)

Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Junction Operating Temperature Range	TJ	-40 —	+125 °C —
Ambient Storage Temperature Range T	S	-40 —	+150 °C —
Package Thermal Resistance
Thermal Resistance FQFN-36Ld θ	JA	—	3	0	—	° C /

Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., T_A , T_J , θ_JA ). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability.

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

FIGURE 2-1: Buck Efficiency (LDCR = 0 m Ω) vs. Output Current.

FIGURE 2-4: Buck Efficiency (LDCR = 40 mΩ) vs. Output Current.

FIGURE 2-2: Buck Efficiency (LDCR = 0 m Ω) vs. Output Current.

FIGURE 2-5: Buck Efficiency (LDCR = 40 mΩ) vs. Output Current.

FIGURE 2-3: Boost Efficiency (12V) vs. Output Current.

FIGURE 2-6: Output Voltage vs. Output Current.

FIGURE 2-7: Buck Efficiency (LDCR = 116 mΩ) vs. Output Current.

FIGURE 2-10: Buck Output Voltage (1.0V) vs. Output Current.

FIGURE 2-8: Buck Efficiency (LDCR = 116 mΩ) vs. Output Current.

FIGURE 2-11: Buck Output Voltage Regulator vs. Output Current.

FIGURE 2-9: Output Voltage vs. Temperature.

FIGURE 2-12: Buck Line Regulation vs. Input Voltage.

FIGURE 2-13: Dropout Output Voltage vs. Output Current.

FIGURE 2-16: Current-Limit Threshold vs. Output Voltage.

FIGURE 2-14: V IN Operating Supply Current vs. Input Voltage.

FIGURE 2-17: Output Current-Limit vs. Output Voltage.

FIGURE 2-15: Buck 2 Switching Frequency vs. Input Voltage.

FIGURE 2-18: Programmed Current-Limit vs. Measured Current-Limit.

FIGURE 2-19: Hot Plug – Rising V IN

FIGURE 2-21: Unplug – Falling V IN

FIGURE 2-20: POR Timing.

FIGURE 2-22: STBY Delay.

FIGURE 2-23: Buck Soft-Start.

FIGURE 2-26: POR Delay.

FIGURE 2-24: Boost Soft-Start.

FIGURE 2-27: Output Pull-Down Resistance.

FIGURE 2-25: Standard Delay.

FIGURE 2-28: Buck 2 Load Transient – 10 mA to 1A.

FIGURE 2-29: Buck 4 Load Transient – 10 mA to 3A.

FIGURE 2-32: Buck 2 Load Transient – 10 mA to 0.2A.

FIGURE 2-30: Buck 2 Load Transient – 200 mA to 1A.

FIGURE 2-33: Buck 4 Load Transient – 10 mA to 0.5A.

FIGURE 2-31: Buck 4 Load Transient – 0.5A to 3A.

FIGURE 2-34: Boost 6 Load Transient – 10 mA to 200 mA.

FIGURE 2-35: Boost 6 Load Transient – 10 mA to 50 mA.

FIGURE 2-38: Cross Regulation.

FIGURE 2-36: Buck 4 Line Transient – 3.3V to 5.0V.

FIGURE 2-39: Buck 2 PWM Switching Waveforms.

FIGURE 2-37: Boost 6 Line Transient – 3.3V to 5.0V.

FIGURE 2-40: Buck 2 PFM Switching Waveforms.

FIGURE 2-41: Buck 4 PWM Switching Waveforms.

FIGURE 2-44: Boost 6 PFM Switching Waveforms.

FIGURE 2-42: Buck 4 PFM Switching Waveforms.

FIGURE 2-45: Input Supply Inrush Current - No Load.

FIGURE 2-43: Boost 6 PWM Switching Waveforms.

FIGURE 2-46: Input Supply Inrush Current – Loaded.

FIGURE 2-48: Rising Edge Trigger Standby.

FIGURE 2-47: Falling Edge Trigger Standby (DEFAULT).

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

FIGURE 3-1: MIC7400 Pin Configuration.

TABLE 3-1: PIN FUNCTION TABLE

Pin Number	Pin Name	Description
1	SW2	Switch Pin 2 (Output): Inductor connection for the synchronous step-down regulator. Connect the inductor between the output capacitor and the SW2 pin.
2 PVIN2		Power Supply Voltage 2 (Input): Input supply to the source of the internal high-side P-channel MOSFET. An input capacitor between PVIN2 and the power ground PGND2 pin is required and should be placed as close as possible to the IC.
3	O	Output Voltage Sense 2 (Input): This pin is used to sense the output voltage. Connect OUT2 as close to the output capacitor as possible to sense output voltage. Also provides the path to discharge the output through an internal 90Ω resistor when disabled. This pull-down feature is programmed through the PULLD[x] register.
4 PVIN3		Power Supply Voltage 3 (Input): Input supply to the source of the internal high-side P-channel MOSFET. An input capacitor between PVIN3 and the power ground PGND3 pin is required and should be placed as close as possible to the IC.
5	SW3	Switch Pin 3 (Output): Inductor connection for the synchronous step-down regulator. Connect the inductor between the output capacitor and the SW3 pin.
6	P	Power Ground 3: The power ground for the synchronous buck converter power stage. The PGND pin connects to the sources of the internal low-side N-Channel MOSFET, the negative terminals of input capacitors, and the negative terminals of output capacitors.
7	O	Output Voltage Sense 3 (Input): This pin is used to sense the output voltage. Connect OUT3 as close to the output capacitor as possible to sense output voltage. Also provides the path to discharge the output through an internal 90Ω resistor when disabled. This pull-down feature is programmed through the PULLD[x] register.
8 PVIN4		Power Supply Voltage 4 (Input): Input supply to the source of the internal high-side P-channel MOSFET. An input capacitor between PVIN4 and the power ground PGND4 pin is required and to be placed as close as possible to the IC.
9	SW4	Switch Pin 4 (Output): Inductor connection for the synchronous step-down regulator. Connect the inductor between the output capacitor and the SW4 pin.

TABLE 3-1: PIN FUNCTION TABLE (CONTINUED)

Pin Number	Pin Name Description
10 PGND4
11 OUT4
12 STBY
13 SDA
14 AGND
15 SCL
16 POR
17 OUT5
18 PGND5
19 SW5
20 PVIN5
21 OUT6
22 PGND6
23 SW6

TABLE 3-1: PIN FUNCTION TABLE (CONTINUED)

Pin Number	Pin Name	Description
24 PVIN6O		Power Supply Voltage 6 (Output): This pin is the output of the power disconnect switch for the boost regulator. When the boost regulator is on, an internal switch provides a current path for the boost inductor. In shutdown, an internal P-channel MOSFET is turned off and disconnects the boost output from the input supply. This feature eliminates current draw from the input supply during shutdown. An input capacitor between PVIN6O and the power ground PGND6 pin is required and place as close as possible to the IC.
25 PVIN6	Power Supply Voltage 6 (Input): Input supply to the internal disconnect switch.
26 PVIN1		Power Supply Voltage 1 (Input): Input supply to the source of the internal high-side P-channel MOSFET. An input capacitor between PVIN1 and the power ground PGND1 pin is required and should be placed as close as possible to the IC.
27 SW1		Switch Pin 1 (Output): Inductor connection for the synchronous step-down regulator. Connect the inductor between the output capacitor and the SW1 pin.
28 PGND1		Power Ground 1: The power ground for the synchronous buck converter power stage. The PGND pin connects to the source of the internal low-side N-Channel MOSFET, the negative terminals of input capacitors, and the negative terminals of output capacitors.
29 OUT1		Output Voltage Sense 1 (Input): This pin is used to sense the output voltage remotely. Connect OUT1 as close to output capacitor as possible to sense output voltage. This feature also provides the path to discharge the output through an internal 90Ω resistor when disabled. The pull-down feature is programmed through the PULLD[x] register.
30 VSLT		POR Selection Threshold (Input): A high on this pin sets the PORUP and PORDN registers to their upper threshold limits and a low to their lower threshold limits. Do not leave floating.
31 AVIN		Analog Voltage Supply (Input): The start-up sequence begins as soon as the AVIN pin voltage rises above the IC's UVLO upper threshold. The outputs do not turn off until AVIN pin voltage falls below the lower threshold limit. A 2.2 μF ceramic capacitor from the AVIN pin to AGND pin must be placed next to the IC.
32 AGND		Analog Ground: Internal signal ground for all low power circuits. Connect directly to the layer 2 ground plane. Layer 2 is the point where all the PGNDs and AGND are connected. Do not connect PGND and AGND together on the top layer.
33 NC No Connect. Must be left floating.
34 NC No Connect. Must be left floating.
35 PG		Global Power Good (Output): This is an open-drain output that is pulled high when all the regulator power good flags are high. If an output falls below the power good threshold or a thermal fault occurs, the global power good flag is pulled low. There is a falling edge de-glitch time of 50 μs to prevent false triggering on output voltage transients. A power good mask feature programmed through the PGOOD_MASK[x] registers can be used to ignore a power good fault. When masked an individual power good fault will not cause the global power good output to de-assert. Do not connect the power good pull-up resistor to a voltage higher than AVIN.
36 PGND2		Power Ground 2: The power ground for the synchronous buck converter power stage. The PGND pin connects to the source of the internal low-side N-Channel MOSFET, the negative terminals of input capacitors, and the negative terminals of output capacitors.
EP ePAD	Exposed Pad: Must be connected to the GND plane for full output power to be realized.

4.0 FUNCTIONAL DESCRIPTION

The MIC7400 is one of the industry's most-advanced PMIC designed for solid state drives (SSD) on the market today. It is a multi-channel solution that offers software-configurable soft-start, sequencing, and digital voltage control (DVC) that minimizes PC board area. These features usually require a pin for programming. However, this approach makes the IC larger by increasing pin count, and also increases BOM cost due to the external components.

The following is a complete list of programmable features:

• Buck output voltage (0.8V – 3.3V/50 mV steps)
• Boost output voltage (7.0V – 14V/ 200 mV steps)
  • Power-on-reset (2.25V – 4.25V/50 mV steps)
• Power-on-reset delay (5 ms – 160 ms/5 ms steps)
  • Power-up sequencing (6 time slots)
• Power-up sequencing delay (0 ms – 7 ms/1 ms steps)
• Soft-start (4 μs – 1024 μs per step)
• Buck current limit threshold - (1.1A to 6.1A/0.5A steps)
• Boost current limit threshold - (1.76A to 2.6A/0.12A steps)
• Boost pull-down (37 mA to 148 mA/37 mA steps)
• Buck pull-down (90Ω)
• Buck standby output voltage programmable
• Buck standby programmable standby current limit
• Boost standby output voltage programmable
• Boost standby programmable standby current limit
  • Global power good masking

These features give the system designer the flexibility to customize the MIC7400 for their application. For example, V_OUT1 current-limit can be programmed to 4.1A and V_OUT2 can be set to 1.1A. These outputs can be programmed to come up at the same time or 2.0 ms apart. In addition, in power-saving standby mode, the outputs can either be turned off or programmed to a lower voltage. With this programmability, the MIC7400 can be used in multiple platforms.

The MIC7400 buck regulators are adaptive on-time synchronous step-down DC-to-DC regulators. They are designed to operate over a wide input voltage range from 2.4V to 5.5V and provide a regulated output voltage at up to 3.0A of output current. An adaptive on-time control scheme is employed to obtain a constant switching frequency and to simplify the control compensation. The device includes an internal soft-start function which reduces the power supply input surge current at start-up by controlling the output voltage rise time.

The MIC7400 has a current-mode boost regulator that can deliver up to 200 mA of output current and only consumes 70 µ A of quiescent current. The 2.0 MHz switching frequency allows small chip inductors to be used. Programmable overcurrent sensing protects the boost from overloads and an output disconnect switch opens to protect against a short-circuit condition. Soft-start is also programmable and controls both the rising and falling output.

4.1 Programmable Buck Soft-Start Control

The MIC7400 soft-start feature forces the output voltage to rise gradually, which limits the inrush current during start-up. A slower output rise time will draw a lower input surge current. The soft-start time is based on the least significant bit (LSB) of an internal DAC and the speed of the ramp rate, as shown in Figure 4-1. This illustrates the soft-start waveform for all five synchronous buck converters. The initial step starts at 150 mV and each subsequent step is 50 mV.

FIGURE 4-1: Buck Soft-Start.

The output ramp rate ( t_RAMP ) is set by the soft-start registers. Each output ramp rate can be individually set from 4 µ s to 1024 µ s, see Table 4-1 for details.

The soft-start time t_SS can be calculated by Equation 4-1:

EQUATION 4-1:

t _ SS ( V _ OUT - 0 . 1 5 V5 0 mV) × ≠_ RAMP

Where:

t _ SS = Output rise time .

V _ OUT = Output voltage .

t _ RAMP = Output dwell time .

For example:

EQUATION 4-2:

t _ SS (1 . 8 V 0 . 1 5 V -/5 0 mV) 8 µs × =

t _ SS = 2 6 4 µs

Where:

V _ OUT = 1. 8 V

t _ RAMP = 8. 0 µs

TABLE 4-1: BUCK OUTPUTS DEFAULT SOFT-START TIME (DEFAULT)

—	VOUT	tRAMP	tSS
VOUT1	1.8V 8 μs	264 μs
VOUT2	1.1V 8 μs	152 μs
VOUT3	1.8V 8 μs	264 μs
VOUT4	1.05V 8 μs	144 μs
VOUT5	1.25V 8 μs	176 μs

Figure 4-2 shows the output of Buck 1 ramping up cleanly, starting from 0.15V to its final 1.1V value.

FIGURE 4-2: Buck Soft-Start.

4.2 Buck Digital Voltage Control (DVC)

The output voltage has a 6-bit control DAC that can be programmed from 0.8V to 3.3V in 50 mV increments. If the output is programmed to a higher voltage, then the output ramps up, as shown in Figure 4-3.

FIGURE 4-3: Buck DVC Control Ramp.

The ramp time is determined by Equation 4-3:

EQUATION 4-3:

Δt = ( V _ OUT - V _ OUT _ INIT5 0 mV) × t _ RAMP

Where:

V_OUTINIT = Initial output voltage.

V_OUT^-=Final output voltage.

t_RAMP = Output\ dwell\ time.

When the regulator is programmed to a lower voltage, then the output voltage ramps down at a rate determined by the output ramp rate ( t_RAMP ), the output capacitance and the external load. Small loads result in slow output voltage decay and heavy loads cause the decay to be controlled by the DAC ramp rate.

In Figure 4-4, V_OUT1 is switched to stand-by mode with an I²C command and then switched back to normal mode either by an I²C command or a low-to-high transition of the STBY pin. In this case, the rise and fall times are the same due to a 1A load on V_OUT1 .

FIGURE 4-4: Buck DVC Control Ramp.

4.3 Programmable Boost Soft-Start Control

The boost soft-start time is divided into two parts as shown in Figure 4-5. T1 is a fixed 367 µs delay starting from when the internal enable goes high. This delay gives enough time for the disconnect switch to turn on and bring the inductor voltage to VIN before the boost is turned on. There is a 50 µs delay that is controlled by the parasitic capacitance (CGD) of the disconnect switch before the output starts to rise.

After the T1 period, the DAC output ramp starts, T2. The total soft-start time, t_SS , is the sum of both periods. Figure 4-6 displays the actual boost soft-start waveform.

FIGURE 4-5: Boost Soft-Start Ramp.

FIGURE 4-6: Boost Soft-Start.

EQUATION 4-4:

t _ SS T 1 T 2 + =

T 2 ( V _ OUT - 1 . 4 V0 . 2 V) × ≠_ RAMP

T 2 = (1 2 V 1 . 4 V -/0 . 2 V) × 1 6 µs

Where:

T 1 = 3 6 7 µs

T 2 = 8 4 8 µs

t _ SS = 3 6 7 µs + 8 4 8 µs = 1. 2 1 5 ms

V _ OUT = Output voltage .

t _ RAMP = Output dwell time = 1 6 µs.

4.4 Boost Digital Voltage Control (DVC)

The boost output control works the same way as the buck, except that the voltage steps are 200 mV, see Figure 4-7. When the boost is programmed to a lower voltage the output ramps down at a rate determined by the output ramp rate ( t_RAMP ), the output capacitance and the external load. During both the ramp up and down time, the power good output is blanked and if the power good mask bit is set to "1".

FIGURE 4-7: Boost DVC Control Ramp.

The ramp time can be computed using the following equation:

EQUATION 4-5:

t Δ ( V _ OUT - V _ OUT _ INIT0 . 2 V) × ≠_ RAMP

Where:

V _ OUT _ INIT = Initial output voltage .

TABLE 4-2: BOOST OUTPUT DEFAULT SOFT-START TIME

—	VOUT	tRAMP	tSS
VOUT6	12V 16 μs	1.215 ms

4.5 Buck Current-Limit

The MIC7400 buck regulators have high-side current-limiting that can be varied by a 4-bit code. If the regulator remains in current-limit for more than seven consecutive PWM cycles, the output is latched off, the overcurrent status register bit is set to 1, the power-good status register bit is set to 0 and the global power good (PG) output pin is pulled low. An overcurrent fault on one output will not disable the remaining outputs. Table 4-3 shows the current-limit register settings verses output current. The current-limit register setting is set at twice the maximum output current.

TABLE 4-3: BUCK CURRENT-LIMIT REGISTER SETTINGS

IOUT(MAX)	IPROG	BINARY HEX
0.5A 1.1A	1111 F'h
1.0A 2.1A	1101	D'h
1.5A 3.1A	1011	B'h
2.0A 4.1A	1001	9'h
2.5A 5.1A	0111 7'h
3.0A 6.1A	0101	5'h

The output can be turned back on by recycling the input power or by software control. To clear the overcurrent fault by software control, set the enable register bit to "0" then clear the overcurrent fault by setting the fault register bit to "0". This will clear the overcurrent and power good status registers. Now the output can be re-enabled by setting the enable register bit to "1".

During start-up sequencing, once an overcurrent condition is sensed, the fault register is set to "1" and the start-up sequence will stop and no further outputs will be enabled. See Figure 4-9 for default start-up sequence.

4.6 Boost Current-Limit

The boost current-limit features cycle-by-cycle protection. The duty cycle is cut immediately once the current-limit is hit. When the boost current-limit is hit for five consecutive cycles, the FAULT signal is asserted and remains asserted with the boost converter keeping on running until the boost is powered off.

This protects the boost in normal overload conditions, but not in a short-to-ground case. For a short-circuit to ground, the boost current-limit will not be able to limit the inductor current. This short-circuit condition is sensed by the current in the disconnect switch. When the disconnect switch current limit is hit for four consecutive master clock cycles (2 MHz), regardless if the boost is switching or not, both the disconnect switch and boost are latched off automatically and the FAULT signal is asserted.

The output can be turned back on by recycling the input power or by software control. To clear the overcurrent fault by software control, set the enable register bit to "0" then clear the overcurrent fault by setting the fault register bit to "0".

4.7 Global Power Good Pin

The global power-good output indicates that all the outputs are above the 91% limit after the power-up sequence is completed. Once the power-up sequence is complete, the global power good output stays high unless an output falls below its power-good limit, a thermal fault occurs, the input voltage drops below the lower UVLO threshold or an output is turned OFF by setting the enable register bit to "0" unless the PGOOD_MASK[x] bit is set to "1" (Default).

A power-good mask bit can be used to control the global power good output. The power-good mask feature is programmed through the PGOOD_MASK[x] registers and is used to ignore an individual power-good fault. When masked, PGOOD_MASK[x] bit is set to "1", an individual power good fault will not cause the global power good output to de-assert.

If all the PGOOD_MASK[x] bits are set to "1", then the power good output de-asserts as soon as the first output starts to rise. The PGOOD_MASK[x] bit of the last output must be set to "0" to have the PG output stay low until the last output reaches 91% of its final value.

The global power-good output is an open-drain output. A pull-up resistor can be connected to V_IN or V_OUT . Do not connect the pull-up resistor to a voltage higher than AV_IN .

4.8 Standard Delay

There is a programmable timer that is used to set the standard delay time between each time slot. The timer starts as soon as the previous time slot's output power good goes high. When the delay completes, the regulators assigned to that time slot are enabled, see Figure 4-8.

FIGURE 4-8: Standard Delay Time.

4.9 Power-Up Sequencing

When power is first applied to the MIC7400, all I ² C registers are loaded with their default values from the EEPROM. There is about a 1.5 ms delay before the first regulator is enabled while the MIC7400 goes through the initialization process. The DELAY register's STDEL bits set the delay between powering up each regulator at initial power up.

The sequencing registers allow the outputs to come up in any order. There are six time slots that an output can be configured to power up in. Each time slot can be programmed for up to six regulators to be turned on at once or none at all.

Figure 4-9 shows an example of this feature. V_OUT4 is enabled in time slot 1. After a 1 ms delay, V_OUT2 and V_OUT3 are enabled at the same time in time slot 2. The 1 ms is the standard delay for all of the outputs and can be programmed from 0 ms to 7 ms in 1 ms steps. Next, V_OUT1 is powered up in time slot 3 and V_OUT5 in time slot 4. There are no regulators programmed for time slot 5. Finally, V_OUT6 is powered up in time slot 6. The global power good output, V_PG , goes high as soon as the last output reaches 91% of its final value.

FIGURE 4-9: Hot Plug - V IN Rising.

4.10 VSLT Pin

The power-on-reset threshold toggles between two different ranges by driving the VSLT pin high or low. The lower range of 2.25V to 3.25V is selected when the VSLT pin is tied to ground. The upper range, 3.25V to 4.25V, is selected when the VSLT pin is tied to V_IN .

4.11 Programmable Power-on-Reset (POR) Delay

The POR output pin provides the user with a way to let the SOC know that the input power is failing. If the input voltage falls below the power-on reset lower threshold level, the POR output immediately goes low. The lower threshold is set in the PORDN register and the upper threshold uses PORUP register.

The low-to-high POR transition can be delayed from 5 ms to 160 ms in 5 ms increments. This feature can be used to signal the SOC that the power supplies are stable. The PORDEL register sets the delay of the POR pin. The POR delay starts as soon as the AVIN pin voltage rises above the power-on reset upper threshold limit. Figure 4-10 shows the POR operation.

FIGURE 4-10: POR.

4.12 Power-Down Sequencing

When power is removed from V_IN , all the regulators try to maintain the output voltage until the input voltage falls below the UVLO limit of 2.35V as shown in Figure 4-11.

FIGURE 4-11: Hot Unplug - V IN Falling.

4.13 Stand-By Mode

In stand-by mode, efficiency can be improved by lowering the output voltage to the standby mode value or turning an output off completely. There are two registers used for setting the output voltage, normal-mode register and stand-by mode register. The default power-up voltages are set in the normal-mode registers.

An I ² C write command to the STBY_CTRL_REG register or the STBY pin can be used to set the MIC7400 into stand-by mode. Figure 4-12 shows an I ² C write command implementation. In stand-by mode, the output can be programmed to a lower voltage or turned completely off. When disabled, the output will be soft-discharged to zero if the PULLD[1-6] register are set to 1. If PULLD[x] = 0 the output drifts to PGND at a rate determined by the load current and output capacitance.

In stand-by, if an output is disabled, the global power good output is not affected when the PGOOD_MASK[x] is set to logic 1. If the PGOOD_MASK[x] is set to logic 0, then the global power good flag is pulled low. In Figure 4-12, all the PGOOD_MASK[x] bits are set to logic 1.

FIGURE 4-12: I ² C Stand-by Mode.

4.14 Resistive Discharge

To ensure a known output condition in stand-by mode, the output is actively discharged to ground if the output is disabled. Setting the buck pull down register field PULLD[1-5] = 1 connects a 90Ω pull down resistor from OUT[x] to PGND[x] when the MIC7400 is disabled. If PULLD[x] = 0 the output drifts to PGND at a rate determined by the load current and the output capacitance value. The boost has a programmable pull-down current level from 37 mA to 148 mA. In Figure 4-13, the top trace shows the normal pull down and the bottom trace is with the 90Ω pull-down.

FIGURE 4-13: Output Pull-Down Resistance.

4.15 STBY Pin

A pin-selectable STBY input allows the MIC7400 to be placed into standby or normal mode. In standby mode, the individual regulator can be turned on or off or the output voltage can be set to a different value. If the regulators are turned off, standby mode cuts the quiescent current by 23 µ A for each buck regulator and 70 µ A for the boost.

Figure 4-14 illustrates the STBY pin operation. A low-to-high transition on the STBY pin switches the output from standby mode to normal mode. There is a 100 µs STBY de-glitch time to eliminate nuisance tripping then all the regulators are enabled at the same time and ramp up with their programmed ramp rates. A high-to-low transition on the STBY pin switches the output from normal mode to standby mode.

FIGURE 4-14: STBY-to-NORMAL Transition (DEFAULT).

4.16 Safe Start-Up into a Pre-Biased Output

The MIC7400 is designed for safe start-up into a pre-biased output. This prevents large negative inductor currents that can cause the output voltage to dip and excessive output voltage oscillations. A zero crossing comparator is used to detect a negative inductor current. If a negative inductor current is detected, the low-side synchronous MOSFET functions as a diode and is immediately turned off.

Figure 4-15 shows a 1V output pre-bias at 0.5V at start-up, see V_OUT4 trace. The inductor current, trace I_L4 , is not allowed to go negative by more than 0.5A before the low-side switch is turned off. This feature prevents high negative inductor current flow in a pre-bias condition which can damage the IC.

FIGURE 4-15: Pre-Biased Output Voltage.

4.17 Buck Regulator Power Dissipation

The total power dissipation in a MIC7400 is a combination of the five buck regulators and the boost dissipation. The buck regulators (OUT1 to OUT5) dissipation is approximately the switcher's input power minus the switcher's output power and minus the power loss in the inductor:

EQUATION 4-6:

P _ D _ BUCK V _ IN I _ IN V _ OUT I _ OUT - P _ L LOSS

While the boost power dissipation is estimated by Equation 4-7:

EQUATION 4-7:

P _ D _ BOOST ≈ V _ IN × I _ IN - I _ OUT × _ UT - L _ LOSS - N _ f × OUT

Although the maximum output current for a single buck regulator can be as much as 3A, the MIC7400 will thermal limit and will not support this high output current on all outputs at the same time.

4.18 Total Power Dissipation

The total power dissipation in the MIC7400 package is equal to the sum of the power loss of each regulator:

EQUATION 4-8:

P _ D _ TOTAL ≈ SUM (P _ D _ SWITCHERS)

Once the total power dissipation is calculated, the IC junction temperature can be estimated using Equation 4-9:

EQUATION 4-9:

T _ J (MAX) ≈ T _ A + P _ D _ TOTAL × 0 _ JA

Where:

T_J(MAX) = The maximum junction temperature.

T_A = The ambient temperature.

θ_JA = The junction-to-ambient thermal resistance

of the package (30°C/W).

Figure 4-16 shows the measured junction temperature versus power dissipation of the MIC7400 evaluation board. The actual junction temperature of the IC depends upon many factors. The significant factors influencing the die temperature rise are copper thickness in the PCB, the surface area available for convection heat transfer, air flow and power dissipation from other components, including inductors, SOCs and processor ICs. It is good engineering practice to measure all power components temperature during the final design review using a thermal couple or IR thermometer, see the Thermal Measurements sub-section for details.

FIGURE 4-16: Power Dissipation.

4.19 Power Derating

The MIC7400 package has a 2W power dissipation limit. To keep the IC junction temperature below a 125°C design limit, the output power has to be limited above an ambient temperature of 65°C. Figure 4-17 shows the power dissipation derating curve.

FIGURE 4-17: Power Derating Curve.

The maximum power dissipation of the package can be calculated by Equation 4-10:

EQUATION 4-10:

P _ D (MAX) ≈ T _ J (MAX) - T _ Aθ_ JA

Where:

T_J(MAX) = The maximum junction temperature (125°C).

T_A = The ambient temperature.

θ_JA = The junction-to-ambient thermal resistance of the package (30°C/W).

4.20 Overtemperature Fault

An overtemperature fault is triggered when the IC junction temperature reaches 160° C. When this occurs, both the overtemperature fault flag is set to "1", the global power good output is pulled low and all the outputs are turned off. During the fault condition the ² C interface remains active and all registers values are maintained.

When the die temperature decreases by 20° C the overtemperature fault bit can be cleared. To clear the fault, either recycle power or write a logic "0" to the over temperature fault register. Once the fault bit is cleared, the outputs power up to their default values and are sequenced according to the time slot settings.

4.21 Input Voltage "Hot Plug"

High voltage spikes of twice the input voltage can appear on the MIC7400 PVIN pins if a battery pack is hot-plugged to the input supply voltage connection as shown in Figure 4-18 (Trace 1). These spikes are due to the inductance of the wires to the battery and the very low inductance and ESR of the ceramic input capacitors. This problem can be solved by placing a 150 µ F POS capacitor across the input terminals. Figure 4-18 (Trace 2) shows that the high voltage spike is greatly reduced to a value below the maximum allowable input voltage rating.

FIGURE 4-18: Hot Plug Input Voltage Spike.

4.22 Thermal Measurements

Measuring the IC's case temperature is recommended to ensure it is within its operating limits. Although this might seem like a very elementary task, it is easy to get erroneous results. The most common mistake is to use the standard thermal couple that comes with a thermal meter. This thermal couple wire gauge is large (typically 22 gauge) and behaves like a heatsink, resulting in a lower case measurement.

Two reliable methods of temperature measurement are a smaller thermal couple wire or an infrared thermometer. If a thermal couple wire is used, it must be constructed of 36 gauge wire or higher (smaller wire size) to minimize the wire heat-sinking effect. In addition, the thermal couple tip must be covered in either thermal grease or thermal glue to make sure that the thermal couple junction is making good contact with the case of the IC. Omega brand thermal couple (5SC-TT-K-36-36) is adequate for most applications.

Whenever possible, an infrared thermometer is recommended. The measurement spot size of most infrared thermometers is too large for an accurate reading on a small form factor ICs. However, an IR thermometer from Optris has a 1 mm spot size, which makes it a good choice for measuring the hottest point on the case. An optional stand makes it easy to hold the beam on the IC for long periods of time.

5.0 TIMING DIAGRAMS

5.1 Normal Power-Up Sequence for Outputs

The STDEL register sets the delay between powering up of each regulator at initial power-up (see power-up sequencing in Figure 5-1). Once all the internal power good registers PGOOD[1-6] are all "1", then the global PG pin goes high without delay (see the Global Power Good Pin section for more information).

The PORDEL register sets the delay for the POR flag pin. The POR delay time starts as soon as the AV_IN pin voltage rises above the system UVLO upper threshold set by the PORUP register. The POR output goes low without delay if AV_IN falls below the lower UVLO threshold set by the PORDN register.

FIGURE 5-1: MIC7400 Power-Up/Down.

5.2 Standby (STBY) Pin (Wake-Up)

An I²C write command to the STBY_CTRL_REG register or the STBY pin can be used to set the MIC7400 into standby mode. The standby (STBY) pin provides a hardware-specific manner in which to wake-up from stand-by mode and go into normal mode. Figure 5-2 shows the STBY pin operation. A low-to-high transition on the STBY pin switches the output from stand-by mode to normal mode.

There is a 100 µs STBY deglitch time to eliminate nuisance tripping, then all the regulators are enabled at the same time and ramp up with their programmed ramp rates.

FIGURE 5-2: MIC7400 STBY Function (DEFAULT).

6.0 PCB LAYOUT GUIDELINES

PCB layout is critical to achieve reliable, stable, and efficient performance. A ground plane is required to control EMI and minimize the inductance in power, signal, and return paths.

To minimize EMI and output noise, follow these layout recommendations to ensure proper operation:

6.1 General

• Most of the heat removed from the IC is due to the exposed pad (EP) on the bottom of the IC conducting heat into the internal ground planes and the ground plane on the bottom side of the board. Use at least 16 vias for the EP to ground plane connection.
• Do not connect the PGND and AGND traces together on the top layer. The single point connection is made on the layer 2 ground plane.
• Do not put a via directly in front of a high current pin, SW, PGND, or PVIN. This will increase the trace resistance and parasitic inductance.
• Do not place a via in between the input and output capacitor ground connection. Put it to the inside of the output capacitor and in the way of the high di/dt current path.
• Route all power traces on the top layer.
• Place the input capacitors first and put them as close as possible to the IC.

6.2 IC

• The 2.2 µ F ceramic capacitor, which is connected to the AVIN pin, must be located right at the IC. The AVIN pin is very noise sensitive and placement of the capacitor is very critical. Use wide traces to connect to the AVIN and AGND pins.
• The analog ground pin (AGND) must be connected directly to the ground planes. Do not route the SGND pin to the PGND Pad on the top layer.
• Use wide traces to route the input and output power lines.
• Use Layer 5 as an input voltage power plane.
• Layer 2 and the bottom layer (Layer 6) are ground planes.

6.3 Input Capacitor

• A 10 µ F X5R or X7R dielectrics ceramic capacitor is recommended on each of the PVIN pins for bypassing.
• Place the input capacitors on the same side of the board and as close to the IC as possible.

• Keep both the PVIN pin and PGND connections short.

• If possible, place vias to the ground plane close to the each input capacitor ground terminal, but not in the way of the high di/dit current path.

• Use either X7R or X5R dielectric input capacitors. Do not use Y5V or Z5U type capacitors.
• Do not replace the ceramic input capacitor with any other type of capacitor. Any type of capacitor can be placed in parallel with the input capacitor.
• In "Hot-Plug" applications, a Tantalum or Electrolytic bypass capacitor must be used to limit the over-voltage spike seen on the input supply with power is suddenly applied.

6.4 Inductor

• Keep the inductor connection to the switch node (SW) short.
• Do not route any digital lines underneath or close to the inductor.
• To minimize noise, place a ground plane underneath the inductor.

6.5 Output Capacitor

• Use a wide trace to connect the output capacitor ground terminal to the input capacitor ground terminal.
• The OUT[1-6] trace should be separate from the power trace and connected as close as possible to the output capacitor. Sensing a long high-current load trace can degrade the DC load regulation.

6.6 Proper Termination of Unused Pins

Many designs will not require all six DC/DC output voltages. In these cases, the unused pin must be connected to either VIN or GND. The schematic in Figure 6-1 shows where to tie the unused pins and Table 6-1 summarizes the connections.

FIGURE 6-1: Connections for Unused Pins.

TABLE 6-1: SUMMARIZATION OF UNUSED PIN CONNECTIONS

Unused VIN PGND
Boost PVIN6, PGIN6O, VOUT6 PGND6, SW6
Buck PVIN[x], VOUT[x} PGND[6], SW[x]
POR —	POR

7.0 I ² C CONTROL REGISTER

The MIC7400 I²C Read/Write registers are detailed here. During normal operation, the configuration data can be saved into non-volatile registers in EEPROM by addressing the chip and writing to SAVECONFIG key = 66'h. Saving CONFIG data to EEPROM takes time so the external host should poll the MIC7400 and read the CONFIG bit[1] of EEPROM Ready register 01'h to determine the end of programming.

All transactions start with a control byte sent from the I ² C master device. The control byte begins with a START condition, followed by a 7-bit slave address. The slave address is seven bits long followed by an eighth bit which is a data direction bit (R/W), a "0" indicates a transmission (WRITE) and a "1" indicates a request for data (READ). A data transfer is always terminated by a STOP condition that is generated by the master.

7.1 Serial Port Operation

7.1.1 EXTERNAL HOST INTERFACE

Bidirectional I ² C port capable of Standard (up to 100 kbits/s), Fast (up to 400 kbits/s), Fast Plus (up to 1 Mbit/s) and High Speed (up to 3.4 Mbit/s) as defined in the I ² C-Bus Specification.

The MIC7400 acts as an I²C slave when addressed by the external host. The MIC7400 slave address uses a fixed 7-bit code and is followed by an R/W bit which is part of the control word that is right after the start bit as shown in Figure 7-1 in the Device Address column.

The MIC7400 can receive multiple data bytes after a single address byte and automatically increments its register pointer to block fill internal volatile memory. Byte data is latched after individual bytes are received so multi-byte transfers could be corrupted if interrupted mid-stream.

No system clock is required by the digital core for I²C access from the external host (only the host SCL clock is assumed).

In order to prevent spurious operation of the I ² C, if a start bit is seen, then any partial communication is aborted and new I ² C data is allowed. Start bit is when SDA goes low when SCL is high. Stop bit is when SDA goes high when SCL is high. Normal I ² C exchange is shown in Figure 7-1.

FIGURE 7-1: Read/Write Protocol.

7.1.2 SPECIAL HOST I ² C COMMANDS

The following commands are all 2 byte communications:

- Byte1 = Device address with write bit set, LSB = 0.

- Byte2 = Special key.

Special keys include the following:

• SAVECONFIG Key = 66'h. Saves the shadow register configuration data into EEPROM registers 03'h through 23'h.
• RESET Key = 6A'h. Reloads only NORMAL mode voltage and current limit settings then enables the regulator to NORMAL mode with no soft-start, no sequencing, and no delays. Then it clears the STANDBY register bit 6 in register 03'h.
• RELOAD Key = 6B'h. Reloads all data from EEPROM into the shadow registers. No other actions are performed, including soft-start, sequencing, and delay.
• REBOOT Key = 6C'h. Turns all regulators OFF, reloads EEPROM data into shadow registers, then re-sequences the regulators with the programmed soft-start and sequence delays.
• SEQUENCE Key = 6D'h. Turns all regulators OFF, restarts the sequencer including soft-start and sequence delays.

OBS: In order to use the Special Keys, FORCE_CLK_ON bit 2 of the Internal Clock control register (0x2F'h) must be set to "1". After the action has completed, the FORCE_CLK_ON bit can be cleared by writing "0".

8.0 REGISTER SETTINGS DESCRIPTIONS

8.1 Power Good Register (00'h)

This register indicates when the regulators 1 – 6 output voltage is above 91% of the target value. The MIC7400 deglitches the input signal for 50 µ s in order to prevent false events. The global PG pin indicator is functional 'AND' of all the power good indicators during sequencing. Once the power-up sequence is complete, the global power good output stays high unless an output falls below its power-good limit, a thermal fault occurs, the input voltage drops below the lower UVLO threshold or an output is turned OFF by setting the enable register bit to "0" if the PGOOD_MASK[x] bit is set to "0".

TABLE 8-1: POWER GOOD STATUS REGISTER

Register Name	PGOOD1-6_REG Power Good Status Register
Address — 0x00'h
Field Bit R/W Default		Description
PGOOD1 0 R	0			Power Good indicator for Regulator 1
				0 = Buck Not Valid	1 = Buck Valid
PGOOD2 1 R	0			Power Good indicator for Regulator 2
				0 = Buck Not Valid	1 = Buck Valid
PGOOD3 2 R	0			Power Good indicator for Regulator 3
				0 = Buck Not Valid	1 = Buck Valid
PGOOD4 3 R	0			Power Good indicator for Regulator 4
				0 = Buck Not Valid	1 = Buck Valid
PGOOD5 4 R	0			Power Good indicator for Regulator 5
				0 = Buck Not Valid	1 = Buck Valid
PGOOD6 5 R	0			Power Good indicator for Regulator 6
				0 = Boost Not Valid	1 = Boost Valid
Reserved	6	R/W	0	Not Used	—
Reserved	7	R/W	0	Not Used	—

8.2 EEPROM-Ready Register (01'h)

This register indicates the status of EEPROM to external I²C host.

The READY bit = 1 when the Trim and Configuration data have been loaded into core from EEPROM after reset, reboot or reload and the chip is ready for operation. If the SAVE1 bit in register 04'h is read in as logic 1, the configuration registers will not be loaded from the EEPROM memory and the READY bit will still get set indicating that any startup procedure involving the EEPROM memory is complete. The READY bit will be set to 1 after loading or attempting to load Trim and Configuration data from EEPROM into volatile memory. The Trim data will always be loaded and if SAVE1 bit in register 04'h is set to logic 0, Configuration data is also loaded. Regardless of the SAVE1 bit being set or not, after the loading operation the READY bit is set to 1.

The CONFIG bit = 1 when the Configuration data have been saved to EEPROM after the SAVECONFIG Code is issued from the Host. If CONFIG=1 before the SAVECONFIG code is issued, CONFIG will be cleared immediately and then will be set to logic 1 again once all Configuration data is written to the EEPROM memory.

The EEPROM and EEPROM write bits indicate if an EEPROM read or write fault has occurred. These bits should be read and cleared prior to reloading data from the EEPROM memory.

TABLE 8-2: EEPROM STATUS REGISTER

Register Name	STATUS_REG EEPROM Status			Register
Address — 0x01'h
Field Bit R/W Default		Description
READY 0 R 0				Indicate ready for operation when the trim and configuration data has been loaded.
				0 = Data not loaded 1 = Chip ready
CONFIG 1 R 0				Indicate Configuration saved to EEPROM
				0 = Configuration not saved 1 = Configuration saved
Reserved	2 R 0		Not Used	—
Reserved	3	R/W	0	Not Used	—
Reserved	4	R/W	0	Not Used	—
Reserved	5	R/W	0	Not Used	—
EEPREAD	6	R/W	0	EEPROM Read
				0 = No Fault	1 = Fault
EEPWRITE	7	R/W	0	EEPROM Write
				0 = No Fault	1 = Fault

8.3 Fault Registers (02'h)

This register indicates the overcurrent flag for each regulator and one global overtemperature (OT). These register bits are set by an overcurrent condition and reset by writing a logic "0" to each bit by the I ² C host. The respective channel must be restarted to enter normal functionality in order to successfully clear the over current fault.

If the fault condition persists, the bit will be set to logic "1" again immediately by the MIC7400 after it is written to logic "0" by the host.

TABLE 8-3: OVERCURRENT STATUS FAULT REGISTER

Register Name	FAULT_REG			Overcurrent Status Fault Register
Address —				0x02'h
Field Bit R/W Default				Description
REG1OC	0	R/W	0	Regulator 1 Overcurrent
				0 = No Fault	1 = Fault
REG2OC	1	R/W	0	Regulator 2 Overcurrent
				0 = No Fault	1 = Fault
REG3OC	2	R/W	0	Regulator 3 Overcurrent
				0 = No Fault	1 = Fault
REG4OC	3	R/W	0	Regulator 4 Overcurrent
				0 = No Fault	1 = Fault
REG5OC	4	R/W	0	Regulator 5 Overcurrent
				0 = No Fault	1 = Fault
REG6OC	5	R/W	0	Regulator 6 Overcurrent
				0 = No Fault	1 = Fault
Reserved	6	R/W	0	Reserved	—
OT	7	R/W	0	Overtemperature
				0 = No Fault	1 = Fault

8.4 Standby Register (03'h)

This register controls standby mode operation. Global standby mode can either be enabled by I ² C or by changing the logic state of the STBY input pin. Global standby is controlled by the STBY_MODEB bit. When STBY_MODEB [6] = 1 then the regulators output voltages are set to their normal mode output voltage settings, (05'h - 0A'h) registers. When STBY_MODEB [6] = 0 then regulators output voltages are set to the standby mode output voltage settings, (0B'h - 10'h) registers. If STBY [1-6] register is set to logic "0", then the output is shut off in standby mode.

The global power good flag is asserted when an output is disabled unless the power good mask bit (PGOOD_MASK[x]) is set to 1.

TABLE 8-4: STANDBY REGISTER

Register Name	STBY_CTRL_REG Standby Register
Address — 0x03'h
Field Bit R/W Default		Description
STBY1 0 R/W 1				Regulator 1 Standby Voltage Control
				0 = OFF 1 = ON
STBY2 1 R/W 1				Regulator 2 Standby Voltage Control
				0 = OFF 1 = ON
STBY3 2 R/W 1				Regulator 3 Standby Voltage Control
				0 = OFF 1 = ON
STBY4 3 R/W 1				Regulator 4 Standby Voltage Control
				0 = OFF 1 = ON
STBY5 4 R/W 1				Regulator 5 Standby Voltage Control
				0 = OFF 1 = ON
STBY6 5 R/W 1				Regulator 6 Standby Voltage Control
				0 = OFF 1 = ON
STBY_MODEB	6 R/W 1			Global Standby Control
				0 = All regulators in Standby Mode 1 = All regulators in Normal Mode
SAVE1 7 R/W 0				Save Configuration
				0 = Configuration Saved to EEPROM 1 = Configuration Not Saved to EEPROM

8.5 Enable/Disable Register (04'h)

This register controls the enable/disable of each DC/DC regulators. When EN(n) bit transitions from "0" to "1", then the regulator(n) is enabled with soft-start unless the STBY_MODEB register bit in register 03'h is set to logic "0".

The configuration save bit "SAVE1" should be cleared by customer before saving configuration data to EEPROM. This bit is used during power up to indicate via the Status register (00'h) that configuration data has previously been stored.

TABLE 8-5: ENABLE REGISTER

Register Name	EN_REG			Enable Register
Address — 0x04'h
Field Bit R/W Default		Description
EN1	0 R/W	1		Regulator 1 ON/OFF Control bit
				0 = OFF	1 = ON
EN2	1 R/W	1		Regulator 2 ON/OFF Control bit
				0 = OFF	1 = ON
EN3	2 R/W	1		Regulator 3 ON/OFF Control
				0 = OFF	1 = ON
Address —				0x04'h
Field	Bit	R/W	Default	Description
EN4 3 R/W	1			Regulator 4 ON/OFF Control
				0 = OFF 1 = ON
EN5 4 R/W	1			Regulator 5 ON/OFF Control
				0 = OFF 1 = ON
EN6 5 R/W	1			Regulator 6 ON/OFF Control
				0 = OFF 1 = ON
Reserved 6 R/W 0 Not Used —
Reserved 7 R/W 0 Not Used —

8.6 Regulator Output Voltage Setting NORMAL Mode (05'h - 09'h)

One register for each regulator output (OUT1 - OUT5). Sets output voltage of regulator for NORMAL mode operation.

TABLE 8-6: DVC REGISTERS FOR OUT[1 - 5]

Register Name	OUT1-5_REG DVC Registers for OUT[1-5]
Address —				OUT1 = 0x05'h; OUT2 = 0x06'h; OUT3 = 0x07'hOUT4 = 0x08'h; OUT5 = 0x09'h
Field Bit	R/W	Default		Description
OUT[1-5]	5:0	R/W	OUT1 = 011110(1.8V)OUT2 = 101100(1.1V)OUT3 = 011110(1.8V)OUT4 = 101101(1.05V)OUT5 = 101001(1.25V)	Output Voltage setting of OUT[1-5]DVC from 3.3V to 0.8V in -50 mV steps
				000000 = 3.30V	010000 = 2.50V	100000 = 1.70V	110000 = 0.90V
				000001 = 3.25V	010001 = 2.45V	100001 = 1.65V	110001 = 0.85V
				000010 = 3.20V	010010 = 2.40V	100010 = 1.60V	110010 = 0.80V
				000011 = 3.15V	010011 = 2.35V	100011 = 1.55V	110011 = 0.80V
				000100 = 3.10V	010100 = 2.30V	100100 = 1.50V	110100 = 0.80V
				000101 = 3.05V	010101 = 2.25V	100101 = 1.45V	110101 = 0.80V
				000110 = 3.00V	010110 = 2.20V	100110 = 1.40V	110110 = 0.80V
				000111 = 2.95V	010111 = 2.15V	100111 = 1.35V	110111 = 0.80V
				001000 = 2.90V	011000 = 2.10V	101000 = 1.30V	111000 = 0.80V
				001001 = 2.85V	011001 = 2.05V	101001 = 1.25V	111001 = 0.80V
				001010 = 2.80V	011010 = 2.00V	101010 = 1.20V	111010 = 0.80V
				001011 = 2.75V	011011 = 1.95V	101011 = 1.15V	111011 = 0.80V
				001100 = 2.70V	011100 = 1.90V	101100 = 1.10V	111100 = 0.80V
				001101 = 2.65V	011101 = 1.85V	101101 = 1.05V	111101 = 0.80V
				001110 = 2.60V	011110 = 1.80V	101110 = 1.00V	111110 = 0.80V
				001111 = 2.55V	011111 = 1.75V	101111 = 0.95V	111111 = 0.80V
—	6	—	0	Not Used		—
—	7	—	0	Not Used		—

8.7 Boost Regulator Output Voltage Setting NORMAL Mode (0A'h)

Sets output voltage of the boost regulator (OUT6) in NORMAL mode operation.

TABLE 8-7: DVC REGISTERS FOR OUT6

Register Name	OUT6_REG DVC Registers
Address — 0x0A'h
Field Bit R/W Default Description
OUT6 5:0	R/W		001010(12V)	DVC from 14V to 7V in 200 mV decrements
				000000 = 14.0V	010000 = 10.8V	100000 = 7.6V	110000 = 7.0V
				000001 = 13.8V	010001 = 10.6V	100001 = 7.4V	110001 = 7.0V
				000010 = 13.6V	010010 = 10.4V	100010 = 7.2V	110010 = 7.0V
				000011 = 13.4V	010011 = 10.2V	100011 = 7.0V	110011 = 7.0V
				000100 = 13.2V	010100 = 10.0V	100100 = 7.0V	110100 = 7.0V
				000101 = 13.0V	010101 = 9.8V	100101 = 7.0V	110101 = 7.0V
				000110 = 12.8V	010110 = 9.6V	100110 = 7.0V	110110 = 7.0V
				000111 = 12.6V	010111 = 9.4V	100111 = 7.0V	110111 = 7.0V
				001000 = 12.4V	011000 = 9.2V	101000 = 7.0V	111000 = 7.0V
				001001 = 12.2V	011001 = 9.0V	101001 = 7.0V	111001 = 7.0V
				001010 = 12.0V	011010 = 8.8V	101010 = 7.0V	111010 = 7.0V
				001011 = 11.8V	011011 = 8.6V	101011 = 7.0V	111011 = 7.0V
				001100 = 11.6V	011100 = 8.4V	101100 = 7.0V	111100 = 7.0V
				001101 = 11.4V	011101 = 8.2V	101101 = 7.0V	111101 = 7.0V
				001110 = 11.2V	011110 = 8.0V	101110 = 7.0V	111110 = 7.0V
				001111 = 11.0V	011111 = 7.8V	101111 = 7.0V	111111 = 7.0V
—	6	—	0	Not Used		—
—	7	—	0	Not Used		—

8.8 Regulator Voltage Setting STBY Mode (0B'h - 0F'h)

This register is used to sets the output voltage of regulators 1 - 5 in STBY mode operation.

TABLE 8-8: STANDBY REGISTERS

Register Name	STBY_OUT1-5_REG Standby DVC Registers
Address —				OUT1 = 0x0B'h; OUT2 = 0x0C'h; OUT3 = 0x0D'hOUT4 = 0x0E'h; OUT5 = 0x0F'h
Field Bit	R/W	Default Description
SB_OUT[1-5]	5:0 R/W		OUT1 = 011110(1.8V)OUT2 = 101100(1.1V)OUT3 = 011110(1.8V)OUT4 = 101101(1.05V)OUT5 = 101001(1.25V)	Output Voltage setting of OUT[1-5]DVC from 3.3V to 0.8V in -50 mV steps
				000000 = 3.30V 0	10000 = 2.50V 100	000 = 1.70V 11000 = 0.90V
				000001 = 3.25V 0	10001 = 2.45V 100	001 = 1.65V 110001 = 0.85V
				000010 = 3.20V 0	10010 = 2.40V 100	010 = 1.60V 11001 = 0.80V
				000011 = 3.15V 0	10011 = 2.35V 100	011 = 1.55V 110011 = 0.80V
				000100 = 3.10V 0	10100 = 2.30V 100	100 = 1.50V 110100 = 0.80V
				000101 = 3.05V 0	10101 = 2.25V 100	101 = 1.45V 110101 = 0.80V
				000110 = 3.00V 0	10110 = 2.20V 100	110 = 1.40V 110110 = 0.80V
				000111 = 2.95V	010111 = 2.15V	100111 = 1.35V 110111 = 0.80V
				001000 = 2.90V 0	11000 = 2.10V 101	000 = 1.30V 111000 = 0.80V
				001001 = 2.85V 0	11001 = 2.05V 101	001 = 1.25V 111001 = 0.80V
				001010 = 2.80V 0	11010 = 2.00V 101	010 = 1.20V 11101 = 0.80V
				001011 = 2.75V	011011 = 1.95V	101011 = 1.15V 111011 = 0.80V
				001100 = 2.70V	011100 = 1.90V	101100 = 1.10V 111100 = 0.80V
				001101 = 2.65V	011101 = 1.85V	101101 = 1.05V 111101 = 0.80V
				001110 = 2.60V	011110 = 1.80V	101110 = 1.00V 111110 = 0.80V
				001111 = 2.55V	011111 = 1.75V	101111 = 0.95V 111111 = 0.80V
—	6	—	0	Not Used		—
—	7	—	0	Not Used		—

8.9 Boost Regulator Output Voltage Setting STBY Mode (10'h)

Sets output voltage of the boost regulator (OUT6) for STBY mode operation.

TABLE 8-9: STANDBY DVC REGISTER FOR OUT6

Register Name	STBY_OUT6_REG DVC Registers
Address — 0x10'h
Field Bit R/W Default Description
SB_OUT6	5:0	R/W	001010(12V)	DVC from 14V to 7V in 200 mV decrements
				000000 = 14.0V	010000 = 10.8V	100000 = 7.6V 1	10000 = 7.0V
				000001 = 13.8V	010001 = 10.6V	100001 = 7.4V 1	10001 = 7.0V
				000010 = 13.6V	010010 = 10.4V	100010 = 7.2V 1	10010 = 7.0V
				000011 = 13.4V	010011 = 10.2V	100011 = 7.0V	110011 = 7.0V
				000100 = 13.2V	010100 = 10.0V	100100 = 7.0V 1	10100 = 7.0V
				000101 = 13.0V	010101 = 9.8V 1	100101 = 7.0V 1101	101 = 7.0V
				000110 = 12.8V	010110 = 9.6V	100110 = 7.0V	110110 = 7.0V
				000111 = 12.6V	010111 = 9.4V	100111 = 7.0V	110111 = 7.0V
				001000 = 12.4V	011000 = 9.2V 1	101000 = 7.0V 1	11000 = 7.0V
				001001 = 12.2V	011001 = 9.0V 1	101001 = 7.0V 1	11001 = 7.0V
				001010 = 12.0V	011010 = 8.8V 1	101010 = 7.0V 1	11010 = 7.0V
				001011 = 11.8V	011011 = 8.6V	101011 = 7.0V	111011 = 7.0V
				001100 = 11.6V	011100 = 8.4V	101100 = 7.0V	111100 = 7.0V
				001101 = 11.4V	011101 = 8.2V	101101 = 7.0V	111101 = 7.0V
				001110 = 11.2V	011110 = 8.0V	101110 = 7.0V	111110 = 7.0V
				001111 = 11.0V	011111 = 7.8V	101111 = 7.0V	111111 = 7.0V
—	6	—	0	Not Used		—
—	7	—	0	Not Used		—

8.10 Sequence Register (11'h)

Each regulator can be assigned to start in any one of six sequencing slots (1 to 6). If starting in slot 1, the regulator starts immediately. If starting in any other slot, the regulator must wait for the PGOOD = 1 flags of all regulators assigned to the preceding slot and then wait for the specified delay time (register 17'h) i.e., all PGOODs in preceding state flag then the delay timer is started and when delay completes the regulator is enabled.

Each regulator will delay its startup (after the appropriate preceding PGOOD flags) by the delay set in the Delay Register (17'h), unless the regulator is assigned to sequence state 0.

If all default Enable bits = 0 the IC starts up, but no outputs are enabled.

Sequencing is only used during initial startup, and not used when outputs are enabled via I²C command. If outputs are enabled via I²C , then soft-start is still active, but start-up delays (timed from preceding PGOODs) are not.

TABLE 8-10: SEQUENCE STATE 1 REGISTER

Register Name	SEQ1_REG			Sequence Register
Address — 0x11'h
Field	Bit	R/W Default		Description
REG1SQ1	0	R/W	0	0 = No Start	1 = Regulator 1 will Start in Sequence State 1
REG2SQ1	1	R/W	0	0 = No Start	1 = Regulator 2 will Start in Sequence State 1
REG3SQ1	2	R/W	0	0 = No Start	1 = Regulator 3 will Start in Sequence State 1
Register Name	SEQ1_REG Sequence Register
Address — 0x11'h
Field Bit R/W Default		Description
REG4SQ1 3 R/W 1 0 = No Start					1 = Regulator 4 will Start inSequence State 1
REG5SQ1 4 R/W 0 0 = No Start					1 = Regulator 5 will Start inSequence State 1
REG6SQ1 5 R/W 0 0 = No Start					1 = Regulator 6 will Start inSequence State 1
— 6 R/W 0 Reserved
— 7 R/W 0 Reserved

TABLE 8-11: SEQUENCE STATE 2 REGISTER

Register Name	SEQ2_REG Sequence Register
Address — 0x12'h
Field Bit R/W Default		Description
REG1SQ2 0 R/W 0 0 = No Start					1 = Regulator 1 will Start in Sequence State 2
REG2SQ2 1 R/W 1 0 = No Start					1 = Regulator 2 will Start in Sequence State 2
REG3SQ2 2 R/W 1 0 = No Start					1 = Regulator 3 will Start in Sequence State 2
REG4SQ2 3 R/W 0 0 = No Start					1 = Regulator 4 will Start in Sequence State 2
REG5SQ2 4 R/W 0 0 = No Start					1 = Regulator 5 will Start in Sequence State 2
REG6SQ2 5 R/W 0 0 = No Start					1 = Regulator 6 will Start in Sequence State 2
— 6 R/W 0 Reserved
— 7 R/W 0 Reserved

TABLE 8-12: SEQUENCE STATE 3 REGISTER

Register Name	SEQ3_REG			Sequence Register
Address —				0x13'h
Field Bit R/W Default				Description
REG1SQ3 0 R/W 1		0	= No Start		1 = Regulator 1 will Start in Sequence State 3
REG2SQ3 1 R/W 0		0	= No Start		1 = Regulator 2 will Start in Sequence State 3
REG3SQ3 2 R/W 0		0	= No Start		1 = Regulator 3 will Start in Sequence State 3
REG4SQ3 3 R/W 0		0	= No Start		1 = Regulator 4 will Start in Sequence State 3
REG5SQ3 4 R/W 0		0	= No Start		1 = Regulator 5 will Start in Sequence State 3
REG6SQ3 5 R/W 0		0	= No Start		1 = Regulator 6 will Start in Sequence State 3

TABLE 8-12: SEQUENCE STATE 3 REGISTER (CONTINUED)

Register Name	SEQ3_REG			Sequence Register
Address — 0x13'h
Field Bit R/W Default		Description
— 6 R/W 0 Reserved
— 7 R/W 0 Reserved

TABLE 8-13: SEQUENCE STATE 4 REGISTER

Register Name	SEQ4_REG Sequence Register
Address — 0x14'h
Field Bit R/W Default		Description
REG1SQ4 0 R/W 0 0 = No Start					1 = Regulator 1 will Start inSequence State 4
REG2SQ4 1 R/W 0 0 = No Start					1 = Regulator 2 will Start inSequence State 4
REG3SQ4 2 R/W 0 0 = No Start					1 = Regulator 3 will Start inSequence State 4
REG4SQ4 3 R/W 0 0 = No Start					1 = Regulator 4 will Start inSequence State 4
REG5SQ4 4 R/W 1 0 = No Start					1 = Regulator 5 will Start inSequence State 4
REG6SQ4 5 R/W 0 0 = No Start					1 = Regulator 6 will Start inSequence State 4
— 6 R/W 0 Reserved
— 7 R/W 0 Reserved

TABLE 8-14: SEQUENCE STATE 5 REGISTER

Register Name	SEQ5_REG			Sequence Register
Address —				0x15'h
Field Bit R/W Default				Description
REG1SQ5 0 R/W 0 0 = No Start					1 = Regulator 1 will Start in Sequence State 5
REG2SQ5 1 R/W 0 0 = No Start					1 = Regulator 2 will Start in Sequence State 5
REG3SQ5 2 R/W 0 0 = No Start					1 = Regulator 3 will Start in Sequence State 5
REG4SQ5 3 R/W 0 0 = No Start					1 = Regulator 4 will Start in Sequence State 5
REG5SQ5 4 R/W 0 0 = No Start					1 = Regulator 5 will Start in Sequence State 5
REG6SQ5 5 R/W 0 0 = No Start					1 = Regulator 6 will Start in Sequence State 5
— 6 R/W 0				Reserved
— 7 R/W 0				Reserved

TABLE 8-15: SEQUENCE STATE 6 REGISTER

Register Name	SEQ6_REG Sequence Register
Address — 0x16'h
Field Bit R/W Default		Description
REG1SQ6 0 R/W 0		0	= No Start		1 = Regulator 1 will Start inSequence State 6
REG2SQ6 1 R/W 0		0	= No Start		1 = Regulator 2 will Start inSequence State 6
REG3SQ6 2 R/W 0		0	= No Start		1 = Regulator 3 will Start inSequence State 6
REG4SQ6 3 R/W 0		0	= No Start		1 = Regulator 4 will Start inSequence State 6
REG5SQ6 4 R/W 0		0	= No Start		1 = Regulator 5 will Start inSequence State 6
REG6SQ6 5 R/W 1		0	= No Start		1 = Regulator 6 will Start inSequence State 6
—	6 R/W	0 Reserved
—	7 R/W	0 Reserved

8.11 Delay Register (17'h)

The STDEL register sets the delay between powering up of each regulator at initial power up (see Figure 5-1). Once all the internal power good registers PGOOD[1-6] are all "1", then the global PG pin goes high without delay.

The PORDEL register sets the delay for the POR flag pin. The POR delay time starts as soon as AVIN pin voltage rises above the system UVLO upper threshold set by the PORUP register (21'h). The POR output goes low without delay if AVIN falls below the lower UVLO threshold set by the PORDN register (22'h).

TABLE 8-16: DELAY REGISTER

Register Name	DELAY_CNTL_REG			Delay Register
Address —				0x17'h
Field Bit R/W Default	Description
STDEL	2:0	R/W	001(1 ms)	Delay Time from 0 ms to 7 ms in 1 ms increment
				000 = 0 ms	010 = 2 ms	100 = 4 ms	110 = 6 ms
				001 = 1 ms	011 = 3 ms	101 = 5 ms	111 = 7 ms
PORDEL	7:3	R/W	00011(20 ms)	Delay Time from 5 ms to 160 ms in 5 ms increment
				00000 = 5ms	01000 = 45ms	10000 = 85ms	11000 = 125ms
				00001 = 10ms	01001 = 50ms	10001 = 90ms	11001 = 130ms
				00010 = 15ms	01010 = 55ms	10010 = 95ms	11010 = 135ms
				00011 = 20ms	01011 = 60ms	10011 = 100ms	11011 = 140ms
				00100 = 25ms	01100 = 65ms	10100 = 105ms	11100 = 145ms
				00101 = 30ms	01101 = 70ms	10101 = 110ms	11101 = 150ms
				00110 = 35ms	01110 = 75ms	10110 = 115ms	11110 = 155ms
				00111 = 40ms	01111 = 80ms	10111 = 120ms	11111 = 160ms

8.12 Soft-Start Registers (18'h - 1A'h)

When regulator(n) is turned on from either the Enable Register (04'h) in NORMAL mode or from the Standby Register (03'h) in STANDBY mode, the three REG(n)SS soft-start bits are used to control both the rising and falling ramp rate of the outputs.

In NORMAL mode, the outputs are stepped from the current regulator voltage settings to a newly programmed regulator voltage setting or to the default value.

On power-up, the regulator voltage output is set to the lowest possible voltage setting, which is 3F'h. The voltage regulator will change by one step or increment at a time. The amount of time between each step is controlled by the soft-start registers. Table 8-17 details the amount of time for each encoded soft-start value.

TABLE 8-17: SOFT-START REGISTER SPEED SETTINGS

Register R/W	Default Description
SS_SPEED = 0 RW 000		Soft-Start Time from 4 μs to 512 μs
		000 = 4 μs	010 = 16 μs	100 = 64 μs	110 = 256 μs
		001 = 8 μs	011 = 32 μs	101 = 128 μs	111 = 512 μs
SS_SPEED = 1 RW 000		Soft-Start Time from 8 μs to 1024 μs
		000 = 8 μs	010 = 32 μs	100 = 128 μs	110 = 512 μs
		001 = 16 μs	011 = 64 μs	101 = 256 μs	111 = 1024 μs

TABLE 8-18: SOFT-START REGISTER OUT1 AND OUT2

Register Name	SS1-2_REG			Soft-Start Register for VOUT1 and VOUT2
Address	—			0x18'h
Field	Bit	R/W Default		Description
REG1SS	2:0	R/W	001(8 μs)	OUT1 Soft-Start Time. See Table 8-17 for Soft-Start settings.
REG2SS	5:3	R/W	001(8 μs)	OUT2 Soft-Start Time. See Table 8-17 for Soft-Start settings.
—	6	R/W	0	Reserved
SS_SPEED	7	R/W	0	Sets the speed of the clock to slow or fast for different clock division, see Table 8-17. 0 = Slow speed; 1 = Fast speed.

TABLE 8-19: SOFT-START REGISTER OUT3 AND OUT4

Register Name	SS3-4_REG			Soft-Start Register for VOUT3 and VOUT4
Address	—			0x19'h
Field	Bit	R/W Default		Description
REG3SS	2:0	R/W	001(8 μs)	OUT3 Soft-Start Time. SeeTable 8-17for Soft-Start settings.
REG4SS	5:3	R/W	001(8 μs)	OUT4 Soft-Start Time. SeeTable 8-17for Soft-Start settings.
—	6	R/W	0	Reserved
—	7	R/W	0	Reserved

TABLE 8-20: SOFT-START REGISTER OUT5 AND OUT6

Register Name	SS5-6_REG Soft-Start Register			for VOUT5 and VOUT6
Address — 0x1A'h
Field Bit R/W Default		Description
REG5SS 2:0	R/W		001(8 μs)	OUT5 Soft-Start Time. See Table 8-17 for Soft-Start settings.
REG6SS 5:3	R/W		010(16 μs)	OUT6 Soft-Start Time. See Table 8-17 for Soft-Start settings.
—	6	R/W	0	Reserved
—	7	R/W	0	Reserved

8.13 Current-Limit (Normal Mode) Registers (1B'h - 1D'h)

This register is used to set the current limit for each DC/DC regulator in normal mode operation.

TABLE 8-21: CURRENT-LIMIT REGISTER I OUT1 AND IOUT2

Register Name	ILIMIT_1-2_REG			Current-Limit Register for VOUT1 and VOUT2
Address — 0x1B'h
Field Bit R/W Default				Description
REG1CL 3:0	R/W		1001(4.1A)	Normal current-limit for regulator 1 from 8.6A to 1.1A in 0.5A decrements
				0000 = 8.6A	0100 = 6.6A	1000 = 4.6A	1100 = 2.6 A
				0001 = 8.1A	0101 = 6.1A	1001 = 4.1A	1101 = 2.1A
				0010 = 7.6A	0110 = 5.6A	1010 = 3.6A	1110 = 1.6A
				0011 = 7.1A 0	11 = 5.1A 1011	= 3.1A 1111 = 1.1A
REG2CL 7:4	R/W		1001(4.1A)	Normal current-limit for regulator 2 from 8.6A to 1.1A in 0.5A decrements
				0000 = 8.6A	0100 = 6.6A	1000 = 4.6A	1100 = 2.6 A
				0001 = 8.1A	0101 = 6.6A	1001 = 4.1A	1101 = 2.1A
				0010 = 7.6A	0110 = 5.6A	1010 = 3.6A	1110 = 1.6A
				0011 = 7.1A 0	11 = 5.2A 1011	= 3.1A 1111 = 1.1A

TABLE 8-22: CURRENT-LIMIT REGISTER I OUT3 AND IOUT4

Register Name	ILIMIT_3-4_REG			Current-Limit Register for VOUT3 and VOUT4
Address —				0x1C'h
Field Bit R/W Default		Description
REG3CL 3:0	R/W		1001(4.1A)	Normal current-limit for regulator 3 from 8.6A to 1.1A in 0.5A decrements
				0000 = 8.6A	0100 = 6.6A	1000 = 4.6A	1100 = 2.6 A
				0001 = 8.1A	0101 = 6.1A	1001 = 4.1A	1101 = 2.1A
				0010 = 7.6A	0110 = 5.6A	1010 = 3.6A	1110 = 1.6A
				0011 = 7.1A	0111 = 5.1A	1011 = 3.1A 1	111 = 1.1A
REG4CL 7:4	R/W		0101(6.1A)	Normal current-limit for regulator 4 from 8.6A to 1.1A in 0.5A decrements
				0000 = 8.6A	0100 = 6.6A	1000 = 4.6A	1100 = 2.6 A
				0001 = 8.1A	0101 = 6.6A	1001 = 4.1A	1101 = 2.1A
				0010 = 7.6A	0110 = 5.6A	1010 = 3.6A	1110 = 1.6A
				0011 = 7.1A	0111 = 5.6A	1011 = 3.1A 1	111 = 1.1A

TABLE 8-23: CURRENT-LIMIT REGISTER I OUT5 AND IOUT6

Register Name	LIMIT_5-6_REG Current-Limit			Register for V OUT5 and VOUT6
Address — 0x1D'h
Field Bit R/W Default		Description
REG5CL 3:0	R/W		1001(4.1A)	Normal current-limit for regulator 5 from 8.6A to 1.1A in 0.5A decrements
				0000 = 8.6A	0100 = 6.6A	1000 = 4.6A	1100 = 2.6 A
				0001 = 8.1A	0101 = 6.1A	1001 = 4.1A	1101 = 2.1A
				0010 = 7.6A	0110 = 5.6A	1010 = 3.6A	1110 = 1.6A
				0011 = 7.1A	0111 = 5.1A	1011 = 3.1A 1	111 = 1.1A
REG6CL 6:4	R/W		011(2.24A)	Current-limit from 2.6A to 1.78A in 0.12A decrements
				000 = 2.6A	010 = 2.36A	100 = 2.12A	110 = 1.88A
				001 = 2.48A	011 = 2.24A	101 = 2.00A	111 = 1.76A
—	7	R/W	0	0 = Current-Limit On		1 = Current-Limit Off

8.14 Current-Limit (STBY Mode) Registers (1E'h - 20'h)

This register is used to set the current-limit for each DC/DC regulator when in standby (STBY) mode operation.

TABLE 8-24: STANDBY CURRENT-LIMIT REGISTER I OUT1 AND IOUT2

Register Name	STBY_ILIMIT_1-2_REG			Standby Current-Limit Register for VOUT1 and VOUT2
Address —				0x1E'h
Field Bit R/W Default				Description
SB1CL	3:0 R/W		1001(4.1A)	Standby current-limit for regulator 1 from 8.6A to 1.1A in 0.5A decrements
				0000 = 8.6A	0100 = 6.6A	1000 = 4.6A	1100 = 2.6 A
				0001 = 8.1A	0101 = 6.1A	1001 = 4.1A	1101 = 2.1A
				0010 = 7.6A	0110 = 5.6A	1010 = 3.6A	1110 = 1.6A
				0011 = 7.1A 01	11 = 5.1A 1011	= 3.1A 1111 = 1.1A
SB2CL	7:4 R/W		1001(4.1A)	Standby current-limit for regulator 2 from 8.6A to 1.1A in 0.5A decrements
				0000 = 8.6A	0100 = 6.6A	1000 = 4.6A	1100 = 2.6 A
				0001 = 8.1A	0101 = 6.6A	1001 = 4.1A	1101 = 2.1A
				0010 = 7.6A	0110 = 5.6A	1010 = 3.6A	1110 = 1.6A
				0011 = 7.1A 01	11 = 5,1A 1011	= 3.1A 1111 = 1.1A

TABLE 8-25: STANDBY CURRENT-LIMIT REGISTER I OUT3 AND IOUT4

Register Name	STBY_ILIMIT_3-4_REG			Standby Current-Limit Register for VOUT3 and VOUT4
Address	—			0x1F'h
Field Bit R/W Default		Description
SB3CL	3:0 R/W		1001(4.1A)	Standby current-limit for regulator 3 from 8.6A to 1.1A in 0.5A decrements
				0000 = 8.6A	0100 = 6.6A	1000 = 4.6A	1100 = 2.6 A
				0001 = 8.1A	0101 = 6.1A	1001 = 4.1A	1101 = 2.1A
				0010 = 7.6A	0110 = 5.6A	1010 = 3.6A	1110 = 1.6A
				0011 = 7.1A	0111 = 5.1A	1011 = 3.1A 1	111 = 1.1A

TABLE 8-25: STANDBY CURRENT-LIMIT REGISTER I OUT3 AND IOUT4 (CONTINUED)

Register Name	STBY_ILIMIT_3-4_REG			Standby Current-Limit Register for VOUT3 and VOUT4
Address	—			0x1F'h
Field	Bit	R/W	default	Description
SB4CL 7:4 R/W			0101(6.1A)	Standby current-limit for regulator 4 from 8.6A to 1.1A in 0.5A decrements
				0000 = 8.6A 0100 = 6.6A 1000= 4.6A 1100 = 2.6 A
				0001 = 8.1A 0101 = 6.1A 1001= 4.1A 1101 = 2.1A
				0010 = 7.6A 0110 = 5.6A 1010= 3.6A 1110 = 1.6A
				0011 = 7.1A 0111 = 5.1A 1011= 3.1A 1111 = 1.1A

TABLE 8-26: STANDBY CURRENT-LIMIT REGISTER I OUT5 AND IOUT6

Register Name	STBY_ILIMIT_5-6_REG Standby			Current-Limit Register for V OUT5 and VOUT6
Address	—			0x20'h
Field	Bit	R/W Default		Description
SB5CL 3:0 R/W			1001(4.1A)	Standby current-limit for regulator 5 from 8.6A to 1.1A in 0.5A decrements
				0000 = 8.6A 0	100 = 6.6A 1000	= 4.6A	1100 = 2.6 A
				0001 = 8.1A 0	101 = 6.1A 1001	= 4.1A	1101 = 2.1A
				0010 = 7.6A 0	110 = 5.6A 1010	= 3.6A	1110 = 1.6A
				0011 = 7.1A 0	111 = 5.1A 1011	= 3.1A	1111 = 1.1A
SB6CL 6:4 R/W			011(2.24A)	Current-limit from 2.6A to 1.78A in 0.12A decrements
				000 = 2.6A 0	10 = 2.36A 100 =	2.12A	110 = 1.88A
				001 = 2.48A 0	11 = 2.24A 101 =	2.00A	111 = 1.76A
—	7	R/W	0	0 = Current-Limit On		1 = Current-Limit Off

8.15 Power-on-Reset (POR) Threshold Voltage Setting Register (21'h and 22'h)

This register is used to set the rising and falling threshold of power-on-reset (POR) comparator. The POR threshold voltage setting is based on the logic level of the VSLT pin in addition to the register bits. Refer to Table 8-16 for POR time delay settings.

TABLE 8-27: RISING AND FALLING POWER-ON-RESET THRESHOLD VOLTAGE SETTINGS

Condition	—			Rising and Falling Power-On-Reset Threshold Voltage Setting
Pin	Bit	R/W	Default	Description
VSCLT = 0	4:0 R/W	00000		3.3V to 2.3V in 50 mV decrements
				00000 = 3.25V	01000 = 2.85V	10000 = 2.45V	11000 = 2.25V
				00001 = 3.20V	01001 = 2.80V	10001 = 2.40V	11001 = 2.25V
				00010 = 3.15V	01010 = 2.75V	10010 = 2.35V	11010 = 2.25V
				00011 = 3.10V	01011 = 2.70V	10011 = 2.30V	11011 = 2.25V
				00100 = 3.05V	01100 = 2.65V	10100 = 2.25V	11100 = 2.25V
				00101 = 3.00V	01101 = 2.60V	10101 = 2.25V	11101 = 2.25V
				00110 = 2.95V	01110 = 2.55V	10110 = 2.25V	11110 = 2.25V
				00111 = 2.90V	01111 = 2.50V	10111 = 2.25V	11111 = 2.25V

TABLE 8-27: RISING AND FALLING POWER-ON-RESET THRESHOLD VOLTAGE SETTINGS

Condition	—			Rising and Falling Power-On-Reset Threshold Voltage Setting
Pin	Bit	R/W	Default	Description
VSCLT = 1 4:0	R/W 00000			4.3V to 3.3V in 50 mV decrements
				00000 = 4.25V	01000 = 3.85V	10000 = 3.45V 11000 = 3.25V
				00001 = 4.20V	01001 = 3.80V	10001 = 3.40V 11001 = 3.25V
				00010 = 4.15V	01010 = 3.75V	10010 = 3.35V 11010 = 3.25V
				00011 = 4.10V	01011 = 3.70V	10011 = 3.30V 11011 = 3.25V
				00100 = 4.05V	01100 = 3.65V	10100 = 3.25V 11100 = 3.25V
				00101 = 4.00V	01101 = 3.60V	10101 = 3.25V 11101 = 3.25V
				00110 = 3.95V	01110 = 3.55V	10110 = 3.25V 1110 = 3.25V
				00111 = 3.90V	0111 = 3.50V	10111 = 3.25V 11111 = 3.25V

The three most significant bits [7:5] in registers 21'h and 22'h are used to mask the output voltage power-good flag after the start-up sequenced is finished.

TABLE 8-28: POWER-ON-RESET RISING THRESHOLD VOLTAGE SETTING REGISTER (21'H)

Register Name	PORUP_REG			Power-on-Reset Rising Threshold
Address	—			0x21'h
Field	Bit	R/W	Default	Description
PORUP	4:0	R/W	01011	See Table 8-27
PGOOD_MASK1	5	R/W	1	0 = Do not mask PGOOD1	1 = Mask PGOOD1
PGOOD_MASK2	6	R/W	1	0 = Do not mask PGOOD2	1 = Mask PGOOD2
PGOOD_MASK3	7	R/W	1	0 = Do not mask PGOOD3	1 = Mask PGOOD3

TABLE 8-29: POWER-ON-RESET FALLING THRESHOLD VOLTAGE SETTING REGISTER (22'H)

Register Name	PORDN_REG			Power-on-Reset Falling Threshold
Address	—			0x22'h
Field	Bit	R/W	Default	Description
PORDN	4:0	R/W	01101	See Table 8-27
PGOOD_MASK4	5	R/W	1	0 = Do not mask PGOOD4	1 = Mask PGOOD4
PGOOD_MASK5	6	R/W	1	0 = Do not mask PGOOD5	1 = Mask PGOOD5
PGOOD_MASK6	7	R/W	1	0 = Do not mask PGOOD6	1 = Mask PGOOD6

8.16 Pull-Down When Disabled Register (23'h)

This register is used to set the preference of enabling/disabling a pull-down FET when the DC/DC regulators are disabled. The pull-down value for buck regulators 1 through 5 is 90Ω. The pull-down current value for the boost regulator 6 is programmable.

TABLE 8-30: PULL-DOWN WHEN DISABLED REGISTER

Register Name	PULLDN1-6_REG Pull-Down When Disabled Register
Address — 0x23'h
Field Bit R/W Default		Description
PULLD1 0 R/W 0				Enable/Disable the pull-down on Regulator 1 when power down.0 = No Pull-Down; 1 = Pull-Down
PULLD2 1 R/W 0				Enable/Disable the pull-down on Regulator 2 when power down.0 = No Pull-Down; 1 = Pull-Down
PULLD3 2 R/W 0				Enable/Disable the pull-down on Regulator 3 when power down.0 = No Pull-Down; 1 = Pull-Down
PULLD4 3 R/W 0				Enable/Disable the pull-down on Regulator 4 when power down.0 = No Pull-Down; 1 = Pull-Down
PULLD5 4 R/W 0				Enable/Disable the pull-down on Regulator 5 when power down.0 = No Pull-Down; 1 = Pull-Down
PULLD6C	6:5	R/W	00	Sets Boost Pull-Down Current Level00 = 148 mA; 01 = 111 mA; 10 = 74 mA; 11 = 37 mA
PULLD6 7 R/W 0				Enable/Disable the pull-down on Regulator 6 when power down.0 = No Pull-Down; 1 = Pull-Down

8.17 Internal Clock Control Register

This register houses the Force_CLK_ON bit 2 used when sending the special commands keys. Bit 2 of this register is used to set the PMIC clock to permanently be enabled in order to execute the new command. This bit should be cleared after the command has been executed in order to save power (the internal clock logic will shut down the clock automatically when not needed).

TABLE 8-31: INTERNAL CLOCK CONTROL REGISTER

Register Name	Force Clock Register			Internal Clock Control Register
Address —				0x2F'h
Field Bit R/W Default				Description
—	0 R/W	0		Reserved
—	1 R/W	0		Reserved
FORCE_-CLK_ON	2	R/W	0	0=No action.1= Force the internal clock to keep running and not be turned off by the power down logic.
—	3 R/W	0		Reserved
—	4 R/W	0		Reserved
—	5 R/W	0		Reserved
—	6 R/W	0		Reserved
—	7 R/W	0		Reserved

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

36-Pin FQFN*

(Configurable)

36-Pin FQFN*

(Configured)

Example

Example

Legend: XX...X Product code or customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week '01') NNN Alphanumeric traceability code ePb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) e3 can be found on the outer packaging for this package. •, ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle mark).

Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo.

Underbar (_) and/or Overbar (−) symbol may not be to scale.

36-Lead 4.5 mm x 4.5 mm FQFN Package Outline and Recommended Land Pattern

TITLE

36 LEAD QFN 4.5x4.5mm PACKAGE (Flip Chip) OUTLINE & RECOMMENDED LAND PATTERN

DRAWING #	FQFN4545-36LD-PL-1	UNIT	MM
Lead Frame	Copper	Lead Finish	Matte Tin

TOP VIEW NOTD 1, 2, 3

BOTTOM VIEW NOTE: 1, 2, 3

SIDE VIEW NOTE 1, 2, 3

NOTE:

1. MAX PACKAGE WARPAGE IS 0.05 MM
2. MAX ALLOWABLE BURR IS 0.076MM IN ALL DIRECTIONS
3. PIN #1 IS ON TOP WILL BE LASER MARKED
4. RED CIRCLE IN LAND PATTERN REPRESENT THERMAL VIA. SIZE SHOULD
   BE 0.30-0.35MM IN DIAMETER, 0.8MM PITCH & MUST BE CONNECTED TO GND
   FOR MAX THERMAL PERFORMANCE
5. GREEN RECTANGLES (SHADED AREA, OPTIONAL) REPRESENT SOLDER
   STENCIL OPENING ON EXPOSED PAD AREA. SIZE SHOULD BE 0.60X0.60 MM
   IN SIZE, 0.20MM SPACING.
6. LAND PATTERN OPENINGS MARKED BY '*' (PINS#14, 32 & EPAD) ARE OF
   SAME GND AND SHOULD BE CONNECTED ON BOARD LEVEL FOR MAXIMUM
   THERMAL PERFORMANCE

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.

POD-Land Pattern drawing #FQFN4545-36LD-PL-1

RECOMMENDED LAND PATTERN NOTE: 4, 5, 6

STACKED-UP

EXPOSED METAL TRACE

SOLDER STENCIL OPENING
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.

NOTES:

APPENDIX A: REVISION HISTORY

Revision A (November 2017)

• Converted Micrel document MIC7400 to Microchip data sheet DS20005887A.
• Minor text changes throughout.

NOTES:

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.

Device: MIC7400: Configurable PMIC, Five Channel Buck Regulator Plus One Boost with HyperLight Load® and I²C Control

Output Voltages: = 1.8V, 1.1V, 1.8V, 1.05V, 1.25V, 12V XXXX = Configurable (Contact Marketing for Options)

Junction Y = -40°C to +125°C

Temperature

Range:

Package: FL = 36-Lead 4.5 mm x 4.5 mm FQFN

Media Type: = 1/Tube T5 = 500/Reel TR = 5,000/Reel

Examples:

a) MIC7400YFL-T5: Configurable PMIC, Five Channel Buck Regulator Plus One Boost with HyperLight Load and I²C Control, 1.8V, 1.1V, 1.8V, 1.05V, 1.25V, 12V Output Voltages, -40°C to +125°C Temp. Range, 36-Lead FQFN, 500/Reel

b) MIC7400-XXXXYFL-TR: Configurable PMIC, Five Channel Buck Regulator Plus One Boost with HyperLight Load and I²C Control, Configurable Output Voltages, -40°C to +125°C Temp. Range, 36-Lead FQFN, 5,000/Reel

c) MIC7400YFL: Configurable PMIC, Five Channel Buck Regulator Plus One Boost with HyperLight Load and I²C Control, 1.8V, 1.1V, 1.8V, 1.05V, 1.25V, 12V Output Voltages, -40°C to +125°C Temp. Range, 36-Lead FQFN, 1/Tube

d) MIC7400-XXXXYFL-T5: Configurable PMIC, Five Channel Buck Regulator Plus One Boost with HyperLight Load and I²C Control, Configurable Output Voltages, -40°C to +125°C Temp. Range, 36-Lead FQFN, 500/Reel

Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.

NOTES:

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.
- Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
- There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
- Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELQQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 16949=

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All other trademarks mentioned herein are property of their respective companies.

© 2017, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-2382-9

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