SY89468U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY89468U Microchip

The SY89468U is a 2.5V, 1:20 LVDS fanout buffer with a 2:1 differential input multiplexer (MUX). A unique Fail-Safe Input (FSI) protection prevents metastable output conditions when the selected input clock fails to a DC voltage (voltage between the pins of the differential input drops significantly below 100mV).

The differential input includes Micrel's unique, 3-pin internal termination architecture that can interface to any differential signal (AC- or DC-coupled) as small as 100mV (200mV_PP) without any level shifting or termination resistor networks in the signal path. The outputs are LVDS compatible with very fast rise/fall times guaranteed to be less than 270ps.

The SY89468U operates from a 2.5V ±5% supply and is guaranteed over the full industrial temperature range of -40°C to +85°C. The SY89468U is part of Micrel's high-speed, Precision Edge® product line.

All support documentation can be found on Micrel's web site at: www.micrel.com.

Functional Block Diagram

IN0 50Ω VTD 50Ω /IN0 VREF-AC0 IN1 50Ω VTT 50Ω /IN1 VREF-AC1 SEL 0 1 20 LVDS compatible outputs 20 Q0 - Q19 20 /Q0 - /Q19 OE D

Precision Edge®

Features

- Selects between two inputs, and provides 20 precision LVDS copies

- Fail-Safe Input

– Prevents outputs from oscillating when input is invalid

•Guaranteed AC performance over temperature and supply voltage:

- DC to >1.5GHz throughput

- < 1200ps Propagation Delay (In-to-Q)

- < 270ps Rise/Fall times

- Ultra-low jitter design:

- < 1ps_RMS random jitter

- < 1 ps_RMS cycle-to-cycle jitter

- <10psPP total jitter (clock)

- < 0.7ps_RMS MUX crosstalk induced jitter

- Unique, patented MUX input isolation design minimizes adjacent channel crosstalk

- Unique, patented internal termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS)

- Wide input voltage range VCC to GND

- 2.5V ±5% supply voltage

-40°C to +85°C industrial temperature range

•Available in 64-pin EPAD-TQFP package

Applications

- Fail-safe clock protection

•Ultra-low jitter LVDS clock or data distribution

•Rack-based Telecom/Datacom

Markets

•LAN/WAN

- Enterprise servers

•ATE

•Test and measurement

Precision Edge is a registered trademark of Micrel, Inc.

MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • http://www.micrel.com

Ordering Information ^(1)

Part Number	Package Type	Operating Range	Package Marking	Lead Finish
SY89468UHY	H64-1	Industrial	SY89468UHY with Pb-Free bar-line Indicator	Matte-SnPb-Free
SY89468UHYTR^(2)	H64-1	Industrial	SY89468UHY with Pb-Free bar-line Indicator	Matte-SnPb-Free

Notes:

1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ , DC Electricals Only.
2. Tape and Reel.

Pin Configuration

VCC GND VREF-AC0 VT0 IN0 /IN0 SEL OE IN1 /IN1 VT1 VREF-AC1 GND VCC Q0/Q0 Q1/Q1 Q2/Q2 Q3/Q3 Q4/Q4 Q5/Q5 Q6/Q6 Q7/Q7 Q8/Q8 Q9/Q9 VCC Q10/Q10 Q11/Q11 Q12/Q12 VCC Q13/Q13 Q14/Q14 Q15/Q15 Q16/Q16 Q17/Q17 Q18/Q18 Q19/Q19 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 VCC 47 Q7 46 /Q7 45 Q8 44 /Q8 43 Q9 42 /Q9 41 VCC 40 GND 39 Q10 38 /Q10 37 Q11 36 /Q11 35 Q12 34 /Q12 33 VCC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 /019 /018 /017 /016 /015 /014 /013 /012 /011 /010 /009 /008 /007 /006 /005 /004 /003 /002 /001 /000 /000 /000 /000 /000 /000 /000 /000 /000 /000 /000 /000 /000 /000 /000 /000 /000 /000 /000 /000 /000 /000 /

64-Pin EPAD-TQFP (H64-1)

Pin Description

Pin Number	Pin Name	Pin Function
1, 16, 23, 3341, 48, 58	VCC	Positive Power Supply: Bypass with 0.1 F 0.01 F low ESR capacitors as close to the V_cc pins as possible.
64, 6362, 6160, 5957, 5655, 5453, 5251, 5047, 4645, 4443, 4239, 3837, 3635, 3431, 3029, 2827, 2625, 2422, 2120, 1918, 17	Q0, /Q0Q1, /Q1Q2, /Q2Q3, /Q3Q4, /Q4Q5, /Q5Q6, /Q6Q7, /Q7Q8, /Q8Q9, /Q9Q10, /Q10Q11, /Q11Q12, /Q12Q13, /Q13Q14, /Q14Q15, /Q15Q16, /Q16Q17, /Q17Q18, /Q18Q19, /Q19	Differential Output Pairs: The output swing is typically 325mV. Used and unused outputs must be terminated with 100Ω across the pair (Q, /Q). These differential LVDS outputs are a logic function of the IN0, IN1, and SEL inputs. See “Truth Table” below.
4, 13	VREF-AC0VREF-AC1	Reference Voltage: These outputs bias to V_cc-1.2V . They are used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01 F low ESR capacitor to VCC. Due to limited drive capability, each VREF-AC pin is only intended to drive its respective VT pin. Maximum sink/source current is ± 0.5mA . See “Input Interface Applications” subsection.
5, 12	VT0, VT1	Input Termination Center-Tap: Each side of a differential input pair terminates to the VT pin. The VT pin provides a center-tap for each input (IN, /IN) to a termination network for maximum interface flexibility. See “Input Interface Applications” subsection.
6, 710, 11	IN0, /IN0IN1, /IN1	Differential Inputs: These input pairs are the differential signal inputs to the device. These inputs accept AC- or DC-coupled signals as small as 100mV. The input pairs internally terminate to a VT pin through 50Ω. Each input has level shifting resistors of 3.72k to VCC. This allows a wide input voltage range from VCC to GND. See Figure 3, Simplified Differential Input Stage for details. Note that when these inputs are left in an open state, the FSI feature will override this input state and provide a valid state at the output. See “Functional Description” subsection.
2, 3, 14, 15,32, 40, 49	GND, Exposed Pad	Ground. Exposed pad must be connected to a ground plane that is the same potential as the ground pins.
9	OE	Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q19 outputs. It is internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open. When disabled, Q goes LOW and /Q goes HIGH. OE being synchronous, outputs will be enabled/disabled following a rising and a falling edge of the input clock. V_TH = V_cc/2 .
8	SEL	Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left open. V_TH = V_cc/2 .

Truth Table

Inputs					Outputs
IN0	/IN0	IN1	/IN1	SEL	Q	/Q
0	1	X	X	0	0	1
1	0	X	X	0	1	0
X	X	0	1	1	0	1
X	X	1	0	1	1	0

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_cc ) -0.5V to +4.0V

Input Voltage ( V_IN ) ....-0.5V to V_CC

LVDS Output Current ( I_OUT ). ±10mA

Current ( V_T )

Source or sink on VT pin ....±100mA

Input Current

Source or sink current on (IN, /IN) ....±50mA

Current ( V_REF )

(4)

Source/Sink Current on V _REF-AC (4)....±0.5mA

Maximum operating Junction Temperature..... 125°C

Lead Temperature (soldering, 20 sec.)..... +260°C

Storage Temperature ( T_s ) -65^ to 150^

Operating Ratings ^(2)

Supply Voltage (Vcc) +2.375V to +2.625V

Ambient Temperature ( T_A )....-40°C to +85°C

Package Thermal Resistance ^(3)

TQFP ( _JA )

Still-Air 35°C/W

TQFP ( _JB )

Junction-to-Board 21°C/W

DC Electrical Characteristics ^(5)

T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_CC	Power Supply		2.375	2.5	2.625	V
I_CC	Power Supply Current	No load, max V_CC		260	365	mA
R_IN	Input Resistance (IN-to- V_T )		45	50	55	Ω
R_DIFF\_IN	Differential Input Resistance (IN-to-/IN)		90	100	110	Ω
V_IH	Input High Voltage (IN, /IN)		0.1		V_CC	V
V_IL	Input Low Voltage (IN, /IN)		0		V_IH-0.1	V
V_IN	Input Voltage Swing (IN, /IN)	See Figure 2a. Note 6.	0.1		1.0	V
V_DIFF\_IN	Differential Input Voltage Swing |IN-/IN|	See Figure 2b.	0.2			V
V_IN\_FSI	Input Voltage Threshold that Triggers FSI			30	100	mV
V_REF-AC	Output Reference Voltage	I_VREF-AC = ± 0.5mA	V_CC-1.3	V_CC-1.2	V_CC-1.1	V
V_T\_IN	Voltage from Input to V_T				1.28	V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. _JA and _JB values are determined for a 4-layer board in still air unless otherwise stated.
4. Due to limited drive capability use for input of the same package only.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. V_IN (max) is specified when V_T is floating.

LVDS Outputs DC Electrical Characteristics ^(7)

V_CC = +2.5V ± 5% , R_L = 100 across the outputs; T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_OUT	Output Voltage Swing (Q, /Q)	See Figure 2a	250	325		mV
V_DIFF\_OUT	Differential Output Voltage Swing |Q – /Q|	See Figure 2b	500	650		mV
V_OCM	Output Common Mode Voltage (Q, /Q)	See Figure 5a	1.125	1.20	1.275	V
V_OCM	Change in Common Mode Voltage (Q, /Q)	See Figure 5b	-50		+50	mV

LVTTL/CMOS DC Electrical Characteristics ^(7)

V_CC = 2.5V ± 5% ; T_A = -40^ to +85°C, unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_IH	Input HIGH Voltage		2.0			V
V_IL	Input LOW Voltage				0.8	V
I_H	Input HIGH Current		-125		30	μA
I_L	Input LOW Current		-300			μA

Note:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC Electrical Characteristics ^(8)
V_CC = +2.5V ± 5% , R_L = 100_ across the outputs; T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
f_MAX	Maximum Operating Frequency	V_OUT ≥ 200mV	1.0	1.5		GHz
t_pd	Differential Propagation DelayIN-to-Q	100mV ≤ V_IN ≤ 200mV, Note 9	600	810	1200	ps
	IN-to-Q	200mV ≤ V_IN ≤ 800mV, Note 9	500	720	1100	ps
	SEL-to-Q	V_TH = V_CC/2	350	580	850	ps
t_6 OE	Set-up Time OE-to-IN	Note 10	300			ps
t_H OE	Hold Time IN-to-OE	Note 10	800			ps
t_SKEW	Output-to-Output Skew	Note 11		15	40	ps
	Input-to-Input Skew	Note 12		5	25	ps
	Part-to-Part Skew	Note 13			300	ps
t_ITTER	ClockRandom Jitter	Note 14			1	ps_RMS
	Cycle-to-Cycle Jitter	Note 15			1	ps_RMS
	Total Jitter	Note 16			10	ps_PP
	Crosstalk-Induced Jitter	Note 17			0.7	ps_RMS
t_1	Output Rise/Fall Time (20% to 80%)	At full output swing.	90		270	ps
	Duty Cycle	V_IN > 200mV	47		53	%
		100mV ≤ V_IN ≤ 200mV	45		55	%

Notes:

1. High-frequency AC-parameters are guaranteed by design and characterization.
2. Propagation delay is measured with input t_n , t_r ≤ 300ps (20% to 80%). The propagation delay is a function of the rise and fall times at IN. See “Typical Operating Characteristics” for details.
3. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold do not apply.
4. Output-to-Output skew is measured between two different outputs under identical transitions.
5. Input-to-Input skew is the time difference between the two inputs to one output, under identical input transitions.
6. Part-to-Part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
7. Random Jitter is measured with a K28.7 character pattern, measured at <f_MAX .
8. Cycle-to-Cycle Jitter definition: the variation of periods between adjacent cycles, T_n - T_n-1 where T is the time between rising edges of the output signal.
9. Total Jitter definition: with an ideal clock input of frequency < f_MAX , no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value.
10. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each other at the inputs.

Functional Description

Clock Select (SEL)

SEL is an asynchronous TTL/CMOS compatible input that selects one of the two input signals. An internal 25kΩ pull-up resistor defaults the input to logic HIGH if left open. Input switching threshold is V cc/2. Refer to Figure 1a.

Fail-Safe Input (FSI)

The input includes a special fail-safe circuit to sense the amplitude of the input signal and to latch the outputs when there is no input signal present or when the amplitude of the input signal drops sufficiently below 100mV_PK , typically 30mV_PK . Refer to Figure 1b.

Input Clock Failure Case

If the input clock fails to a floating, static, or extremely low signal swing such that the voltage across the input pair is significantly less than 100mV, FSI

function will eliminate a metastable condition and latch the outputs to the last valid state. No ringing and no undetermined state will occur at the output under these conditions. The output recovers to normal operation once the input signal returns to a valid state with a typical swing greater than 30mV.

Note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on the rise and fall time of the input signal and on its amplitude.

Output Enable (OE)

OE is a synchronous TTL/CMOS-compatible input that enables/disables the outputs based upon the input to this pin. The enable function is synchronous so that the clock outputs will be enabled or disabled following a rising and a falling edge of the input clock.

Refer to Figure 1c. Internal 25kΩ pull-up resistor defaults the input to logic HIGH if left open. Input switching threshold is V_cc/2 .

Timing Diagrams

SEL Vcc/2 Vcc/2 tpd tpd Q /Q

Figure 1a. SEL-to-Q Delay

Figure 1b. Fail-Safe Feature

IN Disabled Enabled OE /Q Q

Figure 1c. Enable Output Timing Diagram

/IN IN /Q Q t_pd t_pd V_IN V_OUT

Figure 1d. Propagation Delay

OE VCC/2 VCC/2 IN ts th /IN

Figure 1e. Setup and Hold Time

Typical Operating Characteristics

V_CC = 2.5V , GND = 0V, V_IN = 200mV , R_L = 100 across the outputs; T_A = 25^ , unless otherwise stated.

Functional Characteristics

V_CC = 2.5V , GND = 0V, V_IN = 200mV , R_L = 100 across the outputs; T_A = 25^ , unless otherwise stated.

Single-Ended and Differential Swings

V_{IN} V_{OUT} 325mV (typ.)

Figure 2a. Single-Ended Voltage Swing

650mV (typ.) VDIFF_IN, VDIFF_OUT

Figure 2b. Differential Voltage Swing

Input Stage

VCC 1.86kΩ 1.86kΩ 1.86kΩ IN 50Ω VT 50Ω /IN GND

Figure 3. Simplified Differential Input Stage

Input Interface Applications

VCC LVPECL GND VCC 0.1μF RP NC VREF-AC IN IN SY89468U Note: For 3.3V, Rp = 50Ω. For 2.5V, Rp = 19Ω.

Figure 4a. LVPECL Interface (DC-Coupled)

VCC LVPECL GND Rp Rp GND IN IN 0.1μF VT VREF-AC SY89468U Note: For 3.3V, Rp = 100Ω. For 2.5V, Rp = 50Ω.

Figure 4b. LVPECL Interface (AC-Coupled)

VCC CML IN /IN SY89468U GND NC □ VT NC □ VREF-AC Option: may connect VT to VCC

Figure 4c. CML Interface (DC-Coupled)

VCC CML GND VCC 0.1μF IN /IN SY89468U VT VREF-AC

Figure 4d. CML Interface (AC-Coupled)

VCC LVDS GND IN /IN SY89468U NC VT NC VREF-AC

Figure 4e. LVDS Interface (DC-Coupled)

LVDS Output Interface Applications

LVDS specifies a small swing of 325mV typical, on a nominal 1.2V common mode above ground. The common mode voltage has tight limits to permit large variations in the ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep EMI low.

VOUT 100Ω VOH, VOL VOH, VOL GND

Figure 5a. LVDS Differential Measurement

50Ω 50Ω VOCM, ΔVOCM GND

Figure 5b. LVDS Common Mode Measurement

Related Product and Support Documentation

Part Number	Function	Data Sheet Link
SY89467U	Precision LVPECL 1:20 Fanout MUX with 2:1 MUX and internal termination with Fail Safe Input	http://www.micrel.com/_PDF/HBW/sy89467u.pdf
	MLF® Application Note	www.amkor.com/products/notes_papers/MLFAppNote.pdf
HBW Solutions	New Products and Applications	www.micrel.com/product-info/products/solutions.shtml

Package Information

12.00 [0.472] BSC SQ. 10.00 [0.394] BSC SQ. 4 4.50 +0.03 -0.03 [0.177 +0.012] -0.012] 64 49 1 48 4.50 +0.03 -0.03 [0.177 +0.012] -0.012] 16 17 32 33 1.20 [0.047] MAX. 0.50 [0.020] BSC SEE DETAIL "A" 0.01 [0.004] 0.22 +0.03 -0.03 [0.009 +0.002]

1.00 ±0.06 [0.039 ±0.002] DETAIL "A" 0° MIN. 0.20 [0.008] 0.09 [0.004] 0.15 [0.006] 0.05 [0.002] 0-7* 0.60 ±2.15 [0.024 ±8.88] 1.00 [0.039] REF.

NOTES:
1. DIMENSIONS ARE IN MM[INCHES].
2. CONTROLLING DIMENSION: MM.
3. EXPOSED PAD: Cu WITH Sn/Pb PLATING.
4. DIMENSION DOES NOT INCLUDE MOLD FLASH OF 0.254[0.010] MAX.
5. DIE UP ORIENTATION SHOWN. EXPOSED PAD IS VISIBLE FROM BOTTOM OF PACKAGE.
6. MAXIMUM AND MINIMUM SPECIFICATIONS ARE INDICATED AS FOLLOWS: MAX MIN
7. THIS DIMENSION INCLUDES LEAD FINISH.

64-Pin EPAD-TQFP (H64-1)

Packages Notes:

1. Package meets Level 2 Moisture Sensitivity Classification.
2. All parts are dry-packed before shipment.
3. Exposed pad must be soldered to a ground for proper thermal management.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL [phone] FAX [phone] WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

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