SN74ALVCH162268DL - Electronic component TEXAS INSTRUMENTS - Free user manual and instructions

USER MANUAL SN74ALVCH162268DL TEXAS INSTRUMENTS

This designed	12-bit	to forCC operation.	24-bit	registered to 3.6-V	GND A10 V	18 19	39 38	GND 1B9	exchanger
The which high-speed	SN74ALVCH162268 data	must bus	be to a wide,	transferred	A11 A12	used 21	37 36	1B8 for from	applications a narrow bus.
The between registers (CLK) ( CLKEN) synchronous data	device	the on inputs	provides two the when with A outputs.	synchronous Data	low frequency 1B1 1B2 GND 1B3 CLKEN2B and SE selects 29			VCC 1B6 data	exchange in the int of the clock-enable ( SEL) line
For storage presented ( OEA,	data	transfer register	in the synchronously	A-to-B A-to-2B	direction, path. as a 24-bit terminals			Proper word are	two-st or on registered
The and	B outputs, undershoot.	which	are	designed				to sink	up

ORDERING
INFORMATION

T_A	PACKAGE^(1)			ORDERABLE		PART
-40 °C to	SSOP - DL	Tube		SN74ALVCH162268DL		ALVCH162268
		Tape and		reel	SN74ALVCH162268DLR
	85 °C	TSSOP		- DGG	Tape	and reel
	VFBGA	GQL Tape and (Pb-free)		reel	SN74ALVCH162268KR	VH2268
	VFBGA	ZQL				74ALVCH162268ZQLR

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DESCRIPTION/ORDERING INFORMATION (CONTINUED)

To ensure____	the	high-impedance				state	during	pc
possible, by the outputs	and current-sinking cannot	cc	#ough should be determined	a pubep capability		resistor; of prior	V the to the	the driver. arrival
Active with the	bus-hold	circuitry		holds is not		unused recommended.	or	undriven
	bus-hold	circuitry

GQL OR ZQL PACKAGE (TOP VIEW)

INPUTS OUTPUTS
CLK	OEA		OEB
↑	H	H	ZZ
↑	H	L	Z Active
↑	L	H	Active
↑	L	L	Active

A 1B, 2B

Z

Active

A-TO-B STORAGE

INPUTS			OUTPUTS
CLKENA1	CLKENA2		CLK
H	H	X	X_0^(1)	2B_0^(1)
L	L	↑	L ^(2)	L X
L	L	↑	HH ^(2)	X
X	L	↑	L	X
X	L	↑	H	X

( OEB = L)

A 1B

(1)	Output established		level	before		the	indicated
(2)	Two	CLK	edges		are	needed

steady-state

to propagate

B-TO-A STORAGE

INPUTS
CLKEN1B CLKEN2B CLK		SEL		1B 2B
H	X	X	H	X	_0^(1) X
X	H	X	L	X	_0^(1) X
L	L	↑	H	L	X
L	L	↑	H	H	X
X	L	↑	L	X	L
X	L	↑	L	X	H

( OEA = L)

OUTPUT
A
A
A
L
H
L
H

(1)

Output were

level established

before

the

indicated

steady-state

LOGIC DIAGRAM (POSITIVE LOGIC)

graph TD
    A["CLK"] --> B["2"]
    C["CLKEN1B"] --> D["2"]
    E["CLKEN2B"] --> F["27"]
    G["CLKENA1"] --> H["30"]
    I["CLKENA2"] --> J["55"]
    K["OEB"] --> L["56"]
    M["SEL"] --> N["28"]
    O["OEAL"] --> P["1"]
    Q["A1"] --> R["8"]
    S["1 of 12 Channels"] --> T["1D C1"]
    U["CE"] --> V["C1 1D"]
    W["CE"] --> X["C1 1D"]
    Y["CE"] --> Z["C1 1D"]
    AA["CE"] --> AB["C1 1D"]
    AC["CE"] --> AD["C1 1D"]
    AE["CE"] --> AF["C1 1D"]
    AG["CE"] --> AH["C1 1D"]
    AI["CE"] --> AJ["C1 1D"]
    AK["CE"] --> AL["C1 1D"]
    AM["CE"] --> AN["C1 1D"]
    AO["CE"] --> AP["C1 1D"]
    AQ["CE"] --> AR["C1 1D"]
    AS["CE"] --> AT["C1 1D"]
    AU["CE"] --> AV["C1 1D"]
    AW["CE"] --> AX["C1 1D"]
    AY["CLK"] --> AZ["29"]
    BA["CLKEN1B"] --> BB["2"]
    BC["CLKEN2B"] --> BD["27"]
    BE["CLKENA1"] --> BF["30"]
    BG["CLKENA2"] --> BH["55"]
    BI["OEB"] --> BJ["56"]
    BK["SEL"] --> BL["28"]
    BM["OEAL"] --> BN["1"]
    BO["A1"] --> BP["G1"]
    BP --> BQ["i̅ 1"]
    BR["A1"] --> BS["CE C1 1D 1D"]
    BT["A1"] --> BU["CE C1 1D 1D"]
    BV["A1"] --> BW["CE C1 1D 1D"]
    BX["A1"] --> BY["CE C1 1D 1D"]
    CA["A1"] --> CB["CE C1 1D 1D"]
    CC["A1"] --> CD["CE C1 1D 1D"]
    CE --> CEA["C1 6"]
    CEA --> CEB["C2B1"]
    CEB --> CEC["C1 6"]
    CEC --> CED["C2B1"]
    CED --> CEE["C1 6"]
    CEE --> CEF["C2B1"]
    CEF --> CEG["C1 6"]
    CEG --> CEH["C2B1"]
    CEH --> CEI["C1 6"]
    CEI --> CEJ["C2B1"]
    CEJ --> CEK["C1 6"]
    CEK --> CEL["C2B1"]
    CEL --> CEM["C1 6"]
    CEM --> CEN["C2B1"]

Pin numbers shown are for the DGG and DL packages.

ABSOLUTE MAXIMUM RATINGS ^(1)

over operating free-air temperature range (unless
						MIN		MAX	UNIT-0.5
V_CC	Supply voltage range
V_I	Input voltage range		Except (2) I/O ports			-0.5		4.6
			I/O (3) ports (3)			-0.5 cc + V 0.5
V_O	Output v^(2) v^(3) range					-0.5 cc + V 0.5		V
I_IK	Input clamp current		_1 < 0			V		-50	mA
I_OK	Output clamp current		_o < 0			V		-50	mA
I_O	Continuous output current
	Continuous current GND through each					V		±	100
_JA	Package thermal impedance package		DGG package						64
			Device package						56
			GQL/ZQL package
T_stg	Storage temperature range

RECOMMENDED OPERATING CONDITIONS ^(1)

							MIN MAX UNIT
V_CC	Supply voltage							1.65 3.6
V_IH	High-level input voltage		V_CC=1.65 V to				1.95 CC V	0.65
			cc=2.3 V to 2.7 V V					1.7
			V_CC=2.7 V to 3.6 V					2
V_IL	Low-level input voltage		V_CC=1.65 V to				1.95 V cc
			cc=2.3 V to 2.7 V
			V_CC=2.7 V to 3.6 V
V_I	Input voltage						cc	V 0
V_O	Output voltage						cc	V
I_OH	High-level output current		V_CC=1.65 V					-4
			V_CC=2.3 V port)					-12
			V_CC=2.7 V port)					-12
			V_CC=3 V					-24 mA
	High-level output current		V_CC=1.65 V					-2
			V_CC=2.3 V port)					-6
			V_CC=2.7 V port)					-8
			V_CC=3 V					-12
I_OL	Low-level output current (A port)		V_CC=1.65 V					4
			V_CC=2.3 V					12
			V_CC=2.7 V					12
			V_CC=3 V					24 mA
	Low-level output current (B port)		V_CC=1.65 V					6
			V_CC=2.3 V					8
			V_CC=2.7 V					12
			V_CC=3 V
Δ t/ Δ v Input transition rise or fall rate
T_A	Operating free-air temperature

(1)

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unused Implications

control

inputs of Slow

GND

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the ensu device Floating

proprest CMOS

beviceheld Inputs,

ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature
PARAMETER		TEST	CONDITIONS MIN (1) TYMAX
V_OH	A port	I_OH= -100 A		1.65C- 0.2 V to 3.6		V2V
		I_OH= -4 mA		1.65 V
		I_OH= -6 mA		2.3 V
		I_OH= -12 mA		2.3 V
				2.7 V
			3 V	2.4
		I_OH= -24 mA		3 V
	B port	I_OH= -100 A		1.65C- 0.2 V to 3.6
		I_OH= -2 mA		1.65 V
		I_OH= -4 mA		2.3 V
		I_OH= -6 mA		2.3 V
			3 V	2.4
		I_OH= -8 mA		2.7 V
		I_OH= -12 mA		3 V
V_OL	A port	I_OL= 100 A		1.65 V to 3.6		V0.450.40.550.450.550.60.8±1
		I_OL= 4 mA		1.65 V
		I_OL= 6 mA		2.3 V
		I_OL= 12 mA	2.3 V
			2.7 V
		I_OL= 24 mA		3 V
	B port	I_OL= 100 A		1.65 V to 3.6
		I_OL= 2 mA		1.65 V
		I_OL= 4 mA		2.3 V
		I_OL= 6 mA		2.3 V
			3 V
		I_OL= 8 mA		2.7 V
		I_OL= 12 mA		3 V
I_I		V_I= _CCV or GND		3.6 V
I_I(hold)		V_I= 0.58 V	1.65	V	25	±500±1
		V_I= 1.07 V			-25
		V_I= 0.7 V	2.3 V		45
		V_I= 1.7 V			-45
		V_I= 0.8 V	3 V		75
		V_I= 2 V			-75
		V_I= 0 to (2) 3.6 V	3.6 V
I_OZ^(3)		V_O= _CCV or GND		3.6 V
I_CC		V_I= _CCV or GND= 0 I	3.6 V
_CC		One input 0.6 atV, V Other CC or G Inputs	3at V V to 3.6 V
C_I	Control	I= _CCV or GND V		3.3 V
C_IO	A or B	ports CC V or GND		3.3 V

TIMING REQUIREMENTS

over recommended operating free-air temperature
				V_cc = 2.5 ± 0.2	V_cc = 2.7	_c = 3.3V ±	V_UNITMAX	V_MIN
				MIN	MAX	MIN
f_clock	Clock frequency					120		125
t_w	Pulse duration, CLK high			or low			3.3
t_su	Setup time	A data before CLK		↑		4.5	↑	4
		B data before CLK		↑		0.8		1.2
		SEL before CLK				1.4		1.6
		CLKENA1 or CLKENA2			before	CLK
		CLKEN1B or CLKEN2B			before	CLK		3.6 ns
		OE before CLK ↑				4.2		3.2
t_n	Hold time	A data after CLK				0	0	0.2
		B data after CLK				1.3		1.2
		SEL after CLK ↑				1		1
		CLKENA1 or CLKENA2			after	CLK ↑		0.1
		CLKEN1B or CLKEN2B			after	CLK ↑		0.1
		OE after CLK ↑			0			0.2

SWITCHING CHARACTERISTICS

over recommended operating free-air temperature
PARAMETER	FROM(INPUT)		V_CC=1.8 OUTPUT TYP	V_CC=2.5 ±0.2	V_VCC=2.7V	o_F=3.3V	V ±0.3	VMAX
				MIN	MAX	MIN
f_max				120	125		150
t_pd	CLK	B	8	1.6	6.1	5.9	5.4	1.8
		A (1B)		8	1.6	5.8		ns 1.7
		A (2B)		8	1.6	5.8		5.3
		A (SEL)		11	2.5	7.3		6.5
t_en	CLK	B	12	2.7	7.2		6.8	2.6
		A	9	2	6.2	5.6		ns 5.1
t_dis	CLK	B	10	2.8	7.2		6.1	2.5
		A	9	2	6.5	5.4		ns 5

OPERATING CHARACTERISTICS
T_A = 25^

PARAMETER						V_CC = 2.5 TEST TYP	ccV= 3.3VCONDITIONS TYP	V
C_pd	Power	dissipation	Outputs	enabledance= 50disabled	pF, f =	10 MHz	C	87
			Outputs					80.5

PARAMETER MEASUREMENT INFORMATION

From Output Under Test CL (see Note A) RL RL S1 VLOAD Open GND

LOAD CIRCUIT

TEST S1
t_pd	Open
t_PLZ/t_PZL	V_LOAD
t_PHZ/t_PZH	GND

V_CC	INPUT		V_M	V_LOAD	C_L	R_L	V_
	V_I	t_r/t_f
1.8 V ± 0.15 V	V_CC	≤2 ns	V_CC/2	2 · V_CC	30 pF	1 kΩ	0.15 V
2.5 V ± 0.2 V	V_CC	≤2 ns	V_CC/2	2 · V_CC	30 pF	500 Ω	0.15 V
2.7 V	2.7 V	≤2.5 ns	1.5 V	6 V	50 pF	500 Ω	0.3 V
3.3 V ± 0.3 V	2.7 V	≤2.5 ns	1.5 V	6 V	50 pF	500 Ω	0.3 V

Timing Input V_I 0 V t_su t_h Data Input V_M V_I 0 V

VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

Input V_M t_W V_M V_I 0 V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
NOTES: A. C L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and t_PHZ are the same as t_dis .
F. t_PZL and t_PZH are the same as t_en .
G. t_PLH and t_PHL are the same as t_pd .
H. All parameters and waveforms are not applicable to all devices.

Figure

1.

Load

Circuit

and

Voltage

TEXAS INSTRUMENTS

www.ti.com

PACKAGE OPTION ADDENDUM

10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status(1)		Package Type	Package Drawing	Pins	Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4-5)	Samples
SN74ALVCH162268DL ACTIVE SSOP DL 56 20 RoHS & Green NIPDAU Level-1 260C-UNLIM -40 to 85 ALVCH162268											Samples
SN74ALVCH162268GR	ACTIVE	TSSOP	DGG	56	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	-40 to 85	ALVCH162268	Samples

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "\~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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TEXAS

INSTRUMENTS

PACKAGE OPTION ADDENDUM

10-Dec-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

Package Drawing

Pins

SPQ Reel

Diameter (mm)

Reel Width W1 (mm)

A0 (mm)

B0 (mm)

K0 (mm)

P1 (mm)

W (mm)

Pin1 Quadrant

SN74ALVCH162268GR

TSSOP DG

G 56 2000

330.0

24.4 8.6

5.6 1.8 12

0 24.0 Q1

TAPE AND REEL BOX DIMENSIONS W L

*All dimensions are nominal

Device	Package Type	Package Drawing	Pins	SPQ	Length (mm)	Width (mm)	Height (mm)
SN74ALVCH162268GR T	SSOP DGG 56 2000	367.0 367.0 45.0

TUBE

T - Tube height L - Tube length W-Tube width B - Alignment groove width

*All dimensions are nominal

Device	Package Name	Package Type	Pins	SPQ	L (mm)	W (mm)	T (μm)	B (mm)
SN74ALVCH162268DL DL	SSOP 56 20 473.7	14.24 5110 7.87

DL (R-PDSO-G56)

PLASTIC SMALL-OUTLINE PACKAGE

0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 0.005 (0,13) 56 29 0.420 (10,67) 0.395 (10,03) 0.299 (7,59) 0.291 (7,39) 1 28 0.730 (18,54) 0.720 (18,29) 0.010 (0,25) 0.005 (0,13) Gage Plane 0°-8° 0.010 (0,25) 0.040 (1,02) 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.008 (0,20) MIN 0.004 (0,10) 4040048-4/F 05/13

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D. Falls within JEDEC MO-118

PowerPAD is a trademark of Texas Instruments.

SMALL OUTLINE PACKAGE

4222167/A 07/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.

SMALL OUTLINE PACKAGE

56X (1.5) 1 56X (0.3) 54X (0.5) (R0.05) TYP 28 SYMM 56 SYMM 29 (7.5)

LAND PATTERN EXAMPLE SCALE:6X

SOLDER MASK OPENING METAL 0.05 MAX ALL AROUND

NON SOLDER MASK DEFINED

METAL UNDER SOLDER MASK SOLDER MASK OPENING 0.05 MIN ALL AROUND

SOLDER MASK DEFINED
SOLDER MASK DETAILS

4222167/A 07/2015

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SMALL OUTLINE PACKAGE

56X (1.5) 1 56X (0.3) 54X (0.5) (R) TYP0.05 28 (7.5) SYMM 56 SYMM 29

SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X

4222167/A 07/2015

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

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