PowerEdge HS5610 - Server DELL - Free user manual and instructions
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| Product Type | Rack Server |
| Form Factor | 2U |
| Dimensions (H x W x D) | 3.4 x 19.0 x 24.0 inches (86.8 x 482.6 x 609.6 mm) |
| Weight | Approximately 35 kg (77.2 lbs) |
| Power Supply | Dual hot-plug redundant PSUs, 1000W typical |
| Processor | Up to two Intel Xeon Scalable Gen 3/4 processors |
| Memory | Up to 3TB DDR5 ECC RDIMM, 16 slots |
| Storage | Up to 10 x 2.5" SAS/SATA/NVMe hot-plug drives |
| RAID Controller | PERC H745 or H755, optional NVMe support |
| Network | Integrated quad-port 1GbE LOM, optional OCP 3.0 |
| Remote Management | iDRAC9 with Lifecycle Controller |
| Expansion Slots | Up to 8 PCIe Gen 4/5 slots |
| Cooling | Hot-plug fans, variable speed |
| Operating Systems Supported | Windows Server, Red Hat Enterprise Linux, SUSE, Ubuntu, VMware vSphere |
| Maintenance | Regularly clean air filters and check fan operation; update firmware via iDRAC |
| Safety Features | Hot-plug redundant components; TPM 2.0; chassis intrusion detection |
| Spare Parts and Repairability | Modular design with hot-swap PSUs, fans, drives; FRUs available from Dell |
| General Information | Intel C620 series chipset; supports up to 3TB RAM; 2U rack form factor |
Frequently Asked Questions - PowerEdge HS5610 DELL
How do I access the iDRAC management interface?
By default, iDRAC is configured with DHCP. Connect a network cable to the dedicated management port and use a browser to access the IP assigned via DHCP. Default login credentials are typically root/calvin.
What processors are compatible with the PowerEdge HS5610?
The server supports Intel Xeon Scalable processors, 3rd or 4th Generation, with LGA 4189 or LGA 4677 socket depending on the model revision. Always refer to the technical specification sheet for exact SKUs.
How can I reset the iDRAC to factory defaults?
You can reset iDRAC via the iDRAC web interface (Configuration → Reset iDRAC to Defaults) or by physically pressing the iDRAC reset button on the system board. Hold the button for 10 seconds until the LED flashes.
What types of drives are supported?
The server supports SAS, SATA, and NVMe drives in 2.5-inch hot-plug form factors. Mixing drive types may require specific backplane configurations and RAID controller compatibility.
How do I configure RAID using the PERC controller?
During boot, press Ctrl+R (for PERC H745/H755) to enter the Option ROM configuration utility. Alternatively, you can use the iDRAC virtual console to launch Dell Lifecycle Controller and set up RAID arrays.
What is the maximum memory capacity?
With 16 DDR5 DIMM slots and 256GB modules, the maximum memory is 3TB. However, actual capacity depends on processor support and DIMM type. Check your processor's memory specifications.
Can I install third-party PCIe cards?
Yes, the server provides up to 8 PCIe slots (Gen 4 or 5). Ensure the card is supported by the operating system and power requirements do not exceed slot limits. Refer to the technical specifications for slot types.
How to perform a system update?
Use Dell Repository Manager or Lifecycle Controller to apply firmware updates. You can also boot to the SUU (Server Update Utility) ISO image. Always backup critical data before updating.
What should I do if the server overheats?
Check the air filters for dust, ensure proper airflow in the rack, and verify all fans are spinning. If a fan fails, replace it immediately (hot-plug). Also, monitor system temperature via iDRAC.
Is the PowerEdge HS5610 compatible with VMware ESXi?
Yes, it is certified for VMware vSphere (ESXi) versions 7.0 and 8.0. Check the VMware Compatibility Guide for exact build numbers and driver requirements.
User questions about PowerEdge HS5610 DELL
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USER MANUAL PowerEdge HS5610 DELL
Statement of Volatility – Dell PowerEdge HS5610
Dell PowerEdge HS5610 contains both volatile and non-volatile (NV) components. Volatile components lose their data immediately upon removal of power from the component. Non-volatile components continue to retain their data even after the power has been removed from the component. Components chosen as user-definable configuration options (those not soldered to the motherboard) are not included in the Statement of Volatility. Configuration option information (pertinent to options such as microprocessors, remote access controllers, and storage controllers) is available by component separately. The following NV components are present in the PowerEdge HS5610 server.
| Item | Non-Volatile or Volatile | Quantity | Reference Designator | Size | Type (e.g. Flash PROM, EEPROM) | Can user programs or operating system write data to it during normal operation? | Purpose? (e.g. boot code) | How is data input to this memory? | How is this memory write protected? | How is the memory cleared? |
| Planar | ||||||||||
| PCH Internal CMOS RAM | Non-Volatile | 1 | U_PCH1 | 256 Bytes | Battery-backed CMOS RAM | No | Real-time clock and BIOS configuration settings | BIOS | N/A – BIOS only control | 1) Set NVRAM_CLR jumper to clear BIOS configuration settings at boot and reboot system. 2) Power off the system, remove coin cell battery for 30 seconds, replace battery and then power back on. 3) Restore default configuration in F2 system setup menu. |
| BIOS SPI Flash | Non-Volatile | 1 | JP45_1 | 32 MB | SPI Flash | No | Boot code, system configuration information, UEFI | SPI Interface via PCH | Software write protected | Not possible with any utilities or applications and system is not functional if corrupted or removed. |
Dell - Internal Use - Confidential
| Item | Non-Volatile or Volatile | Quantity | Reference Designator | Size | Type (e.g. Flash PROM, EEPROM) | Can user programs or operating system write data to it during normal operation? | Purpose? (e.g. boot code) | How is data input to this memory? | How is this memory write protected? | How is the memory cleared? |
| environment, ME | ||||||||||
| BIOS Data SPI Flash | Non-Volatile | 1 | JP8_1 | 4 MB | SPI Flash | No | 4MB Data SPI ROM storage BIOS setting. | SPI interface via PCH | Software write protected | Not possible with any utilities or applications and the system is not functional if BIOS SPI is corrupted or removed. |
| IDRAC SPI Flash | Non-Volatile | 1 | JP46_1 | 4 MB | SPI Flash | No | IDRAC Uboot (boot loader), server management persistent store (i.e. iDRAC boot variables), and virtual planar FRU | SPI interface via iDRAC | Embedded IDRAC subsystem firmware actively controls sub area based write protection as needed. | The user cannot clear memory completely. However, user data, lifecycle log and archive, SEL, and firmware image repository can be cleared using Delete Configuration and Retire System, which can be accessed through the Lifecycle Controller interface. |
| BMC EMMC | Non-Volatile | 1 | U160 | 8 GB | eMMC NAND Flash | No | Operational iDRAC FW, Lifecycle Controller (LC) USC partition, LC service diags, LCOS drivers, USC firmware, IDRAC MAC Address, and EPPID, rac log, System Event Log, lifecycle log cache | NAND Flash interface via iDRAC | Embedded FW write protected | The user cannot clear memory completely. However, user data, lifecycle log and archive, SEL, and firmware image repository can be clearedusing Delete Configuration and Retire System, which can be accessed through the Lifecycle Controller Interface. |
| iDRAC DDR4 | Volatile | 1 | U15 | 8Gb | RAM | Yes | iDRAC RAM | iDRAC firmware | Not write-protected | Remove AC |
| System CPLD RAM | Volatile | 1 | U_CPLD1 | 432 kb | RAM | No | Not utilized | Not utilized | Not accessible | Not accessible |
| System CPLD Flash | Non-Volatile | 1 | U_CPLD1 | 448 kb | FLASH | No | Power on System Firmware | Firmware update | BIOS Security Protocols | Not user clearable |
| CPLD external EEPROM | Non-volatile | 1 | U151 | 2Kb | EEPROM | No | Reserved for OSM using | CPLD | CPLD control | User cannot clear the memory. |
| System Memory: RDIMM | Volatile | Up to 16 | CPU1: A1~A8 CPU2: B1~B8 | Up to 256GB per DIMM | RAM | Yes | System OS RAM | System OS | OS Control | Reboot or power down system |
| CPU VCCIN andFIVRA Regulators | Non-Volatile | 2 | PU56, PU73 | 64KB | OTP (one timeprogrammable) | No | Operational parameters | Once values are loaded into registerspace a cmd writes to nvm. | There are passwords for different sectionsof the register space | The user cannot clear memory. |
| CPU INFAON and VCCFA Regulators | Non-Volatile | 2 | PU68, PU85 | 64KB | OTP (one time programmable) | No | Operational parameters | Once values are loaded into register space a cmd writes to nvm. | There are passwords for different sections of the register space | The user cannot clear memory. |
| Item | Non-Volatile or Volatile | Quantity | Reference Designator | Size | Type (e.g. Flash PROM, EEPROM) | Can user programs or operating system write data to it during normal operation? | Purpose? (e.g. boot code) | How is data input to this memory? | How is this memory write protected? | How is the memory cleared? |
| 4x3.5” SAS/SATA Front Backplane | ||||||||||
| SEP internal flash | Non-Volatile | 1 | U46 | Flash: 4MbData SRAM : 256KBBattery Powered Storage SRAM : 64B | Integrated Flash + Data SRAM + BatteryPowered Storage SRAM | No | Firmware + FRU | I2C interface via iDRAC | Program write protect bit | Not user clearable |
| 8x2.5" SAS/SATA Front Backplane | ||||||||||
| SEP internal flash | Non-Volatile | 1 | U46 | Flash: 4MbData SRAM : 256KBBattery Powered Storage SRAM : 64B | Integrated Flash + Data SRAM + Battery Powered Storage SRAM | No | Firmware + FRU | I2C interface via IDRAC | Program write protect bit | Not user clearable |
| 10x2.5" Universal Front Backplane | ||||||||||
| SEP internal flash | Non-Volatile | 1 | U14 | Flash: 512KBData SRAM : 256KBBattery Powered Storage SRAM : 64B | Integrated Flash + Data SRAM + Battery Powered Storage SRAM | No | Firmware + FRU | I2C interface via iDRAC | Program write protect bit | Not user clearable |
| 6x2.5" Universal Front Backplane | ||||||||||
| SEP internal flash | Non-Volatile | 1 | U9 | Flash: 512KBData SRAM : 256KBBattery Powered StorageSRAM : 64B | Integrated Flash + Data SRAM + Battery Powered Storage SRAM | No | Firmware + FRU | I2C interface via iDRAC | Program write protect bit | Not user clearable |
| 2x2.5" Universal Rear Backplane | ||||||||||
| SEP Internal flash | Non-Volatile | 1 | U47 | Flash: 512KBData SRAM : 256KBBattery Powered Storage SRAM : 64B | Integrated Flash + Data SRAM + Battery Powered Storage SRAM | No | Firmware + FRU | I2C interface via IDRAC | Program write protect bit | Not user clearable |
| H965i Front PERC (Internal Controller) | ||||||||||
| SPI Flash | Non-Volatile | 1 | U2 | 256Mb | SPI Flash | No | Card firmware | Pre-programmed before assembly. Can be updated using Dell/Broadcom tools | Not write protected. Not visible to Host Processor | User cannot clear the memory. |
| FRU | Non-volatile | 1 | U1019 | 2Kb | EEPROM | No | Card manufacturing information | Programmed at ICT during production. | Not write protected | User cannot clear the memory. |
| CPLD | Non-volatile | 1 | U1088 | 64kb | Flash | No | Power sequencing and Cache Offload | Controller may program data during FW update | Not write protectedNot visible to host CPU | User cannot clear this memory |
| MCU | Non-volatile | 1 | U41 | 8kB | Flash | No | PCIe Bifurcation information to system iDRAC | BMC may program data if there is an updated version packaged with iDRAC | Not write protected Not visible to host CPU | User cannot clear this memory |
| NVSRAM | Non-volatile | 1 | U1087 | 128kB | NVSRAM | No | Configuration data | ROC writes configuration data to NVSRAM | Not write protected Not visible to host CPU | User cannot clear this memory |
| BMU | Non-Volatile | 1 | U1126 | 180KB | Integrated Flash + EEPROM | No | Battery Management control | ROC may program data during FW and during boot | Not write protected | User cannot clear this memory |
| SPD | Non-volatile | 1 | U22 | 256b | EEPROM | No | Memory configuration data | Pre-programmed before assembly | No write protected. Not visible to Host Processor | User cannot clear the memory. |
| NAND Flash | Non-volatile | 1 | U1100 | 512Gb | ONFI Flash | No | Cache offload during unexpected power loss | Programmed by ROC during cache offload | No write protected. Not visible to Host Processor | User cannot clear the memory. |
| SDRAM | Volatile | 9 | U1077~U1086 | 8GB | SDRAM | No | Cache for HDD I/O | ROC writes to this memory - using it as cache for data IO to HDDs | No write protected. Not visible to Host Processor | Cache can be cleared by powering off the card |
| Item | Non-Volatile or Volatile | Quantity | Reference Designator | Size | Type (e.g. Flash PROM, EEPROM) | Can user programs or operating system write data to it during normal operation? | Purpose? (e.g. boot code) | How is data input to this memory? | How is this memory write protected? | How is the memory cleared? |
| H755 Front PERC (Internal Controller) | ||||||||||
| SDRAM | Volatile | 9 | U1077~U1085 | 8GB | SDRAM | No | Cache for HDD I/O | ROC writes to this memory - using it as cache for data IO to HDDs | no write protected. Not visible to Host Processor | Cache can be cleared by powering off the card |
| NV Flash | Non-volatile | 1 | U1100 | 512Gb | SPI Flash | No | Card firmware | Pre-programmed before assembly. Canbe updated using Dell/LSI tools | no write protected. Not visible to Host Processor | User cannot clear the memory. |
| BMU | Non-Volatile | 1 | U1126 | 180KB | Integrated Flash + EEPROM | No | Battery Management Control | ROC may program data during FW and during boot during battery detection | Not write protected Not visible to host CPU | User cannot clear this memory |
| SPI Flash | Non-Volatile | 1 | U1086 | 128Mb | SPI Flash | No | Holds cache data during power loss | FPGA backs up DDR data to this device in case of a power failure | no write protected. Not visible to Host Processor | Flash can be cleared by powering up the card and allowing the controller to flush the contents to VDs. If the VDs are no longer available, cache can be cleared by going into controller BIOS and selecting Discard Preserved Cache. |
| NVSRAM | Non-volatile | 1 | U1087 | 128KB | NVSRAM | No | Configuration data | ROC writes configuration data to NVSRAM | no write protected. Not visible to Host Processor | User cannot clear the memory. |
| FRU | Non-volatile | 1 | U1019 | 2Kb | EEPROM | No | Card manufacturing information | Programmed at ICT during production. | no write protected | User cannot clear the memory. |
| SPD | Non-volatile | 1 | U22 | 2Kb | EEPROM | No | Memory configuration data | Pre-programmed before assembly | no write protected. Not visible to Host Processor | User cannot clear the memory. |
| CPLD | Non-volatile | 1 | U1088 | 64kb | Flash | No | Power sequencing and Cache Offload | ROC may program data during FW update | Not write protectedNot visible to host CPU | User cannot clear this memory |
| MCU | Non-volatile | 1 | U41 | 8KB | EEPROM | No | PCIe Bifurcation information to system iDRAC | BMC may program data if there is an updated version packaged with iDRAC | Not write protectedNot visible to host CPU | User cannot clear this memory |
| H755N Front PERC (Internal Controller) | ||||||||||
| NVSRAM | Non-volatile | 1 | U1087 | 128KB | NVSRAM | No | Configuration data | ROC writes configuration data to NVSRAM | No write protected. Not visible to Host Processor | User cannot clear the memory. |
| FRU | Non-volatile | 1 | U1019 | 2Kb | EEPROM | No | Card manufacturing information | Programmed at ICT during production. | No write protected | User cannot clear the memory. |
| SPD | Non-volatile | 1 | U1019 | 2Kb | EEPROM | No | Memory configuration data | Pre-programmed before assembly | No write protected. Not visible to Host Processor | User cannot clear the memory. |
| NV Flash | Non-volatile | 1 | U1100 | 512Gb | SPI Flash | No | Card firmware | Pre-programmed before assembly. Can be updated using Dell/LSI tools | No write protected. Not visible to Host Processor | User cannot clear the memory. |
| CPLD | Non-volatile | 1 | U1088 | 64kb | Flash | No | Power sequencing and Cache Offload | NA | NA | NA |
| SPI Flash | Non-Volatile | 1 | U1086 | 128Mb | SPI Flash | No | Holds cache data during power loss | FPGA backs up DDR data to this device in case of a power failure | No write protected. Not visible to Host Processor | Flash can be cleared by powering up the card and allowing the controller to flush the contents to VDs. If the VDs are no longer available, cache can be cleared by going into controller BIOS andselecting Discard Preserved Cache. |
| SDRAM | Volatile | 9 | U1077~U10 85 | 8GB | SDRAM | No | Cache for HDD I/O | ROC writes to this memory - using it as cache for data IO to HDDs | No write protected. Not visible to Host Processor | Cache can be cleared by powering off the card |
| MCU | Non-volatile | 1 | U41 | 8KB | EEPROM | No | PCIe Bifurcation information to system iDRAC | NA | NA | NA |
| BMU | Non-Volatile | 1 | U1126 | 180KB | NA | No | Battery Management control | NA | NA | NA |
| HBA355i Front (Internal Controller) | ||||||||||
| SPI Flash | Non-Volatile | 1 | U2 | 128Mb | SPI Flash | No | Card firmware | Pre-programmed before assembly. Can be updated using Dell/LSI tools | Not write protected. Not visible to Host Processor | User cannot clear the memory. |
| FRU | Non-volatile | 1 | U5 | 2Kb | EEPROM | No | Card manufacturing information | Programmed at ICT during production. | Not write protected | User cannot clear the memory. |
| CPLD | Non-volatile | 1 | U23 | 24kb | Flash | No | Power sequencing and Cache Offload | Controller may program data during FW update | Not write protectedNot visible to host CPU | User cannot clear this memory |
| MCU | Non-volatile | 1 | U41 | 8kB | EEPROM | No | PCIe Bifurcation information to system iDRAC | BMC may program data if there is an updated version packaged with iDRAC | Not write protectedNot visible to host CPU | User cannot clear this memory |
| H355 Front PERC (Internal Controller) | ||||||||||
| SPI Flash | Non-Volatile | 1 | U2 | 128Mb | SPI Flash | No | Card firmware | Pre-programmed before assembly. Can be updated using Dell/LSI tools | Not write protected. Not visible to Host Processor | User cannot clear the memory. |
| FRU | Non-volatile | 1 | U5 | 2Kb | EEPROM | No | Card manufacturing information | Programmed at ICT during production. | Not write protected | User cannot clear the memory. |
| NVSRAM | Non-volatile | 1 | U3 | 128kB | NVSRAM | No | Configuration data | ROC writes configuration data to NVSRAM | Not write protectedNot visible to host CPU | User cannot clear this memory |
| Status LED Control Panel | ||||||||||
| Microcontroller | Non-Volatile | 1 | U_TINY | 8KB | Flash | No | Driving Health and Status LED | I2C via iDRAC | Hardware strapping | User cannot clear the memory. |
| TPM | ||||||||||
| Trusted Platform Module (TPM) | Non-Volatile | 1 | U2 | 128 Bytes | EEPROM | Yes | Storage of encryption keys | Using TPM Enabled operating systems | SW write protected | F2 Setup option |
| Power Button Control Panel | ||||||||||
| SPI Flash | Non-Volatile | 1 | U2 | 32 Mb | SPI Flash | No | EasyRestore functionality contains Service Tag, Copy of SEL logs | SPI Interface from iDRAC to Right Cntl Panel | Embedded iDRAC subsystem firmware actively controls sub area based write protection as needed. | The user cannot clear memory. |
| BOSS-N1 | ||||||||||
| RAID controller external SPI FLASH | Non-Volatile | 1 | U5 | 128Mb | FLASH EEPROM | No | Boot code, FW | By programming the image via firmware update process | N/A | Use Flash tool, type “go.nsh w y” |
| MCU | Non-volatile | 1 | U41 | 8KB | User cannot clear the memory | |||||
| FRU | Non-Volatile | 1 | U4 | 2Kb | FLASH EEPROM | No | Card manufacturing information | During Manufacturing, by programming the image via firmware update process. During runtime, by I2C Proprietary Command Protocol | N/A | By writing to Flash |
| Left Titan2 | ||||||||||
| MCU | Non-volatile | 1 | USAM7 | 2048kB | Flash ROM | No | Driving Health/ Status LED and Wifi-BT communication. | SPI interface via iDRAC | Hardware strapping | User cannot clear the memory. |
| R1A/R1B/R2C/R2D/R2E | ||||||||||
| MCU | Non-volatile | 1 | U1 | 8kB | Flash ROM | No | Riser information | The data is flash via iDRAC auto update | No write protected. Not visible to Host Processor | User cannot clear the memory. |
| R2A | ||||||||||
| MCU | Non-volatile | 1 | U2 | 8kB | Flash ROM | No | Riser information | The data is flash via iDRAC auto update | No write protected. Not visible to Host Processor | User cannot clear the memory. |
| FLOP | ||||||||||
| MCU | Non-volatile | 1 | U29 | 8kB | Flash ROM | No | Riser information | The data is flash via iDRAC auto update | No write protected. Not visible to Host Processor | User cannot clear the memory. |
| CPLD | Non-volatile | 1 | U30 | 24kb | Flash ROM | No | Power sequencing and Cache Offload | Controller may program data during FW update | No write protected. Not visible to Host Processor | User cannot clear this memory |
| Front USB NIC | ||||||||||
| Microcontroller | Non-volatile | 1 | U1 | 1kB | OTP (one time programmable) | No | Operational parameters | Once values are loaded into register space a cmd writes to nvm. | N/A | The user cannot clear memory. |
| PSU | ||||||||||
| DELTA PSU (600W, 700W, 800W, 1100W, 1400W, 1800W) | ||||||||||
| Primary MCU | Non-volatile | 1 | IC703 | 64KB | Internal Flash | No | Boot code, FW | The data is flash via Dell Update Package (DUP) | SW write protected | Before firmware update, the memory will be cleared. |
| Secondary MCU | Non-volatile | 1 | IC805 | 64KB | Internal Flash | No | Boot code, FW | The data is flash via Dell Update Package (DUP) | SW write protected | Before firmware update, the memory will be cleared. |
| FRU | Non-volatile | 1 | IC704 | 16KB | EEPROM | No | PSU information | During Manufacturing, by programming the image via firmwareupdate process | SW write protected | User cannot clear the memory. |
| ARTESYN PSU (800W, 1100W, 1400W) | ||||||||||
| Primary MCU | Non-volatile | 1 | U317 (TI) | 64K | Internal Flash | No | Boot code, FW | The data is flash via Dell Update Package (DUP) | SW write protected | Before firmware update, the memory will be cleared. |
| Secondary MCU | Non-volatile | 2 | U301 (TI ) U315 (ST ) | 32K 128K | Internal Flash | No | Boot code, FW | The data is flash via Dell Update Package (DUP) | SW write protected | Before firmware update, the memory will be cleared. |
| FRU | Non-volatile | 1 | U305 | 2Mb | SERIAL FLASH | No | PSU information | During Manufacturing | SW write protected | User cannot clear the memory. |
| LiteOn PSU (600W, 700W, 800W, 1100W, 1400W, 1800W) | ||||||||||
| Primary MCU | Non-volatile | 1 | IC050 | 64K | Internal Flash | No | Boot code, FW | The data is flash via Dell Update Package (DUP) | SW write protected | Before firmware update, the memory will be cleared. |
| Secondary MCU/FRU | Non-volatile | 1 | IC900 | 128K | Internal Flash | No | Boot code, FW | The data is flash via Dell Update Package (DUP) | SW write protected | Before firmware update, the memory will be cleared. |
NOTE: For any information that you may need, direct your questions to your Dell Marketing contact.