SN74ALS138AN - Elektronisk komponent TEXAS INSTRUMENTS - Gratis brugsanvisning og manual

BRUGSANVISNING SN74ALS138AN TEXAS INSTRUMENTS

• Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems
  ● Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception
  ● Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

description

The 'ALS138A and 'AS138 are 3-line to 8-line decoders/demultiplexers designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance systems, these devices can be used to minimize the effects of system decoding. When employed with high-speed memories with a fast enable circuit, the delay times of the decoder and the enable time of the memory are usually less than the typical access time of the memory. The effective system delay introduced by the Schottky-clamped system decoder is negligible.

The conditions at the binary-select (A, B, and C) inputs and the three enable (G1, G2A, and G2B) inputs select one of eight output lines. Two active-low and one active-high enable inputs

SN54ALS138A, SN54AS138...J PACKAGE SN74ALS138A, SN74AS138...D OR N PACKAGE (TOP VIEW)

A 1 16 VCC B 2 15 Y0 C 3 14 Y1 G2A 4 13 Y2 G2B 5 12 Y3 G1 6 11 Y4 Y7 7 10 Y5 GND 8 9 Y6

SN54ALS138A, SN54AS138 ... FK PACKAGE (TOP VIEW)

B A NC VCC Y0 3 2 1 20 19 C 4 18 Y1 G2A 5 17 Y2 NC 6 16 NC G2B 7 15 Y3 G1 8 14 Y4 9 1 0 1 1 1 2 3 Y7 GND NC Y6 Y5

NC - No internal connection

reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

The SN54ALS138A and SN54AS138 are characterized for operation over the full military temperature range of -55^ to 125^ . The SN74ALS138A and SN74AS138 are characterized for operation from 0^ to 70^ .

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SDAS055E – APRIL 1982 – REVISED JULY 1996

FUNCTION TABLE

INPUTS

OUTPUTS

ENABLE SELECT

G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

X H X X X X H H H H

X X

H

X

X

X

H

H

H

H

H

H

H

H

H

L

X

X

X

X

X

H

H

H

H

H

H

H

H

H

L

L

L

L

L

L

H

H

H

H

H

H

H

H

L

L

L

L

H

H

L

H

H

H

H

H

H

H

L

L

L

H

L

H

H

L

H

H

H

H

H

H

L

L

L

H

H

H

H

H

L

H

H

H

H

H

L

L

H

L

L

H

H

H

H

L

H

H

H

H

L

L

H

L

H

H

H

H

H

H

L

H

H

H

L

L

H

H

L

H

H

H

H

H

H

L

H

H

L

L

H

H

H

H

H

H

H

H

H

H

L

logic symbols (alternatives)†

BIN/OCT A 1 B 2 C 3 G1 6 G2A 4 G2B 5 EN 0 15 Y0 1 14 Y1 1 13 Y2 2 12 Y3 3 11 Y4 4 10 Y5 5 9 Y6 6 7 Y7 7

DMUX G 0/7 A 1 B 2 C 3 G1 6 G2A 4 G2B 5 & 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 7 Y7

^ These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.

logic diagram (positive logic)

graph TD
    A["Select Inputs"] -->|A 1| NOT1["NOT"]
    B["Select Inputs"] -->|B 2| NOT2["NOT"]
    C["Select Inputs"] -->|C 3| NOT3["NOT"]
    NOT1 --> AND1["AND"]
    NOT2 --> AND1
    NOT3 --> AND2["AND"]
    NOT1 --> AND2
    NOT2 --> AND2
    NOT3 --> AND3["AND"]
    AND1 --> OR1["OR"]
    AND2 --> OR1
    AND3 --> OR1
    OR1 --> Y0["15 Y0"]
    A --> NOT1
    B --> NOT2
    C --> NOT3
    NOT1 --> AND1
    NOT2 --> AND2
    NOT3 --> AND3
    AND1 --> OR2["OR"]
    AND2 --> OR2
    AND3 --> OR2
    OR2 --> Y1["14 Y1"]
    OR2 --> Y2["13 Y2"]
    OR2 --> Y3["12 Y3"]
    OR2 --> Y4["11 Y4"]
    OR2 --> Y5["10 Y5"]
    OR2 --> Y6["9 Y6"]
    OR2 --> Y7["7 Y7"]
    G["Enable Inputs"] --> G2A["G2A 4"]
    G --> G2B["G2B 5"]
    G --> G1["G1 6"]
    G2A --> AND4["AND"]
    G2B --> AND4
    G1 --> AND4
    AND4 --> OR3["OR"]
    OR3 --> Y0
    OR3 --> Y1
    OR3 --> Y2
    OR3 --> Y3
    OR3 --> Y4
    OR3 --> Y5
    OR3 --> Y6
    OR3 --> Y7

Pin numbers shown are for the D, J, and N packages.

SDAS055E – APRIL 1982 – REVISED JULY 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage, V_CC 7 V

Input voltage, V_I 7 V

Operating free-air temperature range, T_A : SN54ALS138A -55^ to 125^

SN74ALS138A 0°C to 70°C

Storage temperature range, T_stg –65°C to 150°C

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

		SN54ALS138A SN7			IALS138A			UNIT
		MIN NOM	MAX		MIN NOM	MAX
V_CC	Supply voltage	4.5	5	5.5	4.5	5	5.5	V
V_IH	High-level input voltage	2			2			V
V_IL	Low-level input voltage			0.7			0.8	V
I_OH	High-level output current			-0.4			-0.4	mA
I_OL	Low-level output current			4			8	mA
T_A	Operating free-air temperature	-55		125	0		70	°C

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS		SN54ALS138A SN7			ALS138A			UNIT
			MIN	TYP‡	MAX	MIN	TYP‡	MAX
V_IK	V_CC = 4.5 V, I_I = -18 mA				-1.5			-1.5	V
V_OH	V_CC = 4.5 V, I_OH = -0.4 mA		V_CC -2			V_CC -2			V
V_OL	V_CC = 4.5 V	I_OL = 4 mA		0.25	0.4		0.25	0.4	V
		I_OL = 8 mA					0.35	0.5
I_I	V_CC = 5.5 V, V_I = 7 V				0.1			0.1	mA
I_IH	V_CC = 5.5 V, V_I = 2.7 V				20			20	A
I_IL	V_CC = 5.5 V, V_I = 0.4 V				-0.1			-0.1	mA
I_O^S	V_CC = 5.5 V, V_O = 2.25 V		-20		-112	-30		-112	mA
I_CC	V_CC = 5.5 V			5	10		5	10	mA

All typical values are at V_CC = 5V, T_A = 25^ C .
§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.

switching characteristics (see Figure 1)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	V_CC = 4.5 V to 5.5 V, C_L = 50 pF, R_L = 500 , T_A = MIN to MAX				UNIT
			SN54ALS138A		SN74ALS138A
			MIN	MAX	MIN	MAX
t_PLH	A,B,C	Any Y	2	28	5	22	ns
t_PHL			6	22	6	18
t_PLH	G or	Any Y	2	22	3	17	ns
t_PHL			4	21	4	17

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage, V_CC 7 V

Input voltage, V_I 7 V

Operating free-air temperature range, T_A : SN54AS138 -55^ to 125^

SN74AS138 0°C to 70°C

Storage temperature range, T_stg –65°C to 150°C

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

		SN54AS138 SN74			AS138			UNIT
		MIN NOM	MAX		MIN NOM	MAX
V_CC	Supply voltage	4.5	5	5.5	4.5	5	5.5	V
V_IH	High-level input voltage	2			2			V
V_IL	Low-level input voltage			0.8			0.8	V
I_OH	High-level output current			-2			-2	mA
I_OL	Low-level output current			20			20	mA
T_A	Operating free-air temperature	-55		125	0		70	°C

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS		SN54AS138 SN74			AS138			UNIT
			MIN	TYP‡	MAX	MIN	TYP‡	MAX
V_IK	V_CC = 4.5 V, I_I = -18 mA				-1.2			-1.2	V
V_OH	V_CC = 4.5 V to 5.5 V, I_OH = -2 mA		V_CC - 2			V_CC - 2			V
V_OL	V_CC = 4.5 V, I_OL = 20 mA			0.35	0.5		0.35	0.5	V
I_I	V_CC = 5.5 V, V_I = 7 V				0.1			0.1	mA
I_IH	V_CC = 5.5 V, V_I = 2.7 V				20			20	A
I_IL	V_CC = 5.5 V, V_I = 0.4 V				-0.5			-0.5	mA
I_O^S	V_CC = 5.5 V, V_O = 2.25 V		-30		-112	-30		-112	mA
I_CCH	V_CC = 5.5 V			12	17.5		12	17.5	mA
I_CCL	V_CC = 5.5 V			14	20		14	20	mA

All typical values are at V_CC=5V,T_A=25^ .
§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.

SDAS055E – APRIL 1982 – REVISED JULY 1996

switching characteristics (see Figure 1)

PARAMETER	FROM(INPUT)	TO(OUTPUT)	V_CC = 4.5 V to 5.5 V, C_L = 50 pF, R_L = 500 , T_A = MIN to MAX		UNIT
			SN54AS138 S	N74AS138
			MIN MAX MIN	MAX
t_PLH	A, B, C	Any Y	2 11 2 10		ns
t_PHL			2 11 29.5
t_PLH	G1	Any Y	2 11.5 2 10		ns
t_PHL			2 11 2 10
t_PLH	2	Any Y	2 9 2 7.5		ns
t_PHL			2 10 2 8.5

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES

NOTES: A. C L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t_r = t_f = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

PACKAGING INFORMATION

Orderable Device Status(1)	Package Type Package Drawing		Pins	Package Qty	Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4,5)	Samples
5962-86866012A ACTIVE LCCC FK 20 1 Non-RoHS					& Green	SNPB N / A for Pkg Type -55 to 125 5962-			86866012ASNJ54ALS138AFK	Samples
5962-8686601FA ACTIVE CFP W 16 1 Non-RoHS					& Green	SNPB N / A for Pkg Type -55 to 125 5962-8686601FA			SNJ54ALS138AW	Samples
JM38510/37701B2A ACTIVE LCCC FK 20 1 Non-RoHS					& Green	SNPB N / A for Pkg Type JM38510/			37701B2A	Samples
JM38510/37701BEA ACTIVE CDIP J 16 1 Non-RoHS					& Green	SNPB N / A for Pkg Type JM38510/			37701BEA	Samples
M38510/37701B2A	ACTIVE LCCC FK 20 1 Non-RoHS				& Green	SNPB N / A for Pkg Type -55 to 125 JM38510/			37701B2A	Samples
M38510/37701BEA	ACTIVE CDIP J 16 1 Non-RoHS				& Green	SNPB N / A for Pkg Type -55 to 125 JM38510/			37701BEA	Samples
SN54ALS138AJ	ACTIVE CDIP J 16 1 Non-RoHS				& Green	SNPB N / A for Pkg Type SN54ALS138AJ				Samples
SN54AS138J	ACTIVE CDIP J 16 1 Non-RoHS				& Green	SNPB N / A for Pkg Type -55 to 125 SN54AS138J				Samples
SN74ALS138AD	ACTIVE	SOIC	D	16	40	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	0 to 70	ALS138A
SN74ALS138ADE4	ACTIVE	SOIC	D	16	40	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	0 to 70	ALS138A
SN74ALS138ADG4	ACTIVE	SOIC	D	16	40	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	0 to 70	ALS138A
SN74ALS138ADR	ACTIVE	SOIC	D	16	2500	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	0 to 70	ALS138A
SN74ALS138ADRG4	ACTIVE	SOIC	D	16	2500	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	0 to 70	ALS138A
SN74ALS138AN	ACTIVE	PDIP	N	16	25	RoHS & Green	NIPDAU	N / A for Pkg Type	0 to 70	SN74ALS138AN
SN74ALS138ANSR	ACTIVE	SO	NS	16	2000	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	0 to 70	ALS138A
SN74AS138D	ACTIVE	SOIC	D	16	40	RoHS & Green	NIPDAU	Level-1-260C-UNLIM	0 to 70	AS138
SN74AS138N	ACTIVE	PDIP	N	16	25	RoHS & Green	NIPDAU	N / A for Pkg Type	0 to 70	SN74AS138N
Orderable Device Status(1)	Package Type Package Drawing		Pins Package Qty		Eco Plan(2)	Lead finish/ Ball material(6)	MSL Peak Temp(3)	Op Temp (°C)	Device Marking(4-5)	Samples
SN74AS138NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 74AS138										Samples
SNJ54ALS138AFK ACTIVE LCCC FK 20 1 Non-RoHS						& Green	SNPB N / A for Pkg Type	-55 to 125	5962-86866012ASNJ54ALS138AFK	Samples
SNJ54ALS138AJ	ACTIVE	CDIP	J	16	1	Non-RoHS & Green	SNPB N / A for Pkg Type	-55 to 125	SNJ54ALS138AJ	Samples
SNJ54ALS138AW	ACTIVE	CFP	W	16	1	Non-RoHS & Green	SNPB N / A for Pkg Type	-55 to 125	5962-8686601FASNJ54ALS138AW	Samples
SNJ54AS138FK	ACTIVE LCCC FK 20 1 Non-RoHS					& Green	SNPB N / A for Pkg Type	-55 to 125	SNJ54AS138FK	Samples
SNJ54AS138J	ACTIVE	CDIP	J	16	1	Non-RoHS & Green	SNPB N / A for Pkg Type	-55 to 125	SNJ54AS138J	Samples

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "-" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54ALS138A, SN54AS138, SN74ALS138A, SN74AS138 :

• Catalog : SN74ALS138A, SN74AS138

• Military : SN54ALS138A, SN54AS138

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

Package Drawing

Pins

SPQ Reel

Diameter (mm)

Reel Width W1 (mm)

A0 (mm)

B0 (mm)

K0 (mm)

P1 (mm)

W (mm)

Pin1 Quadrant

SN74ALS138ADR SO

C D 16 25

00 330.0 1

6.4 6.5

10.3 2.1

8.0 16.0 Q1

SN74ALS138ANSR SO

NS 16 20

00 330.0 1

6.4 8.2

10.5 2.5

12.0 16.0 Q1

SN74AS138NSR SO

NS 16 2000

00 330.0 16

4.8 45

10.55 2.5

12.0 16.2 Q1

TAPE AND REEL BOX DIMENSIONS W L

*All dimensions are nominal

Device	Package Type	Package Drawing	Pins	SPQ	Length (mm)	Width (mm)	Height (mm)
SN74ALS138ADR SOI	C D 16 2500 340.5	336.1 32.0
SN74ALS138ANSR SO	NS 16 2000 853.0	449.0 35.0
SN74AS138NSR	SO NS 16	2000 853.0 449.0 35.0

TUBE

T - Tube height W-Tube width L - Tube length B - Alignment groove width

*All dimensions are nominal

Device	Package Name	Package Type	Pins	SPQ	L (mm)	W (mm)	T (μm)	B (mm)
5962-86866012A FK L	CCC 20 1 506.98 12	2.06 2030 NA
JM38510/37701B2A FK	LCCC 20 1 506.98	2.06 2030 NA
M38510/37701B2A FK	CCC 20 1 506.98 12	2.06 2030 NA
SN74ALS138AD	D	SOIC	16	40	507	8	3940	4.32
SN74ALS138ADE4	D	SOIC	16	40	507	8	3940	4.32
SN74ALS138ADG4	D	SOIC	16	40	507	8	3940	4.32
SN74ALS138AN	N	PDIP	16	25	506	13.97	11230	4.32
SN74ALS138AN	N	PDIP	16	25	506	13.97	11230	4.32
SN74AS138D	D	SOIC	16	40	507	8	3940	4.32
SN74AS138N	N	PDIP	16	25	506	13.97	11230	4.32
SN74AS138N	N	PDIP	16	25	506	13.97	11230	4.32
SNJ54ALS138AFK FK	CCC 20 1 506.98 12	2.06 2030 NA
SNJ54AS138FK	FK LCCC 20 1 506.98 12.06 2030 NA

W (R-GDFP-F16)

CERAMIC DUAL FLATPACK

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification only.

E. Falls within MIL STD 1835 GDFP2-F16

B 14 8 C 1 0.065 (1,65) 0.045 (1,14)

DIM\PINS **	14	16	18	20
A	0.300(7,62)BSC	0.300(7,62)BSC	0.300(7,62)BSC	0.300(7,62)BSC
B MAX	0.785(19,94)	.840(21,34)	0.960(24,38)	1.060(26,92)
B MIN	—	—	—	—
C MAX	0.300(7,62)	0.300(7,62)	0.310(7,87)	0.300(7,62)
C MIN	0.245(6,22)	0.245(6,22)	0.220(5,59)	0.245(6,22)

0.005 (0,13) MIN 0.060 (1,52) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.026 (0,66) 0.014 (0,36) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) A 0°-15°

4040083/F 03/03

NOTES:

A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package is hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18 and GDIP1-T20.

N (R-PDIP-T\*\*)

16 PINS SHOWN

PLASTIC DUAL-IN-LINE PACKAGE

A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) 0.045 (1,14)

C

DIM\PINS **	14	16	18	20
A MAX	0.775(19,69)	0.775(19,69)	0.920(23,37)	1.060(26,92)
A MIN	0.745(18,92)	0.745(18,92)	0.850(21,59)	0.940(23,88)
MS-001VARIATION	AA	BB	AC	AD

0.045 (1,14) 0.030 (0,76) D 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) ⊕ 0.010 (0,25) M 14/18 Pin Only 20 Pin vendor opt

0.325 (8,26) 0.300 (7,62) 0.015 (0,38) Gauge Plane 0.010 (0,25) NOM 0.430 (10,92) MAX

4040049/E 12/2002

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C Falls within JEDEC MS-001, except 18 and 20 pin minimum body length (Dim A).

The 20 pin end lead shoulder width is a vendor option, either half or full width.

SOP

4220735/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

SOP

16X (1.85) 1 16X (0.6) SYMM SEE DETAILS 16 SYMM 14X (1.27) 8 (R0.05) TYP 9 (7)

LAND PATTERN EXAMPLE SCALE:7X

METAL SOLDER MASK OPENING 0.07 MAX ALL AROUND

NON SOLDER MASK DEFINED

SOLDER MASK OPENING METAL 0.07 MIN ALL AROUND

SOLDER MASK DEFINED
SOLDER MASK DETAILS

4220735/A 12/2021

NOTES: (continued)

1. Publication IPC-7351 may have alternate designs.
2. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SOP

16X (1.85) 1 16X (0.6) 14X (1.27) 8 (R0.05) TYP SYMM 16 SYMM 9 (7)

SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X

4220735/A 12/2021

NOTES: (continued)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.

FK (S-CQCC-N**)

28 TERMINAL SHOWN

LEADLESS CERAMIC CHIP CARRIER

NO. OF TERMINALS**	A		B
	MIN	MAX	MIN	MAX
20	0.342(8,69)	0.358(9,09)	0.307(7,80)	0.358(9,09)
28	0.442(11,23)	0.458(11,63)	0.406(10,31)	0.458(11,63)
44	0.640(16,26)	0.660(16,76)	0.495(12,58)	0.560(14,22)
52	0.740(18,78)	0.761(19,32)	0.495(12,58)	0.560(14,22)
68	0.938(23,83)	0.962(24,43)	0.850(21,6)	0.858(21,8)
84	1.141(28,99)	1.165(29,59)	1.047(26,6)	1.063(27,0)

4040140/D 01/11
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. Falls within JEDEC MS-004

D (R-PDSO-G16)
PLASTIC SMALL OUTLINE

0.394 (10,00) 0.386 (9,80) 16 9 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,80) Pin 1 Index Area 1 8 0.050 (1,27) 0.020 (0,51) 0.012 (0,31) ⊕ 0.010 (0,25) M 0.069 (1,75) Max 0.010 (0,25) 0.004 (0,10) Gcuge Plane 0.010 (0,25) 0.005 (0,13) 0'-8" Seating Plane 0.010 (0,25) 0.050 (1,27) 0.016 (0,40) 4040047-6/M 06/11

NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.006 (0,15) each side.
Body width does not include interlead flash. Interlead flash shall not exceed 0.017 (0,43) each side.
E. Reference JEDEC MS-012 variation AC.

D (R-PDSO-G16)

PLASTIC SMALL OUTLINE

Example Board Layout (Note C) 14x1,27 5,40 Example Non Soldermask Defined Pad 1,55 0,60 0,07 All Around Stencil Openings (Note D) 16x0,55 16x1,50 14x1,27 5,40 Example Pad Geometry (See Note C) Example Solder Mask Opening (See Note E)

4211283-4/E 08/12
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Publication IPC-7351 is recommended for alternate designs.
D. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.
E. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.

MECHANICAL DATA

NS (R-PDSO-G\*\*)

PLASTIC SMALL-OUTLINE PACKAGE

14-PINS SHOWN

1,27 14 0,51 0,35 Ø 0,25① 8 5,60 5,00 8,20 7,40 1 7 A

0,15 NOM Gage Plane 0,25 0°-10° 1,05 0,55

2,00 MAX 0,15 0,05

Seating Plane 0.10

DIM\PINS **	14	16	20	24
A MAX	10,50	10,50	12,90	15,30
A MIN	9,90	9,90	12,30	14,70

4040062/C 03/03

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.

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